JPH0223774A - Picture synthesizing device - Google Patents

Abstract

PURPOSE:To reduce the capacity of a picture memory by making the quantized number of second picture data one bit fewer than the quantized number of first picture data, and allotting an identification bit to said one bit. CONSTITUTION:The first picture data of n bits is stored previously in the picture memory 1, and the second picture data of n-1 bits is stored previously in the picture memory 2. Then, an address generator 3 is started to operate, and the picture data to be outputted respectively from the memories 1 and 2 are read out at a time. When MSB of the data outputted from the memory 2 is '1', a selector 4 selects the first picture data to be outputted from the memory 1. When MSB of the data outputted from the memory 2 is '0', the selector 4 selects the second picture data to be outputted from the memory 2. By an above-mentioned operation, the first and the second picture data to be outputted respectively from the memories 1 and 2 are synthesized.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image synthesizing apparatus for synthesizing two digital images in a copying machine, a facsimile machine, or the like.

2. Description of the Related Art Recently, in high-performance copying machines, facsimile machines, etc., it has become common to combine two images to obtain a third image.

Hereinafter, a conventional image synthesizing device will be explained with reference to FIG. In FIG. 4, 1 is composed of M×N pixels,
and the quantization number of one pixel is expressed by n bits.
The first image memory 2 has a capacity for storing image data of In order to store data obtained by adding 1 bit of identification bit, that is, data represented by n + 1 bits, 3.
\-/ a second image memory with a capacity of This is a selector for switching the second image data output from 2, and has a selection control terminal 41. Further, FIG. 5 shows the data structure of data representing one pixel in image memory 1 and image memory 2.

In addition, in FIG. 5, the quantization number of one pixel is set to 8 bits for simplicity. FIG. 5(a) shows the data structure of data representing one pixel in the image memory 1.
FIG. 2B shows the data structure of data representing one pixel in the image memory 2. FIG. As shown in FIG. 5(b), the image memory 2 contains n-bit image data as well as
One identification bit is added to the MS date side, resulting in a total data width of n + 1 bits.

The operation of the configuration shown in FIG. 4 will be explained below.

Image memory 1 and image memory 2 each store n-bit image data in advance.

Further, in the data of the image memory 2, the MSB of the portion to be combined with the image memory 1 is set to fl 011, and the MSB of the portion not to be combined is set to il 111 in advance. The MSB of the data in image memory 2 is selected by selector 4.
is connected to the selection control terminal 41 of “
When the selector 4 is "1", the selector 4 selects the first image data output from the image memory 1, and when it is "0", the selector 4 selects the first image data output from the image memory 2.
The data of the second image output from is selected.

In such a state, the address generator 3 is operated,
Image data output from image memory 1 and image memory 2 are read simultaneously. When the MSB of the data output from the image memory 2 is +1111, the selector 4 selects the first image data output from the image memory 1. MSB of data output from image memory 2 is 1'
0", the selector 4 selects the second image data output from the image memory 2. By performing the above operations, the first image data and the second image data output from the image memory 1 and the image memory 2, respectively, are selected. The image data of 2 is 5 ・＼−
7 can be combined and output to obtain a third image.

Problems to be Solved by the Invention However, conventional image synthesizing devices do not have the ability to combine the first image data stored in the first image memory 1 and the second image data stored in the second image memory 2. Since the number of pixels is the same as n bits, in order to add one identification bit for switching the image data output from the first image memory 1 and the second image memory 2 for each pixel, A memory of n + 1 bits was required, and there was a problem that the capacity of the image memory had to be increased. The present invention solves the above-mentioned problems, and its purpose is to reduce the capacity of an image memory.

Means for Solving the Problems In order to achieve the above object, the technical solution of the present invention does not add one bit to the image memory for the identification bit, but instead divides one pixel by n bits. Of the second image data to be expressed, 6 to 7 bits are assigned to identification bits. That is, the quantization number of the second image data is substantially 1 bit less than the quantization number of the first image data.

Effect: The present invention makes the quantization number of the second data substantially 1 bit smaller than the quantization number of the first image data, and assigns an identification bit to the 1 bit instead of the quantization number of the first image data. This reduces memory capacity.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an image synthesizing apparatus in a first embodiment of the present invention. In FIG. 1, 1 is a first image memory having a capacity for storing first image data composed of M×N pixels and in which the quantization number of one pixel is represented by n bits; 2 is a first image memory having a capacity for storing first image data; It has the same capacity as image memory 1,
And the quantization number of one pixel is represented by n-1 bits to the second 7-7 image data, and 1 bit of identification bit is added, and it has a capacity to store data represented by a total of n bits. second image memory, a is image memory 1 and image memory 2;
This is an address generator that generates address data. 4
is a selector for switching image data output from the image memory 1 and the image memory 2, respectively, and has a selection control terminal 41. Further, FIG. 2 shows the data structure of data representing one pixel in image memory 1 and image memory 2. In addition, in FIG. 2, the quantization number of one pixel is expressed as 8 bits for simplicity.

FIG. 2(a) shows the data structure of data representing one pixel in image memory 1, and FIG. 2(b) shows the data structure of data representing one pixel in image memory 2. be. As shown in FIG. 2(b), in addition to n-1 bits of image data, the data in the image memory 2 includes one identification bit added to the MSB side.

The operation shown in FIG. 1 will be explained below. The image memory 1 stores n-bit first image data in advance. Further, the image memory 2 stores n-1 bits of second image data in advance. Furthermore, in the data of image memory 2, the MSB of the part to be combined with image memory 1 is 1+ () u, and the IVI of the part not to be combined
The SB is set to (1111) in advance. The MSB of the data in the image memory 2 is connected to the selection control terminal 41 of the selector 4, and when this data is "1", the selector 4 outputs from the image memory 1. When it is "0", the second image data output from the image memory 2 is selected.

In such a state, the address generator 3 is operated,
Image data output from image memory 1 and image memory 2 are read simultaneously. When the MSB of the data output from the image memory 2 is "I If," the selector 4 selects the first image data output from the image memory 1.The MSB of the data output from the image memory 2 is "If".
At Q11, the selector 4 selects the second image data output from the image memory 2. By performing the above operations, the first image data and the second image data respectively output from the image memory 1 and the image memory 2 are combined and output, and a third image can be obtained.

As described above, in this embodiment, the number of quantizations of the image data in the image memory 2 is made substantially 1 bit smaller than the number of quantizations of the image data in the image memory 1, and the identification bit is assigned to the 1 bit instead. By doing so, the capacity of the image memory can be reduced.

FIG. 3 is a block diagram of an image synthesizing apparatus in a second embodiment of the present invention. In FIG. 3, 1 is a first image memory having a capacity for storing first image data composed of M×N pixels and in which the quantization number of one pixel is represented by n bits; 2A is a first image memory having a capacity for storing first image data; It has the same capacity address space as image memory 1 and is smaller than the first image data K×
It is composed of L pixels, and the quantization number of one pixel is n −
Second image data represented by 1 bit and 1 stroke 101
, -/ A second image memory having a capacity to store data in which one identification bit is added to each element, that is, data represented by n bits; 3 generates address data for image memory 1 and image memory 2A; This is an address generator. 4 is a selector for switching between the first image data output from the image memory 1 and the second image data output from the image memory 2, and has a selection control terminal 41. Furthermore, the data structure of data representing one pixel in these image memories 1 and 2A is the same as in the first embodiment.

Note that the hatched area surrounding the image memory 2A indicates the same address space as the image memory 1, and is an area where no memory physically exists.

The operation shown in FIG. 3 will be explained below. The image memory 1 stores n-bit first image data. Further, second image data of i-1 bits is stored in advance in the image memory 2A. Furthermore, 11 Q +1 is stored in advance in the MSB of all data in the image memory 2A. MsB of the data in the image memory 2A is connected to the selection control terminal 41 of the selector 4, and this data is set to "1".
When "O", the first image data output from the image memory 1 is selected, and when "O", the second image data output from the image memory 2A is selected. Further, the potential of the data bus connecting the image memory 2A and the selector 4 is determined by a pull-up resistor or the like, and when there is no data, all the data buses are normally set to "1".

In such a state, the address generator 3 is operated,
The image data output from the image memory 1 and the image memory 2A are read simultaneously. Address is image memory 2
When the hatched area surrounding A is indicated, there is no data, so all output data on the image memory 2A side becomes "1", and the selector 4 selects the first image data output from the image memory 1. When the address indicates the image memory 2A other than the shaded area, the MSB of the data output from the image memory 2A is all 110 I+, so the selector 4 selects the second
Select the image data. By performing the above operations, the first image data and the second image data respectively output from the image memory 1 and the image memory 2A are combined and output, and the third
images can be obtained.

As described above, in this embodiment, the number of quantizations of the image data in the image memory 2A is made substantially 1 bit less than the number of quantizations of the image data in the image memory 1, and the identification bit is assigned to the 1 bit instead. By doing so, the capacity of the image memory can be reduced. Furthermore, since it is necessary to have only the image memory for the portion to be combined, the capacity of the image memory can be further reduced.

Note that in the above explanation, the identification bit is the MSB of the image data.
However, this identification bit can be anywhere other than the MS date.

Effects of the Invention As described above, the present invention makes the number of quantization bits of the image data in the second image memory substantially 1 bit smaller than the number of quantization bits of the image data in the first image memory. By assigning identification bits to bits in a 13-way manner, the capacity of the image memory can be reduced. Furthermore, by having only the image memory for the portion to be combined, the capacity of the image memory can be further reduced.

[Brief explanation of the drawing]

FIG. 1 is a block wiring diagram of an image synthesis device according to the first embodiment of the present invention, FIG. 2 is a conceptual diagram showing the data structure of data representing one pixel of the image memory in FIG. 1, and FIG. A block wiring diagram of an image synthesizing apparatus according to a second embodiment of the invention, FIG. 4 is a block wiring diagram of a conventional image synthesizing apparatus,
FIG. 5 is a conceptual diagram showing the data structure of data representing one pixel of the image memory shown in FIG. 4. 1...First image memory, 2,2A...
・Second image memory, 3...address generator,
4...Selector, 41...Selection control terminal. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (1)

[Claims] a first image memory having a capacity to store first image data composed of M×N pixels and in which the quantization number of one pixel is represented by n bits; and a first image memory having the same capacity as the first image memory. or has an address space of the same capacity as the first image memory and less than the first image data
and a second image memory having a capacity to store second image data composed of L pixels and in which the quantization number of one pixel is represented by n bits, and the image data is output from the first image memory. When generating a third image by combining the first image data output from the second image memory and the second image data output from the second image memory, one bit of the second image data is used as an identification bit. This identification bit determines for each pixel whether the first image data output from the first image memory or the second image data output from the second image memory is selected. An image synthesizing device having an output means for determining and outputting.