JPH056325A - Input/output control device - Google Patents

Abstract

PURPOSE:To improve the using efficiency of a bus by an I/O control device capable of mixedly controlling plural adaptors having respectively different control sequences. CONSTITUTION:The I/O control device has a request arbitration part 110 for returning an accept signal 320 to an IOP bus request signal 310 with the highest priority out of plural IOP bus request signals 310 outputted from adaptors to apply the permission of use to the adaptor concerned, an address control part 140 for controlling the access address of a main storage access from the adaptor, a data buffer 130 for temporarily storing transfer data, an ADP type recognizing part 150 for judging the type of the adaptor by an ADP type signal 350 outputted from the adaptor, and a sequence control part 120 for switching a processing sequence in accordance with the recognized adaptor sort and controlling the buffer 130 and the control part 140.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device for an information processing device, and more particularly, it is connected to a plurality of adapters for controlling the input / output device by a bus, and is also connected to a central processing unit and a main memory control device. The present invention relates to an input / output control device that controls a main memory access request from a main memory to realize data transfer with a main memory.

[0002]

2. Description of the Related Art Conventionally, in this type of input / output control device, only one type of adapter can be connected via a bus.
When there is a main memory access request from the adapter, there is a method in which the input / output control device accesses the main storage control device to realize data transfer with the adapter.

[0003]

In the above-mentioned conventional method, since only the adapters controlled by the same sequence can be connected, the sequence of other adapters is also adjusted to the bus which adopts the method of the method of inefficient use of the bus. However, there is a problem that the performance cannot be improved in order to have compatibility.

The present invention has been made in order to solve the above problems, and an object thereof is to provide an input / output control device capable of controlling adapters having different control sequences in a mixed manner.

[0005]

The input / output control device of the first invention is connected to a plurality of adapters for controlling the input / output device by a bus, and is also connected to a central processing unit and a main memory control device. In an input / output control device for controlling a main memory access request from a main memory to realize data transfer with a main memory, a bus use for arbitrating a bus use right request from the adapter and giving a bus use right to the adapter Right arbitration means, address control means for controlling an access address of main memory access from the adapter to which the bus use right is given, and transfer data for temporarily holding transfer data between the adapter and the main memory device. Storage means, adapter type recognition means for discriminating the adapter type from the adapter type signal from the adapter in use of the bus, and the adapter type recognition The processing sequence of the bus is switched according to the type of adapter recognized by the stage to control the control signal of the bus and the address control means and the transfer data storage means, thereby controlling the adapters having different processing sequences in a mixed manner. And a sequence control means for enabling the operation.

The input / output control device of the second invention is connected to a plurality of adapters for controlling the input / output device by a bus, and is also connected to a central processing unit and a main storage control device, and a main storage access request from the adapter. In the input / output control device for controlling data transfer between the main memory and the main memory, the bus usage right arbitration means for arbitrating the bus usage right request from the adapter and giving the bus usage right to the adapter, Address control means for controlling the access address of the main memory access from the adapter given the bus use right;
Transfer data storage means for temporarily holding transfer data between the adapter and the main storage device, and an adapter type for determining the adapter type by a command code according to a control signal when a main storage access request is made from the adapter which is using the bus Different processing is performed by switching the processing sequence of the bus according to the recognition means and the adapter type recognized by the adapter type recognition means to control the bus control signal and control the address control means and the transfer data storage means. It has a sequence control means capable of controlling a mixture of sequence adapters.

The input / output control device of the third invention is connected to a plurality of adapters for controlling the input / output device by a bus, and is also connected to a central processing unit and a main storage control device, and a main storage access request from the adapter is sent. In the input / output control device for controlling data transfer between the main memory and the main memory, the bus usage right arbitration means for arbitrating the bus usage right request from the adapter and giving the bus usage right to the adapter, Address control means for controlling an access address of main memory access from an adapter to which a usage right is given, transfer data storage means for temporarily holding transfer data between the adapter and the main memory device, and use of the bus Adapter type that determines the adapter type based on the adapter type type information included in the address information when the main memory access request is made from the existing adapter Different processing is performed by switching the processing sequence of the bus according to the recognition means and the adapter type recognized by the adapter type recognition means to control the bus control signal and control the address control means and the transfer data storage means. It has a sequence control means capable of controlling a mixture of sequence adapters.

The input / output control device of the fourth invention is connected to a plurality of adapters for controlling the input / output device by a bus, and is also connected to a central processing unit and a main storage control device, and a main storage access request from the adapter. In the input / output control device for controlling data transfer between the main memory and the main memory, the bus usage right arbitration means for arbitrating the bus usage right request from the adapter and giving the bus usage right to the adapter, Address control means for controlling the access address of the main memory access from the adapter given the bus use right;
Transfer data storage means for temporarily holding transfer data between the adapter and the main storage device, adapter type recognition means for discriminating the adapter type according to a bus use right request signal of the adapter which is using the bus, and the adapter type By switching the processing sequence of the bus according to the type of adapter recognized by the recognizing unit to control the control signal of the bus and controlling the address control unit and the transfer data storage unit, the adapters of different processing sequences are mixed. It has a sequence control means capable of controlling.

[0009]

The adapter type recognizing means in the first invention is
Address control means for discriminating the adapter type from the adapter type signal from the adapter that is using the bus, and switching the processing sequence of the bus according to the recognized adapter type, and controlling the access address of the main memory access from the adapter. Since the transfer data storage means for temporarily holding the transfer data is controlled, the adapters having different processing sequences can be mixed and controlled.

Also in the second invention, the adapter type recognizing means discriminates the adapter type by the command code by the control signal at the time of the main memory access request from the adapter, and the sequence control means determines the processing sequence by the recognized adapter type. Since switching is performed, it is possible to control by mixing adapters having different processing sequences.

Also in the third invention, the adapter type recognition means discriminates the adapter type from the adapter type type information included in the address information at the time of the main memory access request from the adapter, and the sequence control means recognizes the adapter type. Since the processing sequence is switched by this, it becomes possible to control by mixing adapters of different processing sequences.

In the fourth invention, the adapter type recognizing means discriminates the adapter type according to the bus right request signal of the adapter, and the sequence control means switches the processing sequence depending on the recognized adapter type. It is possible to control them by mixing them.

[0013]

The present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of an information processing apparatus including an input / output control unit (IOP) according to one embodiment of the present invention.

From FIG. 5, the IOP 100 is connected to an instruction execution control unit (CPU) 400 and a main memory control unit (MEM) 500 by a system bus 200. Also, IOP1
00 is connected to the I / O adapter (type A) 600 and the I / O adapter (type B) 700 by the IOP bus 300. When the CPU 400 activates an input / output instruction to the IOP 100, the IOP 100 loads the channel program into the ME.
Read from M500 to perform I / O operation I / O adapter (type A) 600 or I / O adapter (type B)
Instruct 700. The I / O adapter instructed to perform the I / O operation is connected to the I / O device connected under it and the MEM 50.
In order to transfer data to and from 0, a data transfer request is made to the IOP 100 via the IOP bus 300 in units of 4 bytes or 16 bytes. IOP100 is IOP
When there is an access request from the bus 300 to the MEM 500, the system bus 200 is requested to access the MEM 500, and data transfer between the request source I / O adapter and the MEM 500 is realized.

FIG. 1 is a block diagram of an input / output control device according to an embodiment of the first invention.

FIG. 6 shows an ADP type A ME according to the first invention.
It is a data transfer timing chart of M write.

FIG. 7 shows an ADP type B ME of the first invention.
It is a data transfer timing chart of M write.

From FIG. 1, a request arbitration unit 110 (bus use right arbitration unit), a sequence control unit 120 (sequence control unit), a data buffer 130 (transfer data storage unit), an address control unit 140 (address control unit),
The ADP type recognition section 150 (adapter type recognition means) is used.

An IOP bus request signal 310, which is a request from the I / O adapter to acquire the right to use the IOP bus 300.
When the (bus usage right arbitration unit) is given to the request arbitration unit 110, a plurality of request signals are arbitrated by the request arbitration unit 110, and I / I having a high priority is assigned.
I which is a use permission signal of the bus 300 to the O adapter
The OP bus accept signal 320 (bus arbitration means) is returned. I was given permission to use the bus 300
The / O adapter activates the bus operation. In the start-up sequence, the type of bus operation is indicated as a command by the IOP bus control signal 330 (sequence control means) from the I / O adapter. This command is IOP10
It is input to the sequence control unit 120 in 0 and analyzed.
When the command is an access request to the MEM 500, the sequence control unit 120 starts a response to the request from the I / O adapter. When the command is recognized in the activation sequence, the address control signal 170 (sequence control means) from the sequence control unit 120 causes the I
The address information of the IOP bus address / data signal 340 (address control means) on the OP bus 300 is taken into the address control unit 140 as a MEM access address. At the same time, I / O adapter to IOP bus / A
The DP type signal 350 (adapter type recognition means) is output. This IOP bus / ADP type signal 350 is I
It is input to the ADP type recognition unit 150 in OP100,
The adapter type of the request source is recognized. Recognized ADP
When the type 180 (adapter type recognition means) is input to the sequence control unit 120, the sequence control unit 120 switches the control sequence according to the ADP type. Next, the IOP bus enters the data transfer phase, and in the case of MEM write, by the data buffer control signal 160 (sequence control means) from the sequence control unit 120,
IOP bus address / data signal 34 on the IOP bus
The data information of 0 is taken into the data buffer 130. Further, when a request for MEM access is generated from the IOP bus, the sequence control unit 120 causes the system bus 200
To access the MEM 500 via. The sequence control unit 120 acquires the right to use the system bus 200, and the system bus control signal 210 (sequence control means) causes the MEM 5 via the system bus 200.
Start the transfer sequence with 00. At this time, the data stored in the data buffer 130 is transferred to the address stored in the address control unit 140 by the system bus address signal 220 (address control means), and the data stored in the data buffer 130 is transferred to the MEM 500 by the system bus data signal 230 (transfer data storage means). Write in. The data flow is reversed during MEM read. Data transfer between the I / O adapter and the MEM 500 is performed by these series of operations.
In the case of the MEM write requested by the / O adapter (type A) 600, the ADP type recognition display "0" is used for switching, and data transfer is performed at the timing shown in FIG.
Further, in the case of a MEM write requested by the I / O adapter (type B) 700, the ADP type recognition display becomes "1", and data transfer is performed at the timing shown in FIG.
At this time, the time for occupying the IOP bus 300 for each MEM access is 16 clock cycles for the I / O adapter (type A) 600 and 11 clock cycles for the I / O adapter (type B) 700. .

FIG. 2 is a block diagram of an input / output control device according to an embodiment of the second invention.

FIG. 8 shows an ADP type A ME of the second invention.
It is a data transfer timing chart of M write.

FIG. 9 shows an ADP type B ME of the second invention.
It is a data transfer timing chart of M write.

From FIG. 2, it comprises a request arbitration unit 110, a sequence control unit 120, a data buffer 130, an address control unit 140, and an ADP type recognition unit 150.

IOP bus request signal 310 which is a request for acquisition of the right to use the IOP bus 300 from the I / O adapter.
Are sent to the request arbitration unit 110, a plurality of request signals are arbitrated by the request arbitration unit 110, and the IOP bus accept signal 320, which is a use permission signal of the bus 300, is returned to the I / O adapter having a high priority. Be done. I / was given permission to use the bus
The O adapter activates the bus operation. In the start-up sequence, the IOP bus control signal 330 from the I / O adapter indicates the type of bus operation as a command. This command is input to the sequence control unit 120 in the IOP 100 and analyzed. The command is MEM500
If the request is for access to the sequence control unit 12,
0 initiates a response to the request from the I / O adapter. When the command is recognized in the startup sequence, the address control signal 170 from the sequence control unit causes the I
The address information of the IOP bus address / data signal 340 on the OP bus 300 is taken into the address control unit 140 as a MEM access address. At this time, the ADP type information is included in a part of the command information, and the IOP bus control signal 330 is IOP1.
It is input to the ADP type recognition unit 150 in 00, and the adapter type of the request source is recognized. When the recognized ADP type 180 is input to the sequence control unit 120, the sequence control unit 120 switches the control sequence according to the ADP type. Next, the IOP bus enters the data transfer phase, and in the case of MEM write, the data information of the IOP bus address / data signal 340 on the IOP bus is taken into the data buffer 130 by the data buffer control signal 160 from the sequence controller. Be done. Also,
When a request for MEM access is generated from the IOP bus 300, the sequence control unit 120 accesses the MEM 500 via the system bus 200. The sequence control unit 120 acquires the right to use the system bus 200, and activates a transfer sequence with the MEM 500 via the system bus 200 by the system bus control signal 210. At this time, according to the address stored in the address controller 140, the system bus address signal 22
When 0, the data stored in the data buffer 130 is written to the MEM 500 by the system bus data signal 230. The data flow is reversed during MEM read. With these series of operations, I / O adapter and MEM50
Data is transferred to and from 0, but in the case of a MEM write requested by the I / O adapter (type A) 600, when ADP type recognition is "0", data is transferred at the timing shown in FIG. Also, I / O adapter (Type B)
In the case of MEM write requested by 700, when ADP type recognition is “1”, data transfer is performed at the timing shown in FIG. At this time, each MEM access causes IOP
The time for occupying the bus 300 is 16 clock cycles for the I / O adapter (type A) 600 and 11 clock cycles for the I / O adapter (type B) 700.

FIG. 3 is a block diagram of an embodiment of the third invention.

FIG. 10 shows M of ADP type A of the third invention.
It is a data transfer timing chart of EM write.

FIG. 11 shows M of ADP type B of the third invention.
It is a data transfer timing chart of EM write.

From FIG. 3, it comprises a request arbitration unit 110, a sequence control unit 120, a data buffer 130, an address control unit 140, and an ADP type recognition unit 150.

IOP bus request signal 310, which is a request for acquisition of the right to use the IOP bus 300 from the I / O adapter.
Are sent to the request arbitration unit 110, a plurality of request signals are arbitrated by the request arbitration unit 110, and the IOP bus accept signal 320, which is a use permission signal of the bus 300, is returned to the I / O adapter having a high priority. Be done. The I / O adapter that has been given permission to use the bus 300 activates the bus operation. In the start-up sequence, the IOP bus control signal 330 from the I / O adapter indicates the type of bus operation as a command. This command is input to the sequence control unit 120 in the IOP 100 and analyzed. Command is MEM5
If it is a request to access 00, the sequence control unit 120 starts responding to the request from the I / O adapter. When the command is recognized in the start-up sequence, the address control signal 170 from the sequence control unit 120 fetches the address information of the IOP bus address / data signal 340 on the IOP bus into the address control unit 140 as a MEM access address. At this time, the ADP type information is included in part of the address information, and the IOP bus address / data signal 340 (address control means, adapter type recognition means) is the IOP 100.
It is input to the ADP type recognition unit 150 inside and the adapter type of the request source is recognized. Recognized ADP type 18
When 0 is input to the sequence control unit 120, the sequence control unit 120 switches the control sequence according to the ADP type. Next, the IOP bus enters the data transfer phase, and in the case of MEM write, the sequence controller 120
Data buffer control signal 160 from the IOP
The data information of the IOP bus address / data signal 340 on the bus is taken into the data buffer 130. When a request for MEM access is issued from the IOP bus, the sequence control unit 120 accesses the MEM 500 via the system bus 200. The sequence control unit 120 acquires the right to use the system bus 200, and activates a transfer sequence with the MEM 500 via the system bus 200 by the system bus control signal 210. At this time, according to the address stored in the address controller 140, the system bus address signal 22
0 causes the data stored in the data buffer 130 to be written to the MEM by the system bus data signal 230. The data flow is reversed during MEM read. Data transfer between the I / O adapter and the MEM500 is performed by these series of operations, but the I / O adapter (type A) is used.
In the case of the MEM write requested by 600, the ADP type recognition is switched to "0", and the data transfer is performed at the timing shown in FIG. Also, I / O adapter (Type B)
In the case of the MEM write requested by 700, the ADP type becomes "1", and the data transfer is performed at the timing shown in FIG. At this time, each MEM access causes IOP
Bus occupancy time is I / O adapter (type A) 6
00 is 16 clock cycles, and I / O adapter (type B) 700 is 11 clock cycles.

FIG. 4 is a block diagram of an input / output control device according to an embodiment of the fourth invention.

FIG. 12 shows M of ADP type A of the fourth invention.
It is a data transfer timing chart of EM write.

FIG. 13 shows an ADP type B M of the fourth invention.
It is a data transfer timing chart of EM write.

From FIG. 4, it comprises a request arbitration unit 110, a sequence control unit 120, a data buffer 130, an address control unit 140, and an ADP type recognition unit 150.

IOP bus request signal 310, which is a request for acquisition of the right to use the IOP bus 300 from the I / O adapter.
Are sent to the request arbitration unit 110, a plurality of request signals are arbitrated by the request arbitration unit 110, and the IOP bus accept signal 320, which is a use permission signal of the bus 300, is returned to the I / O adapter having a high priority. Be done. The I / O adapter that has been given permission to use the bus 300 activates the bus operation. In the start-up sequence, the IOP bus control signal 330 from the I / O adapter indicates the type of bus operation as a command. This command is input to the sequence control unit 120 in the IOP 100 and analyzed. When the command is an access request to the MEM, the sequence control unit 120
Starts a response to the request from the I / O adapter.
When the command is recognized in the startup sequence, the IOP is sent by the address control signal 170 from the sequence control unit.
The address information of the IOP bus address / data signal 340 on the bus is taken into the address control unit 140 as a MEM access address. At this time, since the requesting I / O adapter can be specified by the IOP bus accept signal 320, the IOP bus accept signal 3
20 (bus right-of-use arbitration means, adapter type recognition means) is input to the ADP type recognition section 150 in the IOP 100, and the adapter type of the request source is recognized. Recognized A
When the DP type 180 is input to the sequence control unit 120, the sequence control unit 120 switches the control sequence according to the ADP type. Next, the IOP bus enters the data transfer phase, and in the case of MEM write, the data buffer control signal 160 from the sequence controller 120 causes the IOP bus address / IOP bus address /
The data information of the data signal 340 is the data buffer 130.
Is taken into. When a request for MEM access is generated from the IOP bus 300, the sequence control unit 120 accesses the MEM 500 via the system bus 200. The sequence control unit 120 acquires the right to use the system bus 200, and the system bus control signal 21
0 through the system bus 200 to the MEM 500
Start the transfer sequence between and. At this time, according to the address stored in the address control unit 140, the system bus address signal 220 causes the data buffer 13
The data stored in 0 is transferred to the system bus data signal 23
Write to MEM with 0. The data flow is reversed during MEM read. Data transfer between the I / O adapter and the MEM 500 is performed by these series of operations.
In the case of the MEM write requested by the adapter (type A) 600, the ADP type determination is “0”, and the data transfer is performed at the timing shown in FIG. Further, in the case of the MEM write requested by the I / O adapter (type B) 700, the ADP type judgment is “1”, and the data transfer is performed at the timing shown in FIG. At this time, each ME
It takes 16 clock cycles for the I / O adapter (type A) 600 to occupy the IOP bus for M access.
The O adapter (type B) 700 has 11 clock cycles.

[0036]

As described above, according to the present invention, since I / O adapters having different control sequences can be controlled in a mixed manner, the bus use efficiency can be improved without impairing the compatibility.

[Brief description of drawings]

FIG. 1 is a block diagram of an input / output control device according to an embodiment of the first invention.

FIG. 2 is a block diagram of an input / output control device of a second invention.

FIG. 3 is a block diagram of an input / output control device of a third invention.

FIG. 4 is a block diagram of an input / output control device of a fourth invention.

FIG. 5 is a block diagram of an information processing device including an input / output processing device to which the present invention is applied.

FIG. 6 is a data transfer timing chart of the ADP type A MEM write of the first invention.

FIG. 7 is a data transfer timing chart of the ADP type B MEM write of the first invention.

FIG. 8 is a data transfer timing chart of the ADP type A MEM write of the second invention.

FIG. 9 is a data transfer timing chart of the ADP type B MEM write of the second invention.

FIG. 10 is a data transfer timing chart of the ADP type A MEM write of the third invention.

FIG. 11 is a data transfer timing chart of the ADP type B MEM write of the third invention.

FIG. 12 is a data transfer timing chart of the ADP type A MEM write of the fourth invention.

FIG. 13 is a data transfer timing chart of the ADP type B MEM write of the fourth invention.

[Explanation of symbols]

100 IOP 110 Request Arbitration Unit 120 Sequence control unit 130 data buffer 140 address control unit 150 ADP type recognition unit 160 data buffer control signal 170 Address control signal 180 ADP type 200 system bus 210 system bus control signal 220 system bus address signal 230 system bus data signal 300 IOP bus 310 IOP bus request signal 320 IOP bus accept signal 330 IOP bus control signal 340 IOP bus address / data signal 350 IOP bus / ADP type signal 400 CPU 500 MEM 600 I / O adapter (Type A) 700 I / O adapter (Type B)

Claims (4)

[Claims] 1. A plurality of adapters for controlling an input / output device are connected by a bus, and are also connected to a central processing unit and a main memory control unit, and control main memory access requests from the adapters to communicate with the main memory. In the input / output control device for realizing the above data transfer, a bus use right arbitration unit that arbitrates a bus use right request from the adapter and gives a bus use right to the adapter, and an adapter to which the bus use right is given. Address control means for controlling the access address of the main memory access, transfer data storage means for temporarily holding transfer data between the adapter and the main memory device, and an adapter type signal from the adapter using the bus. The adapter type recognition means for determining the adapter type by the adapter type recognition means, and the adapter type recognized by the adapter type recognition means By controlling the control signal of the bus by switching the processing sequence of the bus and controlling the address control means and the transfer data storage means, it is possible to control the mixture of adapters of different processing sequences. An input / output control device comprising: 2. A plurality of adapters for controlling the input / output device are connected by a bus, and are also connected to a central processing unit and a main memory control device, and control main memory access requests from the adapters to communicate with the main memory. In the input / output control device for realizing the above data transfer, a bus use right arbitration unit that arbitrates a bus use right request from the adapter and gives a bus use right to the adapter, and an adapter to which the bus use right is given. Address control means for controlling the access address of the main memory access, transfer data storage means for temporarily holding transfer data between the adapter and the main memory device, and main memory access from the adapter using the bus An adapter type recognizing unit that determines the adapter type by a command code based on a control signal at the time of request, and an adapter type recognizing unit. Controlling a mixture of adapters of different processing sequences by switching the processing sequence of the bus according to the recognized adapter type to control the control signal of the bus and controlling the address control means and the transfer data storage means. An input / output control device comprising: 3. A plurality of adapters for controlling an input / output device are connected by a bus, and are also connected to a central processing unit and a main memory control unit, and control main memory access requests from the adapters to communicate with the main memory. In the input / output control device for realizing the above data transfer, a bus use right arbitration unit that arbitrates a bus use right request from the adapter and gives a bus use right to the adapter, and an adapter to which the bus use right is given. Address control means for controlling the access address of the main memory access, transfer data storage means for temporarily holding transfer data between the adapter and the main memory device, and main memory access from the adapter using the bus An adapter type recognizing unit that determines the adapter type based on the adapter type type information included in the address information at the time of request, and the adapter type By switching the processing sequence of the bus according to the adapter type recognized by the different recognition means to control the control signal of the bus and the address control means and the transfer data storage means,
An input / output control device comprising: a sequence control means capable of controlling adapters having different processing sequences in a mixed manner. 4. A bus is connected to a plurality of adapters for controlling the input / output device, and is also connected to a central processing unit and a main memory control device, and controls main memory access requests from the adapters to communicate with the main memory. In the input / output control device for realizing the above data transfer, a bus use right arbitration unit that arbitrates a bus use right request from the adapter and gives a bus use right to the adapter, and an adapter to which the bus use right is given. Address control means for controlling the access address of the main memory access, transfer data storage means for temporarily holding transfer data between the adapter and the main memory device, and bus usage right request of the adapter which is using the bus An adapter type recognizing means for discriminating the adapter type by the signal, and the adapter type recognizing means for recognizing the adapter type by the adapter type recognizing means. Sequence control means for controlling the bus control signal by controlling the bus control signal and the address control means and the transfer data storage means, thereby making it possible to mix and control adapters having different processing sequences. An input / output control device comprising: