JPH0563012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a hetero-bipolar transistor using a heterojunction.

[Conventional technology]

Hetero bipolar transistors (hereinafter referred to as HBTs) use a semiconductor with a larger forbidden band width than the base for the emitter, which allows the base current to be reduced and the current gain to be increased. It is attracting attention as a high-speed operation transistor.

As an emitter, n-type aluminum, gallium,
Arsenic mixed crystal (hereinafter referred to as n-type AlGaAs), p-type gallium arsenide (hereinafter referred to as p-type GaAs) as the base, and n-type GaAs as the collector.
npnHBT is being prototyped.

[Problem to be solved by the invention] Although this type of HBT is thought to operate faster than a normal bihole transistor using silicon, in reality, such ultra-high-speed operation has not been achieved. .

One of the reasons for this is that the parasitic capacitance between the emitter and base and the base and collector is larger than that of a silicon bipolar transistor.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a heterobipolar transistor with extremely small emitter-base and base-collector parasitic capacitances.

[Structure of the invention]

The method for manufacturing a hetero bipolar transistor of the present invention includes a step of sequentially forming a thin film and a photoresist film for forming a reduced structure on the surface of a semiconductor substrate in which a low resistance layer and a high resistance layer of one conductivity type are sequentially laminated. A step of patterning the resist film to form a mask and etching the thin film using the mask to leave a thin film having dimensions smaller than the dimensions of the mask. After forming the film, a step of removing the first insulating film on the mask together with the mask, a step of depositing a second insulating material on the entire surface in a vertical direction to form a second insulating film, and a step of forming a second insulating film on the remaining thin film. a step of removing the second insulating film together with the thin film and leaving an insulating film consisting of the first and second insulating films having a recess of the mask size and an opening smaller than the mask size on the surface of the semiconductor substrate, from a vertical direction; a step of diffusing or ion-implanting impurities of one conductivity type to lower the resistance of the high-resistance layer portion of the semiconductor substrate in the exposed opening;
A layer made of a first semiconductor of one conductivity type and a layer made of a first semiconductor of an opposite conductivity type are in contact with the surface of the semiconductor substrate in the opening and have a forbidden band width larger than that of the semiconductor substrate. A layer made of a second semiconductor of one conductivity type is sequentially formed, and at the same time, a layer made of a high-resistance polycrystalline first semiconductor and a high-resistance polycrystalline second semiconductor are formed on the first and second insulating films. a step of depositing a metal thin film on the entire surface and then forming a photoresist film only in the concave portions so that the entire surface is flat; a step of removing the second and first high-resistance polycrystalline semiconductor layers covered with the metal film; a step of selectively removing only the remaining high-resistance polycrystalline first semiconductor layer; , selectively growing a layer made of a first semiconductor of an opposite conductivity type in contact with at least a side surface of the layer made of a first semiconductor of an opposite conductivity type.

[Function/principle of the invention]

The HBT manufactured according to the present invention consists of a first semiconductor layer of the opposite conductivity type and low resistance for taking out the base electrode, and a polycrystalline second semiconductor layer with high resistance between the emitter electrode and the collector electrode. Because of the intervening layers and insulating layers, emitter-base and base-collector parasitic capacitances are reduced to almost negligible levels.

Therefore, there is no characteristic deterioration due to parasitic capacitance, and ultra-high-speed operating characteristics far superior to Si bipolar transistors can be obtained.

Particularly in manufacturing the HBT having the above-described structure, the present invention realizes an emitter width smaller than the mask dimension and forms the emitter and base in a self-aligned manner.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1J are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1a, an n-type gallium arsenide (GaAs) layer 11 and a high-resistance n-type
An aluminum film 1 with a thickness of 0.5 μm is used as a thin film for forming a reduced structure on a GaAs substrate consisting of a GaAs layer 12.
A mask 14 made of a photoresist film having a width of 1 μm is formed thereon by photolithography.

Next, as shown in FIG. 1B, the aluminum film 15 is etched with a 60 DEG C. phosphoric acid solution using the mask 14, leaving an aluminum film 15A with a width of 0.4 .mu.m under the mask 14. Subsequently, silicon oxide is vertically deposited on the entire surface as a first insulating film by vapor deposition or sputtering to form an arsenic oxide film 17 having a thickness of 0.2 μm.

Next, as shown in FIG. 17C, the silicon oxide film 17A on the mask 14 is removed together with the mask 14. As a result, on the surface of the high-resistance GaAs layer 12, silicon oxide films 17 with a thickness of 0.2 μm are arranged with an interval of 0.3 μm between the aluminum films 15A with a width of 0.4 μm.

Next, as shown in Figure 1d, the second
Silicon oxide is deposited as an insulating film to form a silicon oxide film 18 having a thickness of 0.2 μm. Suitable materials for the second insulating film include silicon nitride outside silicon oxide and aluminum oxide.

Next, as shown in FIG. 1e, the aluminum film 1
The silicon oxide film 18A on the silicon oxide film 18A is removed at the same time as the aluminum film 15A with a 60° C. phosphoric acid solution. In this way, the surface portion 22 of the high resistance n-type GaAs layer 12 on which the aluminum film 15 was formed is exposed. Subsequently, silicon ions are implanted to convert the exposed high resistance GaAs layer 12 into an n-type low resistance layer.

Next, as shown in FIG. 2f, using the molecular beam epitaxial method, an n-type GaAs layer 23 is deposited to a thickness of 0.2 μm on the exposed surface 22 of the n-type GaAs layer, and then a p-type GaAs A layer 24 with a thickness of 0.1 μm is successively deposited thereon, and an n-type AlGaAs layer with a thickness of 0.5 μm is deposited thereon. At the same time, high-resistance polycrystalline GaAs layer 26 and AlGaAs layer 27 are formed on silicon oxide films 17 and 18 with thicknesses of 0.3 μm and 0.5 μm, respectively.

Next, as shown in FIG. 1g, a metal film 28 containing gold and germanium alloy is formed on the polycrystalline AlGaAs layer 27.
Further, a photoresist film 29 is formed only in the recesses so that the entire surface is flat. Formation of such a photoresist film 29 can be easily carried out by a normal planarization technique that combines a coating method utilizing softening of the photoresist film and a dry etching method.

Next, as shown in FIG. 1h, using the photoresist film 29 as a mask, the exposed metal film 28 and the high-resistance polycrystalline AlGaAs layer 27 and GaAs layer 26 located below it are removed, respectively. For this removal step, a conventional chemical etching method or dry etching method can be used.

Next, as shown in FIG. The side surfaces of the type GaAs layer 24 are exposed.

Next, as shown in FIG. 1j, after removing the photoresist film 29, p-type GaAs is grown by vapor phase growth using arsenic trichloride. Growth proceeds from the side surfaces of the p-type GaAs layer 24, so-called lateral growth, and the p-type GaAs layer 3 is grown at least in contact with the p-type GaAs layer 24.
0 is formed. Next, this p-type GaAs region 30
By forming an electrode 31 containing a gold/zinc alloy on the surface and an electrode 32 containing a gold/germanium alloy on the surface of the n-type GaAs layer 17 that is the substrate.
HBT is completed.

In FIG. 1f, the metal layer 28 and the electrode 31,
32 function as emitter, base, and collector electrodes, respectively.

In the HBT manufactured in this way,
Since the layers in contact with the lower part of the p-type GaAs layer 30 for taking out the base electrode are the silicon oxide layers 17 and 18,
The parasitic capacitance between the base and collector is extremely small, and the layer in contact with the top is a high-resistance polycrystalline AlGaAs layer 2.
7, the parasitic capacitance between the base and emitter is also extremely small.

Furthermore, in the HBT manufactured according to this example, an emitter having a width smaller than the mask dimension can be formed in a self-aligned manner, so that the manufactured npn HBT exhibits remarkable ultra-high speed characteristics. While the cutoff frequency of the conventional npnHBT was about 20 GHz, that of the npnHBT made according to the embodiment of the present invention is
improved to 150 GHz.

In the above embodiment, an npn type HBT was explained, but a pnp type HBT can also be formed using a similar manufacturing method. In addition, the combinations of semiconductor materials used include GaAs-AlGaAs, SiGe-Si,
InGaAs−AlInAs, InAs−AlInAs, InAs−
InGaAs, GaAs-GaInP, InGaAs-InP, GaSb
It goes without saying that it is also effective for various combinations such as -AlGaSb, Si-GaP, Ge-GaAs, etc.

〔Effect of the invention〕

As explained above, the present invention provides a polycrystalline second semiconductor with high resistance between the layer made of the first semiconductor of the opposite conductivity type and low resistance for taking out the base electrode, and the emitter electrode and the collector electrode. and an insulating layer, the emitter-base and base-collector parasitic capacitances are extremely small, resulting in a hetero-bipolar transistor with ultra-high-speed operation characteristics.

[Brief explanation of the drawing]

FIGS. 1A to 1J are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. 11...n-type GaAs layer, 12...high-resistance n-type
GaAs layer, 14...Mask, 15, 15A...Aluminum film, 17, 17A, 18, 18A...
Silicon oxide film, 22... surface, 23... n-type GaAs
layer, 24... p-type GaAs layer, 25... n-type
AlGaAs layer, 26... Polycrystalline GaAs layer, 27...
Polycrystalline AlGaAs layer, 28...metal layer, 29...photoresist film, 30...p-type GaAs layer, 31,
32...electrode.

Claims (1)

[Claims] 1 Step of sequentially forming a thin film for forming a reduced structure and a photoresist film on the surface of a semiconductor substrate in which a low-resistance layer and a high-resistance layer of one conductivity type are sequentially laminated, a step of patterning the photoresist film to form a mask, A step of etching the thin film using a mask to leave a thin film having dimensions smaller than the dimensions of the mask, a step of depositing a first insulating film on the entire surface from the vertical direction, forming the first insulating film, and then etching the first insulating film on the mask. a step of removing the first insulating film together with a mask, a step of depositing a second insulating material vertically on the entire surface to form a second insulating film, and a step of removing the second insulating film on the remaining thin film together with the thin film. a step of removing and leaving an insulating film consisting of a first and second insulating film having a recess of the mask size and an opening smaller than the mask size on the surface of the semiconductor substrate, diffusing or ionizing impurities of one conductivity type from the vertical direction; a step of implanting and lowering the resistance of a high resistance layer portion of the semiconductor substrate in the exposed opening; A layer made of a semiconductor of one conductivity type and a layer made of a second semiconductor of one conductivity type having a forbidden band width larger than the forbidden band width of the semiconductor substrate are sequentially formed, and at the same time a high resistance layer is formed on the first and second insulating films. A step of sequentially forming a layer made of a polycrystalline first semiconductor and a layer made of a high-resistance polycrystalline second semiconductor. After a metal thin film is deposited on the entire surface, a photo is applied only to the recessed portions so that the entire surface is flat. a step of forming a resist film, a step of removing the metal film exposed using the photoresist film as a mask, and a layer consisting of a high-resistance polycrystalline second and first semiconductor covered by the metal film; selectively removing only a layer made of a high-resistance polycrystalline first semiconductor; a layer made of a first semiconductor of an opposite conductivity type in contact with at least a side surface of the layer made of a first semiconductor of an opposite conductivity type; A method for manufacturing a hetero bipolar transistor, comprising the step of selectively growing a hetero bipolar transistor.