JPH0562509B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a circuit for clamping signals transmitted with alternating level differences (steps).

BACKGROUND ART AND PROBLEMS Generally, a clamp circuit is configured to clamp a constant level portion of a signal of a predetermined period to be clamped to a desired potential. For example, a portion that is considered to be at a constant level, such as a high level portion or a low level portion of a square wave, or a pedestal portion or a sync tip portion of a video signal, is clamped.

However, there are signals in which portions to be clamped are transmitted at alternating periods with level differences, albeit at a constant period. For example, in the recording system of an electronic still camera, the R-Y and B-Y signals obtained from the image sensor are reduced to FM in a line-sequential manner, frequency-multiplexed with a high-frequency FM luminance signal, and recorded on a cassette magnetic disk. It's getting old. In the reproducing machine, a frequency difference is generated in the FM carrier in order to distinguish line-sequential RY and BY signals from each other. For this reason, in the front stage of the recording system's FM modulator, R-Y, B-Y, and line (horizontal scanning)
A circuit is inserted that alternately adds DC level differences. This DC level difference becomes a difference in carrier frequency of the FM signal.

If a video signal having such line-sequential step levels is clamped with clamp pulses having horizontal periods corresponding to the pedestal sections, the step information will be lost.

Conventionally, therefore, a method has been adopted in which one of the two levels is discriminated and clamping is applied only to this one level. This method requires a level discriminator such as a window comparator,
Therefore, the circuit is not only complicated, but also has the risk of malfunction.

OBJECTS OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to clamp signals with alternating level differences by a simpler means.

Summary of the Invention The clamp circuit of the present invention is a circuit for clamping a stepped input signal in which the signal portions to be clamped at a predetermined period are alternately at the first and second levels, and the clamp circuit is a circuit for clamping a stepped input signal in which the signal portions to be clamped at a predetermined period are alternately at the first and second levels. 1. A circuit 20 that clamps the second level parts so that they have the same potential, a circuit that extracts the DC component of the clamp output (low-pass filter 22), and a circuit that extracts the AC component of the input signal (high-pass filter 22). It includes a filter 21) and a circuit (adder 23) that adds the extracted DC and AC components. With this configuration, the clamp circuit for the stepped signal can be made simpler.

Example The present invention will be explained below based on examples.

FIG. 1 is a block diagram of a recording system of an electronic still camera to which the clamp circuit of the present invention can be applied, and FIG. 2 is a waveform diagram of a stepped line sequential color difference signal to be recorded.

In FIG. 1, a video signal obtained from a CCD 1 is sent to a synchronization addition circuit 3 as a luminance signal and R, G, B signals through process amplifiers 2a to 2d.
and is led out to the matrix circuit 4. Note that the synchronization signal is generated by the synchronization generator 16, and the horizontal and vertical synchronization signals are also supplied to the imaging section to drive the CCD 1.

The luminance signal Y is converted to FM in the high range by the FM modulator 5.
After being modulated, the signal is supplied to a magnetic head 9 via a high-pass filter 6, a mixer 7, and a recording amplifier 8, and is recorded on a magnetic disk 10.

On the other hand, the color difference signals R-Y and B-Y of the matrix circuit 4 are converted into line sequential signals by the changeover switch 11, and after being added with a step G as shown in FIG. 2A by the level difference addition circuit 12, they are clamped. The signal is supplied to an FM modulator 14 via a circuit 13. The FM-modulated line-sequential signal is introduced into the mixer 7 through the low-pass filter 15, mixed with the FM luminance signal, and recorded on the disk 10.

The center frequencies of the recorded FM color difference signals are 1.2 MHz for RY and 1.3 MHz for B-Y due to the step difference. On the other hand, the luminance signal is FM modulated with a deviation of 6 to 7.5 MHz, and is recorded separately from the color difference signal in band. Color difference signal system clamp circuit 13
is inserted to fix the level of the modulation input to the FM modulator 14, but this modulation input has a level difference alternately with 1H (H: horizontal synchronization) as shown in Figure 2A. , conventionally, 2H as shown in Figure 2B located at the pedestal is used as a clamp pulse.
Each clamp pulse was used and required a level discriminator to clamp only one of the two levels.

In addition, in a playback machine for recorded discs, for example, in order to convert line-sequential color difference signals to simultaneous color difference signals,
A delay line such as a CCD is used, and its input is equipped with a clamp circuit that fixes the level of the signal to be delayed. In this case, a level discrimination function is also required to clamp the stepped line sequential signal. .

Furthermore, in the conventional art, since steep amplitude axis operations are performed at the leading and trailing edges of the clamp pulse shown in FIG. 2B, clamp noise N may be superimposed on the clamp output.

FIG. 3 is a block diagram of the clamp circuit of the present invention, and FIG. 4 is a signal waveform diagram of each part in FIG.

The input stepped line sequential color difference signal (FIG. 4A) is branched to a clamp circuit 20 and a high pass filter 21. In the clamp circuit 20, normal clamping is performed based on a horizontal frequency clamp pulse (FIG. 4B) corresponding to the pedestal portion of the input color difference signal, and the desired clamp voltage Vc shown in FIG. 4C is obtained.
A signal clamped to is derived. Note that the level difference information disappears due to this clamping.

Clamp output is several V or more (V is vertical scanning period)
Low pass filter 2 with a very long time constant of
2, and a signal (Average Picture Level) which is the DC portion of the video information is extracted. this
The APL signal (FIG. 4D) has level information L that is exactly the same as the ALP information based on the intermediate level (average level) E of the step in the input signal of FIG. 4A. Also, this ALP signal is the clamp voltage Vc
is clamped to.

The output of the low-pass filter 22 (Fig. 4D) is
The adder 23 adds the input signal that has passed through the high-pass filter 21. The high-pass filter 21 is a DC cut-off filter with a cut-off frequency of several tens of Hz, and the high-pass filter 21 is a DC cut-off filter that has a cut-off frequency of several tens of Hz.
It removes information. Therefore, the output of the high-pass filter 21 and the output of the low-pass filter 22 are
By adding the ALP output, the original signal is reproduced. In this case, since the ALP signal is clamped to the clamp voltage Vc, the output of the adder 23 provides a step line sequential color difference signal clamped to the voltage Vc shown in FIG. 4E.

In this way, in the clamp circuit shown in Figure 3,
The input is divided into a DC component and an AC component, and with the DC component clamped to a desired potential, both are added to obtain a clamped output. The DC component clamp is based on the clamp operation that ignores the step information and the clamp output.
This is achieved by DC fraction extraction.

FIG. 5 is a concrete circuit of the clamp circuit shown in FIG. 3, and the input signal is the transistor T1 and the resistor R1.
is injected into the clamp capacitor C1 through an emitter follower stage consisting of . Clamp capacitor C1
At its output, a clamp voltage is applied in response to a clamp pulse corresponding to the pedestal section of the color difference input signal.
A transistor T2 conductive to the level of Vc is connected. When this transistor T2 becomes conductive, the pedestal level of the signal passing through the clamp capacitor C1 matches the voltage Vc.
is charged, thereby clamping the signal passing through capacitor C1 to voltage Vc.

The output of the capacitor C1 is connected to the connection point A forming the adder 24 via a source follower consisting of a field effect transistor T3 and a resistor R3, and a resistor R3.
is derived. On the other hand, the emitter output of the input transistor T1 is led out to the above-mentioned node A via the capacitor C2, and added at this node A.

Since the connection point A is grounded through the resistors R3 and R2 (R2≪R3), the capacitor C2 and the resistor R3 form the high pass filter 21 shown in FIG. 6A.
is configured, and the emitter output signal of the transistor T1 is derived from the adder 23 through this high-pass filter 21. On the other hand, transistor T3
Viewed from the output of 22 are configured. Therefore transistor T3
The source output signal passes through this low-pass filter 22 and is applied to an adder 23 (connection point A).

The transfer function of the high-pass filter 21 in FIG. 6A is TS/1+TS (T is the CR time constant), and the transfer function of the low-pass filter 22 in FIG. 6B is 1/1+TS, and the sum of these is: TS/1+TS+1/1+TS=1. In other words, the input/output transfer function in Figure 5 is 1
The frequency characteristics are flat. Therefore, even if the screen content suddenly changes, the sudden change in ALP is transmitted to the output through the AC system (high-pass filter 21), so the clamped DC level will not fluctuate to follow the screen content. Never.

Furthermore, according to the clamp circuit of the embodiment, the
Since only the DC component is clamped and the AC component is not clamped, whisker-like clamp noise is not superimposed on the output signal at the steep leading and trailing edges of the clamp pulse.

Effects of the Invention As described above, the present invention clamps the first and second levels of the input signal to be clamped to the same potential, extracts the DC component thereof, separately extracts the AC component of the input signal, and then extracts the DC component of the input signal. By adding the
It becomes possible to clamp stepped signals with a very simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the recording system of an electronic switch camera to which the clamp circuit of the present invention can be applied, Fig. 2 is a waveform diagram of a stepped line sequential color difference signal and a waveform diagram of a conventional clamp pulse, and Fig. 3 is a block diagram showing an embodiment of the clamp circuit of the present invention, FIG. 4 is a waveform diagram of each part of FIG. 3, FIG. 5 is a specific circuit diagram of FIG. 3, and FIG. 6 is included in FIG. 5. FIG. 3 is an equivalent circuit diagram of a high-pass filter and a low-pass filter. In addition, in the symbols used in the drawings, 20...
Clamp circuit, 21... High pass filter, 22
. . . low-pass filter, 23 . . . adder.

Claims (1)

[Claims] 1. A circuit for clamping a stepped input signal in which signal portions of a predetermined cycle to be clamped are alternately at first and second levels, wherein the first and second level of the input signal to be clamped are A circuit that clamps the level parts so that they are at the same potential, a circuit that extracts the DC component of the clamp output, a circuit that extracts the AC component of the input signal, and a circuit that extracts the extracted DC and AC components. A clamp circuit for a stepped signal, comprising a circuit for adding.