JPH0561564A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce cross skew by making input and output characteristics equal each other to a clock signal for each circuit block of the semiconductor integrated circuit, connecting input terminals in common, and providing combined buffers composed of the prescribed number of unit clock buffers arranged adjacently one and another. CONSTITUTION:The input and output characteristics are made equal each other, the input terminals are connected in common, and plural combined buffers 1 are provided while being composed of unit clock buffers (B1-Bm) arranged adjacently one and another. Since the unit clock buffers B1-Bm having the mutually equal input and output characteristics in respect to the clock signal are adjacently arranged on a chip area, propagating time from the clock signal source of this LSI can be made equal among the respective unit clock buffers, and time for signal propagation to a clock signal load can be easily made equal one and another.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to improvement of a clock circuit in a semiconductor integrated circuit (LSI) such as a gate array which is required to operate at high speed.

The operation speed of application-specific LSIs (ASICs) has been increasing more and more in recent years, and CMOS LSIs have an operating speed of 40M.
In the case of Hz and Bi-CMOS LSI, an operating speed exceeding 100 MHz is required. For such high-speed operation, it is necessary to minimize the difference in propagation time of the clock signal supplied as a synchronizing signal to the sequential circuits between the sequential circuits.

[0003]

2. Description of the Related Art A clock circuit in a conventional LSI will be described with reference to FIG. The figure is a block diagram illustrating the configuration of a general clock circuit. The clock signal is supplied from the main clock buffer forming the clock signal source of the LSI to each area portion (circuit block) on the chip area.
It is input to the clock buffers 1 to N arranged for each
These clock buffers 1 to N are applied to each driven cell (clock signal load) such as a sequential circuit.

As illustrated, the clock buffer 1 is connected to 200 driven cells, and the clock buffers 2 and N are connected to 50 and 20 driven cells, respectively, to receive clock signals. Even if the output rise characteristics of each clock buffer are considered to be as uniform as possible according to the load capacitance, there may be a difference in the propagation time from the master clock buffer to the transmission of the clock signal to each driven cell. Is inevitable.

The above difference in propagation time is generally called a clock skew. The clock skew is one clock cycle in order to maintain the accuracy of signal transmission in this LSI.
It is necessary to suppress it to 0% or less.

For example, in a high-speed LSI whose operating frequency exceeds 100 MHz, the clock cycle is 10 nanoseconds, so the clock skew must be 1 nanosecond or less.

However, in the conventional clock circuit in which the number of driven cells is different for each clock buffer as described above, a clock skew of, for example, about 2 to 3 nanoseconds is unavoidable. Can't be satisfied.

[0008]

Problems to be Solved by the Invention JP-A-63-7861
No. 1 gazette discloses a dummy load (pseudo load) which is connected to a clock circuit portion having a small load capacitance due to a difference in load capacitance of each portion of the clock circuit caused by a difference in length of clock wiring or a gate capacitance of a driven cell. It is disclosed that this dummy load eliminates the difference in clock signal propagation time based on the difference in load capacitance.

However, according to the method described in this publication, there is a problem that the layout efficiency of the LSI is deteriorated because a large amount of dummy load is required in a specific chip area portion.

In Japanese Laid-Open Patent Publication No. 61-82525, the output terminals of all clock buffers in the chip are connected in common to unify the rise time of each driven cell, thereby causing a difference between each driven cell. It is disclosed that clock skew is eliminated.

However, in the case of the method described in this publication,
The wiring that connects the output terminals of each clock buffer in common has a large parasitic capacitance because the clock buffers are arranged at distant positions on the chip area. There is a problem that the rise of the clock signal is extremely delayed and the propagation of the clock signal is greatly delayed in exchange for the reduction of the clock skew, which hinders the speeding up of the LSI.

In view of the above-mentioned problems of the prior art in reducing the clock skew, the present invention can suppress the decrease of the chip area efficiency as much as possible and can reduce the clock skew without causing a significant delay in the propagation of the clock signal. An object of the present invention is to provide a semiconductor integrated circuit having a clock circuit.

[0013]

FIG. 1 is a circuit diagram of a combination buffer forming the principle of the present invention. In the figure,
Reference numeral 1 is a combination buffer, and B _{1 to} B _m are unit clock buffers.

To achieve the above object, the semiconductor integrated circuit of the present invention has, as shown in FIG. 1, input and output characteristics with respect to a clock signal being substantially equal to each other and having their input terminals commonly connected. It is characterized by comprising a plurality of combination buffers (1) each comprising a predetermined number of unit clock buffers (B _{1 to} B _m ) arranged close to each other.

[0015]

By providing unit clock buffers having substantially the same input and output characteristics as each other with respect to the clock signal in the vicinity of each other on the chip area, the propagation time of the clock signal from the clock signal source of this LSI is controlled by each unit clock. It is easy to make the buffers substantially equal and it is easy to make the signal propagation times from each unit clock buffer to each clock signal load substantially the same as each other.
Further, since the number of unit clock buffers arranged in each combination buffer is the same predetermined number, it is easy to make the propagation times of the clock signals transmitted from the clock signal source to each combination buffer the same. Is.

Preferably, the number of clock signal loads connected to each unit clock buffer to which the clock signal load is actually connected is equal or approximate to each other. As a result, the unit clock buffer arranged in each combination buffer is
The number of clock signal loads is the same or similar number of connected buffers or not connected at all.

With the above structure, the rise time of the output of the small buffer to which the load is actually connected can be unified as a whole, and the clock skew generated in the load can be reduced.

When an unbalanced load number occurs between the small buffers, the clock skew caused by this can be avoided by connecting the number of pseudo loads corresponding to the unbalanced number.

By adopting a configuration in which the output terminals of the small buffers are commonly connected to each combination buffer, it is possible to avoid clock skew caused by the difference in the characteristics of each load and the elements constituting the buffer.

By providing corresponding sub clock buffers in the circuit blocks in which the respective combination buffers are arranged, the clock signals transmitted from the clock signal source to the respective circuit blocks can have the same propagation time. It will be easy.

[0021]

The present invention will be further described with reference to the drawings. Figure 2
FIG. 6 is a circuit diagram illustrating a combination buffer in an LSI of an embodiment of the present invention and a sub clock buffer arranged in the preceding stage.

In FIG. 2, this combination buffer 1 is 1
0 unit clock buffer (small buffer) B ₁
To B ₁₀ . These small-sized buffers B _{1 to} B ₁₀ have their respective input ends connected in common, are connected to the output end of the sub-clock buffer (sub-buffer) SB at the preceding stage, and receive a clock signal from them.

Each of the small buffers B _{1 to} B ₁₀ is provided in one circuit block on the chip area, and is connected to each of the output terminals labeled “output 1” to “output 10” in the figure. The number of driven cells 1U that are arranged close to these small buffers and have the same input characteristics as each other is connected up to a maximum of 20 and close to 20. That is, the number of load units of the small buffer is 20.

Each of the small buffers B _{1 to} B ₁₀ may be collectively arranged at a specific position of one circuit block on the chip area, or may be individually arranged for each set of driven cells forming respective loads. Therefore, it is possible to disperse the circuit blocks.

As shown in the figure, the sub-buffer SB is provided outside the combination buffer and can supply a clock signal from one sub-buffer to a plurality of combination buffers 1 in parallel. The clock signals may be supplied to one combination buffer provided in a one-to-one correspondence, and the combination buffer 1 may include a sub-buffer SB, which is different from the one shown in the drawing.

FIG. 3 shows a clock circuit diagram in the LSI of one embodiment of the present invention including the combination buffer shown in FIG. In the figure, each combination buffer 1 ₁ to
1 _n is provided with ₁₀ small buffers B _{1 to} B ₁₀ , each of which is a main clock buffer MB forming a clock signal source.
From the sub-buffers SB _{1 to} SB _n to the corresponding combination buffers 1 ₁ to 1 _n . In this case, this clock circuit has a depth of 2
It has a hierarchical structure of. As the scale of the LSI increases, a multi-tiered hierarchical structure can be provided.

Each of the combination buffers 1 ₁ to 1 _n has the first combination buffer 1 ₁ of 20 according to the number of driven cells included in the circuit block in which the combination buffer is arranged.
The clock signals are supplied to 0 driven cells, the second combination buffer 1 ₂ to 100 driven cells, and the nth combination buffer 1 _n to 20 driven cells. There is.

As shown in FIG. 3, 20 buffer cells (lu) are connected to each of the small buffers B _{1 to} B ₁₀ and _one buffer cells are not connected at all. is there. With this configuration, the outputs of the small buffers to which the driven cells are actually connected have the same rise time because their loads are equal to each other, and thus the outputs are transmitted from the small buffers to the driven cells. The propagation time of the clock signal is substantially the same between the small buffers.

The sub-buffers SB _{1 to} SB _n have the same input and output characteristics. Further, each sub-buffer SB ₁ to SB _n equal number of small buffers B ₁ ~
The combination buffers 1 ₁ to 1 _n composed of B ₁₀ are connected, and the sub-buffers SB _{1 to} B _n and the combination buffers 1 ₁ to ₁
Since the signal wiring to 1 _n is short, each sub-buffer SB ₁
The propagation times of the clock signals transmitted from ~ SB _n to the corresponding combination buffers 1 ₁ to 1 _n are substantially the same.

As described above, in the LSI of the embodiment shown in FIG.
Main clock buffer MB to each sub-buffer SB ₁
If the wiring lengths of the clock signals up to SB _n are made equal to each other, the propagation times of the clock signals transmitted from the main buffer MB to the driven cells at the ends can be made substantially the same. Clock skew can be greatly reduced. In the case of the figure, the number of driven cells arranged in each circuit block is a multiple of the unit number of driven cells connectable to the small buffer.

4A and 4B are circuit blocks.
The number of driven cells placed in the can be connected to a small buffer
Explained an example that is not a multiple of the number of driven cells (the number of units)
The second combination buffer 1 shown in FIG.₂
If the number of driven cells that receive output from
The results are shown below. In FIG. 3, the second combination buffer 1 ₂
The number of driven cells was 100 lu, but in the figure (a) and
In (b), the number of driven cells is shown as 50 lu, respectively.
It Other combination buffer 1₁1_nThe load number of is shown in Figure 3
It is a thing.

In FIG. 4A, the 50 driven cells in this circuit block are three small buffers B _{1 to} B _3.
The load is divided into 17, 17, and 16, respectively. In this case, the other combination buffer 1 ₁ shown in FIG.
Number of loads connected to each small buffer in 1 _n 20
Since the number of the driven cell is small only 3-4 than, rises faster driven cell for receiving an output from the second combination buffer 1 _2, clock skew occurs.

The clock skew can be kept as small as possible by making the number of units connected to the small buffer as small as possible. For example, in the above case, if the unit number of driven cells connected to each small buffer is 10, all loads of each small buffer are 10 lu.
The clock skew generated between the driven cells can be avoided. However, if the number of driven cells connected to the small buffer is too small, the number of small buffers increases and the cost increases.

FIG. 4 (b) shows another method for avoiding the clock skew in FIG. 4 (a). In this way, with respect to the unit number 20 each small buffer B ₁ .about.B ₃ load is small relative to the driven cell, the clock skew by respectively connecting the number of dummy load only corresponds to the small number To avoid.

In the case of the present invention, since the clock signal is transmitted from the unit clock buffer to a relatively small number of driven cells, a dummy load added to the relatively small unit clock buffer. The number of can be kept small, and unlike the conventional example in which load balancing is performed between circuit blocks that are large area portions, a large amount of dummy load is not required.
When the LSI is a gate array type ASIC, it is relatively easy to use such a small number of dummy loads.

FIG. 5 is a circuit diagram of a clock circuit in the LSI of the second embodiment of the present invention. A circuit adopting a method of further reducing the clock skew in addition to the method shown in FIG. 4B. Is shown. In FIG. 5, the output terminals of the small buffers to which the driven cells are connected are commonly connected to each of the combination buffers 1 ₁ and 1 ₂ .
The clock skew caused by the difference in the characteristics that inevitably occurs between the driven cells and the transistor elements that form the small buffer, or the difference in the parasitic capacitance of the signal wiring that transmits the clock signal from each small buffer to the driven cell I'm avoiding it.

The small buffers in the combination buffers 1 ₁ to 1 _n are all arranged in the same circuit block as described above, and therefore, the output terminals of the clock buffers in the entire chip area shown in the conventional example. Unlike the case of connecting in common, the length of the wiring connecting the output ends of the small-sized buffers is relatively short, and the parasitic capacitance is not greatly increased by this connecting wiring and the propagation time is not excessively long.

FIG. 6 is a schematic plan view of the chip area in the LSI of the third embodiment of the present invention. The chip area is equally divided into 4 × 4, and subbuffers having the same input and output characteristics are arranged in each area portion.

The main clock buffer MB, which constitutes the clock signal source, is arranged almost at the center of the chip area, and from this main clock buffer MB to each sub-buffer SB.
The clock signal wiring that transmits the clock signal to
They are arranged symmetrically with respect to respective center lines passing through the main clock buffer and running in the horizontal direction and the vertical direction in the drawing.

As shown in FIG. 6, the wiring is branched so that the wiring lengths from the main clock buffer MB to the respective sub-buffers SB are equal to each other, and at each wiring branch point, The sub-buffers SB that configure the loads are distributed so that the total capacities of the loads that receive signals from the branch wirings following the branch points are equal to each other. A corresponding combination buffer is provided in the vicinity of each of the sub-buffers, and the mutual layout relationship between the circuit blocks is the same.

With the above buffer arrangement and wiring configuration, in this LSI, the signal propagation times from the main clock buffer to each sub-buffer are equal to each other. If the LSI of this embodiment adopts the circuit configuration of FIG. 5, for example, Clock skew can be reduced to a negligible amount.

The layout relationship of the main clock buffer, sub-buffer and combination buffer is LS.
Gate array LSI in which the internal arrangement has a periodic structure
Is particularly preferable in. In the gate array LSI, these layout relationships are common to all the LSIs.

An example of clock skew that can be realized in each embodiment of the present invention is shown below. Conventionally, a clock skew of about 2 to 3 nanoseconds is unavoidable due to the configuration of the clock circuit, even if the characteristics of each semiconductor element itself are different. In this case, the upper limit of the operating frequency in the LSI is about 5
It was 0 MHz.

However, by adopting the present invention, for example, in a part of the clock circuit of FIG. 3, the driven cells are connected as shown in FIG. Even if the imbalance occurs, the clock skew is reduced to about 0.7 to 1.2 nanoseconds.
Therefore, the clock frequency at which the LSI can operate is 1
About 00MHz is possible.

By connecting a dummy load to the load of each small buffer as shown in FIG. 4B, the clock skew reduced as described above is further reduced to about 0.5 to 1.0 nanosecond. The operating frequency can be up to about 120 MHz. Further, in this case, if the arrangement configuration shown in FIG. 6 is adopted, this clock skew becomes substantially negligible, and the operable clock frequency is 200M.
Reach up to about Hz.

In each of the above embodiments, the number of small buffers in the combination buffer and the number of driven cells connected to the small buffers are set to 10 and 20, respectively.
These numbers can be set to appropriate numbers for each LSI.

Further, in each drawing, each clock buffer is shown as a buffer of positive polarity, but as is well known, it is possible to employ a clock buffer of opposite polarity, and a NAND type buffer. A clock buffer can also be adopted.

The clock circuit in the LSI of the present invention is
In particular, it is suitable as a circuit for a clock signal having a high repetition frequency such as EWS, a large-sized computer, a minicomputer or a communication device which requires ultra-high speed operation.

[0049]

As described above, according to the semiconductor integrated circuit of the present invention, the clock skew in the clock circuit can be reduced without lowering the area efficiency of the circuit and causing a large delay in the propagation of the clock signal. It has a remarkable effect that it enables high speed operation.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a circuit diagram of a combination buffer according to an embodiment of the present invention.

FIG. 3 is a clock circuit diagram in the LSI of the first embodiment of the present invention.

4 (a) and (b) are another load connection example of the second combination buffer in FIG. 3, respectively.

FIG. 5 is a clock circuit diagram in an LSI according to a second embodiment of the present invention.

FIG. 6 is a plan view of a chip area in an LSI according to a third embodiment of the present invention.

FIG. 7 is a clock circuit diagram in a conventional LSI.

[Explanation of symbols]

1, 1 ₁ to 1 _n : Combination buffer B _{1 to} B ₁₀ , B _m : Unit clock buffer (small buffer) SB _{1 to} SB _n : Sub clock buffer (sub buffer) MB: Main clock buffer

Claims (6)

[Claims] 1. A predetermined number of unit clock buffers (B _{1 to} B _m ) having substantially the same input and output characteristics with respect to a clock signal, having their input terminals connected in common, and arranged close to each other. A semiconductor integrated circuit comprising a plurality of combination buffers (1) each comprising 2. A semiconductor integrated circuit according to claim 1, characterized in that it comprises the unit clock buffer clock signal load is not connected to the output terminal (B1~B _m). 3. The unit clock buffers (B ₁ ~
3. The semiconductor integrated circuit according to claim 1, wherein a pseudo load for adjusting the load capacitance is connected to a part of B _m ). 4. The output terminals of the unit clock buffers (B _{1 to} B _m ) to which clock signal loads are connected are commonly connected to each of the combination buffers (1 ₁ to 1 _n ). The semiconductor integrated circuit according to claim 1. 5. Each of the combination buffers (1₁~ 1_n) Neighborhood
Corresponding to the output terminal of the combination buffer (11 ~
1_n) Said commonly connected unit clock buff
A (B ₁~ B_m) And the input end
Sub clock buffer (SB₁
~ SB_n) Are provided, Claim 1 thru | or 4 characterized by the above-mentioned.
1. The semiconductor integrated circuit described in 1. 6. Each clock signal load is within a predetermined number
A chip area including a plurality of area parts, and one mass forming a clock signal source arranged in the chip area.
Clock buffer (MB) and each area part
A plurality of sub clock buffers (SB ₁~ S
B_n) From the master clock buffer (MB) to each subclock.
Lock buffer (SB1 to SB_n) To the clock signal
From the master clock buffer (MB).
Book clock buffer (SB₁~ SB_n) The above
So that the propagation distances of the signal are equal to each other, and
From the master clock buffer (MB) to each sub clock
Buffer (SB₁~ SB_n) At each wiring branch point
Then, the signal is sent via each branch wiring that follows the wiring branch point.
Sub clock buffer (SB₁~ SB_n)
Clock signals routed so that the number of
Wirings are respectively arranged in the respective area portions and are commonly connected.
The input end of each sub clock buffer (SB₁~
SB_n) Connected to the respective output terminals of
The combination buffer (1₁~ 1_n) And each unit clock buffer (B₁~ B_m) Either
To the clock signal load of each area portion via
A semiconductor integrated circuit that supplies a clock signal.