JPH0561455A - Video display device - Google Patents

Abstract

PURPOSE:To facilitate superposition display and to perform the display of digital data in real time. CONSTITUTION:This device is provided with such feature providing video memory on which display data from a video input device 11 is written sequentially in sequence of display address from a digital input device 21 and which always holds video data of one screen, digital memory 24 on which the write/update of the display data arranged in sequence of display address are performed cyclically and the digital data of one screen is always held, a mixer 3 which performs the superposition processing of the video data of one screen and the digital data at every display address and outputs a result to a display means 5, and a timing generator 4 which sets the write cycle of the digital data of one screen differently from that of the video data of one screen on the video memory and also, conforms the readout cycle of the digital data of one screen from the digital memory 24 to that of the video data of one screen from the video memory.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device using a large color display board or the like as a screen.

[0003]

2. Description of the Related Art Conventionally, as this type of image display device, there is an image display device in which a large number of light-emitting elements such as light bulbs and LEDs are arranged on a display board to display an image like an ordinary television. A video signal (video signal) can be input to such a display board. This video signal is an analog signal of the NTSC system, and after being decomposed into color signals R, G, B by a color decoder, A / D
The digital signal is converted by the conversion unit. This digital signal, after undergoing processing such as gradation by the video signal processing unit, is output to the display board side via the output selection unit,
Images are displayed by changing the brightness of each light emitting element based on gradation. Here, each unit is controlled based on the synchronization signal from the timing generator. Horizontal and vertical synchronizing signals V and H included in the video signal are input to the timing generator.

The display on the display board is not limited to such a video display, but digital characters, graphics, etc. can also be displayed. As the display form, there are superimposition display with video display, digital single display, scroll display of digital information, and the like. In order to display such digital information, first, a digital input device for inputting digital information to be displayed is provided. The digital information input by the digital input device is written in the first digital memory or the second digital memory through the selector under the control of the CPU. Here, the first digital memory writes digital information for one screen, and the second digital memory reads digital information for one screen stored in advance while writing the first digital memory. , The first and second digital memories are alternately written and read to speed up the process. Here, in the first and second digital memories, as one screen for each display screen, in the case of color, substantially three screens for R, G, and B,
When further gradation is added, for example, when 64 gradations are required for each of R, G, and B, a depth of 6 screens is provided.
Digital memory for (= 6 × 3) screens is required.

[0005]

By the way, the reading speed of video data is about 16.6 nanoseconds for one screen, while the writing speed of digital data is at most 3 seconds. Therefore, when the digital data is displayed by superimposing it on the video data, the conventional means switches the digital data on the screen every 3 s,
Characters do not flow smoothly when displaying non-flowing characters.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a video display device which facilitates superposition display and can display digital data in real time.

[Constitution of Invention]

[0008]

A video display device of the present invention is a video display device having a built-in digital memory for displaying digital data on a screen, in which display data from a video input device is sequentially written in display address order. A video memory for holding one screen of video data at all times, a digital memory for cyclically writing and updating display data from a digital input device in the order of display addresses, and constantly holding one screen of digital data; 1 read from video memory and digital memory in order of address
A mixer that superimposes video data and digital data for each screen for each display address and outputs the data to the display means, and a writing cycle of digital data for one screen to the digital memory is the video for one screen to the video memory. A timing generator which is different from the data writing cycle and which makes the reading cycle of the digital data for one screen from the digital memory coincide with the reading cycle of the video data for one screen from the video memory. It is characterized by.

[0009]

[Action]

[0010]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an outline of an image display device according to an embodiment of the present invention. The video display device shown in FIG.
Display means 5 including a digital processing unit 2, a mixer 3, a timing generator (TG) 4 and a video display board,
The mixer 3 and the display means 5 are connected by a display memory 6, a driver 7, and the like. The driver 7 controls the lighting output from the high frequency lighting circuit 8 for dimming,
Power is supplied to the display means 5. Video processing unit 1
Is a driver 7 for generating a video or TV signal, a video analog signal from the driver 7 for each color signal R,
A color decoder 12 for decomposing into G and B, an A / D converter 13 for converting the color decoder 12 signal into a digital signal,
A video selector 14 for controlling writing and reading to and from the video memories A and B for two screens, a mixer 3, and a TG 4 for supplying a timing signal to each circuit are provided. Further, the display unit 5 is configured by arranging a large number of red, green, and blue light emitting elements on a matrix, and controlling the gradation of each of these light emitting elements based on the video data from the video processing unit 1. The image is displayed. This video signal is processed by the video signal processing unit such as gradation, and then output to the display board side through the output selection unit,
Images are displayed by changing the brightness of each light emitting element based on gradation.

Next, the digital processing section 2 will be described. First, a digital input device 21 for inputting digital data to be displayed is provided. The digital data input by the digital input device 21 is CP
It is written in the digital memory 24 via the digital selector 23 under the control of U22. Here, in the digital memory 24, in the case of color as one screen of the display screen, substantially three screens for R, G, B are added, and further gradation is added,
For example, when 64 gradations are required for each of R, G, and B, the digital memory 24 for 18 (= 6 × 3) screens having a depth of 6 screens is provided. Further, the digital memory 24 is for writing digital data of addresses 1 to n for one screen and keeps updating the addresses 1 to n cyclically as long as data is sent from the CPU 22 and always holds the latest data. There is.

Further, the AR is input to the digital selector 23, and during the image reading period of RWCK described later, the AR is
The data corresponding to the address designated by is read by the mixer 3.

Each part is controlled based on a synchronization signal from the timing generator 4 shown in FIGS. Each sync signal from the timing generator 4 is produced by inputting horizontal and vertical sync signals V and H included in the video signal from the color decoder 12.

Next, the operation of the video display device having the above configuration will be described with reference to FIGS. It is assumed that the video display in the video processing unit 1 is performed based on a sync signal having a cycle of 1/60 seconds as shown in (a), for example. In this case, as the control signal MS, as shown in (b), a synchronizing signal that is alternately switched between high level and low level at the falling edge is used, and such a control signal MS is applied to the digital input device 21. , By this, the sync signal 1 for the video memory A and the video memory B
Data for one screen is written and data is read alternately every cycle. AW is video data write signal, AR
Is a video data read signal, and AWP is a video data write pulse. At the moment when the video memory receives the video data write pulse by AND with AW, the data of the specified address is written in the video memory. For example, as shown in (c) and (d), the video memory B is in the read state R when the video memory A is in the write state W, and the video memory B is written in the cycle when the video memory A is in the read state R. It becomes the embedded state W. In this case, data writing to each video memory is performed according to the input timing of the video data input to the video selector 14. Due to the limitation of the size and number of the light emitting elements of the display means 5, a large-screen image display device normally displays an image using only the image data of the television signal, for example, near the center of the screen. Therefore, the writing of the video data to each video memory can be output in a part of the time of each cycle of the synchronization signal. On the other hand, since the video data can be read from the video memories A and B at a speed at which the video data can be supplied to the respective light emitting elements of the display means 5 in accordance with the video operation timing, for example, almost one of the sync signals. It can be done at a slower rate using a period of time. Therefore, by switching the video selector 14, the video data is alternately read from the video memories A and B and transmitted to the display means 5 via the mixer 3, the display memory 6 and the driver 7. Although the above description is for each screen of the video data, the read state R is a period for reading data for one screen from 1 to n, and (f) in FIG.
1 to 3 depending on the AR signal from TG4 as shown in (g).
Data of X, X + 1, and X + 2 to n are read out at 250 nanoseconds per address.

Next, the digital data processing will be described. The RWCK of the H and L signals is given to the digital selector 23 from the TG4 at a cycle of 250 nanoseconds, and the H of the RWCK is set to H.
L of DWP is applied to the digital memory 24 in response to the rising edge of. Digital selector 2 when RWCK is in H state
3 passes the DW address and data from the CPU 22 through the digital memory 24, and writes the DW address and data with the L signal of DWP. By this writing, TG4 to C
The ACK is returned to the PU 22, and the CPU 22 receives the ACK and performs a process for setting the next digital data (address and data indefinite period). Next, when RWCK is L, the digital selector 23 selects AR, and A
The R is also input to the video memory, and the data at the address X, for example, is sent from the digital memory 24 and the video memory to the mixer 3, subjected to overlay processing, and written in the display memory 6. That is, the digital data is (h), (i)
As described above, data is written in a long cycle different from (f) and (g) and is read in cycles of (f) and (g).

In the above embodiment, the scanning cycle of the display means 5 is set to 1/60 seconds, and a part of the television signal such as the NTSC system is used as the video data displayed on the display means 5. As described above, for example, the video scanning period of the display means 5 is set to be longer than 1/60 seconds, and the video data is written to each video memory by inputting one screen of video data of the television signal. The writing and the data reading from each of the video memories A and B can also be performed at a timing according to the scanning cycle of the display means 5.

[0017]

According to the video display device of the present invention, the writing cycle of digital data for one screen to the digital memory 24 is made asynchronous with the writing cycle of video data for one screen to the video memory, and Since a timing generator for matching the read cycle of the digital data for one screen from the memory 24 with the read cycle of the video data for one screen from the video memory is provided, the display data for the video memory and the digital memory 24 can be displayed. The writing speed can be written according to the speed of each display data sent from the video input device 11 and the digital input device 21, and the read cycle of digital data for one screen from the digital memory 24 can be set to one screen from the video memory. Since it matches the read cycle of the minute video data, De sent from Mori - Heavy combined processing can be simplified in order to address other matches. Further, since the display data from the digital input device 21 is sequentially and cyclically written and updated, and the digital memory 24 that always holds the digital data for one screen is provided, the read data from the digital memory 24 is: It is always the latest, digital data for superimposition display can be displayed in real time, and since the digital memory 24 is not switched as in the conventional case, for example, when moving characters are displayed, the character movement display is smoothly performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram for explaining video data processing according to an embodiment of the present invention.

FIG. 3 is a timing diagram for explaining digital data processing according to an embodiment of the present invention.

[Explanation of symbols]

5 ... Display means, 11 ... Video input device, A, B ... Video memory, 21 ... Digital input device, 24 ... Digital memory,
3 ... mixer, 4 ... timing generator.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 5/66 D 7205-5C

Claims (1)

[Claims] 1. A display means having a display screen; a video input device; a video memory which sequentially writes display data from the video input device in the order of display addresses and holds video data for one screen at all times; digital input A device; a digital memory for cyclically writing and updating display data in the order of display addresses from the digital input device, and holding digital data for one screen at all times; and reading sequentially from the video memory and the digital memory in the order of addresses. A mixer that superimposes video data and digital data for one screen for each display address and outputs to the display means; a writing cycle of digital data for one screen in the digital memory for one screen in the video memory. The writing cycle of the video data of A video display device, characterized in that provided with the; reading period Tal data and timing generator match a read cycle of the video data for one screen from the video memory.