JPH0560267B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a read-only semiconductor memory device in which data can be electrically erased, and particularly to a semiconductor memory device with a high integration density of memory cells.

[Technical Background of the Invention] A read-only semiconductor memory device in which data can be electrically erased is known as an EEPROM. FIG. 7 is a circuit diagram showing the basic configuration of the memory cell. This memory cell has select gate SG
A selection MOS transistor 1 having a control gate CG and a data storage MOS transistor 2 having a floating gate FG are connected in series, and the open end of the selection MOS transistor 1 is connected to the drain D. The open ends of the data storage MOS transistors 2 are connected to the sources S, respectively.

When this cell is realized using, for example, a single-layer polycrystalline silicon process, the device structure will be as shown in the pattern plan view of FIG. In the cell shown in FIG. 8, a P-type semiconductor substrate is used, and 11 is the data storage MOS transistor 2 consisting of an N-type diffusion region.
12 is a floating gate (FG) of MOS transistor 2 for data storage made of a polycrystalline silicon layer, 13 is an N-type diffusion region and serves as the source of MOS transistor 1 for selection and the floating gate (FG) of MOS transistor 2 for data storage. A common region consisting of the drain of the MOS transistor 2, 14 the source (S) consisting of an N-type diffusion region, 15 the drain (D) consisting of an N-type diffusion region, and 16 the selection region consisting of a polycrystalline silicon layer. This is the selection gate (SG) of the MOS transistor 1, and a region 17 surrounded by a broken line in the figure is a region in which a thin insulating film for the gate is provided.

The operating principle of such a memory cell is that data is stored by exchanging electrons between the common area 13 and the floating gate 12 using a thin insulating film in the area 17 surrounded by the broken line. for
The threshold voltage Vth of the MOS transistor 2 is changed, thereby programming or erasing data. An example of bias relationships and logic when programming, erasing, and reading data is summarized in FIG. 9.

Electrons are injected into and emitted from the floating gate 12 by utilizing a tunneling phenomenon caused by a thin insulating film in the region 17, particularly in a portion 18 where the floating gate 12 and the common region 13 overlap. In addition,
In order for a tunnel current to flow through the thin insulating film in this portion 18, an electric field of about 10 MV/cm is required, and if the thickness of this thin insulating film is set to about 100 Å, the externally supplied voltage will be as shown in Figure 9. A high voltage of 20V is used as shown in .

[Problems with the Background Art] By the way, the disadvantages of the conventional cell structure described above are its integration density and the conductance gm of the transistor.
It is in. This is particularly due to the fact that a high voltage is applied to the source and drain during programming, so the transistor must have a high breakdown voltage structure. The above is illustrated using the dimensions drawn in the pattern plan view of FIG. 8 as follows.

In order to avoid the short channel effect, the channel length of the data storage MOS transistor 2, which is indicated by the width L ₁ and the dimension L ₂ of the selection gate 16, must be widened, and it is necessary to adopt the minimum dimension here. Can not.

(b) In order to avoid breakdown mode due to electric field concentration between the drain and gate, the common area 13,
The impurity concentration in the drain 15 must be lowered. This reduces the gm of the transistor,
This causes a decrease in the sense margin of cell data and a deterioration in access time. Therefore, in order to reduce such effects, the channel width W of the selection MOS transistor 1 is made large.

C. Since the drain contact part is highly doped to lower the contact resistance, there is a margin for mask alignment between the contact part and the selection gate 16, etc.
L ₃ must be fully accounted for.

The above matters are the same even when a memory cell is realized using a known two-layer polycrystalline silicon process.
This is a factor that reduces the integration density and the conductance of memory cells.

Furthermore, during programming, the floating gate 12 is biased to a negative potential with respect to the drain 15, so a depletion layer is generated directly under the thin insulating film portion 18 and the applied voltage is divided, resulting in a tunnel current. It is necessary to apply a larger voltage to cause the current to flow through the floating gate 12, and the thin insulating film portion 1
The impurity concentration directly below 8 must be increased. This is a cause of deteriorating the film quality of the thin insulating film portion 18 and lowering the withstand voltage with the substrate. However, when erasing data, the floating gate 12 is positively biased, so a depletion layer as described above is not generated, and there is no need to make the impurity concentration higher than necessary.

[Object of the Invention] The present invention has been made in consideration of the above-mentioned circumstances, and its object is to provide a semiconductor memory device in which the integration density of memory cells is high and the conductance of transistors is large.

[Summary of the Invention] A disadvantage of conventional cells is due to the high voltage applied to the drain during programming. Therefore, in the semiconductor memory device of the present invention, electrons are emitted from the floating gate in a region different from the region where they are injected. That is, data is identified by changing the threshold voltage of the floating gate transistor according to the amount of charge stored in the floating gate made of a first conductive material provided on the semiconductor substrate. In a memory cell, a control gate contacts the floating gate through an insulating film and controls the potential of the floating gate to control charge injection into the floating gate by utilizing a tunneling phenomenon of the insulating film; a programming gate made of a second conductive material that contacts through an insulating film and controls the potential thereof to control the release of charges accumulated in the floating gate by utilizing the tunneling phenomenon of the insulating film; The control gate and the programming gate are used to erase and program data in the memory cell, respectively.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 shows a memory cell of a semiconductor memory device according to the present invention, which is composed of two MOS transistors as shown in FIG.
FIG. 3 is a plan view of a pattern in the case of a transistor. Note that the memory cell of this embodiment also has the eighth
As shown in the figure, it is realized using a single-layer polycrystalline silicon process. The difference between the memory cell shown in FIG. 1 and the one shown in FIG. 8 is that a programming gate 19 made of metal such as aluminum is placed on the floating gate 12 via an insulating film (not shown). Other parts corresponding to those in FIG. 8 will be described with the same reference numerals. That is, as shown in FIG. 7, this memory cell is constructed by connecting a selection MOS transistor 1 and a data storage MOS transistor 2 in series.
The source 14 of the MOS transistor 2 is composed of an N-type diffusion region, and the common region 13 that becomes the drain of the data storage MOS transistor 2 and the source of the selection MOS transistor 1 is a common region arranged adjacent to the source 14. The drain 15 of the selection MOS transistor 1 is composed of an N-type diffusion region.
is composed of an N-type diffusion region disposed adjacent to the common region 13 in a direction perpendicular to the extension line formed by the source 14 and the common region 13. Further, the control gate 11 of the data storage MOS transistor 2 is provided in a direction parallel to the extension line formed by the source 14 and the common region 13. A floating gate 12 is provided on the control gate 11 via an insulating film, and a part of the floating gate 12 is connected to the source 14 and a common region 13.
Another part of the floating gate 12 is placed over the common region 13 with an insulating film interposed therebetween. A select gate 16 is provided between the common region 13 and the drain 15 via an insulating film, and the select gate 16 extends in a direction perpendicular to an extension line formed by the source 14 and the common region 13. Also, the above source 14
A programming gate 19 is provided between the floating gate 12 and the common region 13 via an insulating film, and the programming gate 19 extends in a direction perpendicular to the extension line formed by the source 14 and the common region 13. has been done.

FIG. 2 is a cross-sectional view of the memory cell shown in FIG. This is an insulating layer, and 22 is a gate insulating film provided on the control gate 11 and the like. As shown in the figure, a protrusion called an asperity is formed on the upper surface of the floating gate 12 made of a polycrystalline silicon layer.

In a memory with such a configuration, when electrons are released from the floating gate 12 (programming), the control gate 11, which has a large capacitive coupling with the floating gate 12, is set to a low potential, and the programming gate 19 is raised to a high potential. Just let it happen. As described above, the electric field can easily concentrate on the upper surface of the floating gate 12 due to asperity, and electrons can easily be emitted. In fact, the downward tunneling current is approximately
An electric field of about 10 MV/cm is required, but upward tunneling current occurs with an electric field of about 3 to 5 MV/cm. At this time, source 14 and drain 1
5 has a small capacitive coupling with the floating gate 12, so
The potential of the selection gate 16 may be set to a certain potential, and the potential of the selection gate 16 may be set to an arbitrary potential.

On the other hand, when injecting electrons into the floating gate 12 (erasing data), the control gate 11 is set to a high potential as in a normal cell, the source and drain are lowered to a low potential, and the potential of the selection gate 16 is set to a transistor. raise the potential to such a level that it turns on. At this time, the potential of the floating gate 12 follows the potential of the control gate 22 and rises to a high potential, so
Electrons are injected into the common region 13 or the floating gate 12 through the thin insulating film portion 18 . At this time, if the potential of the programming gate 19 is set to a low potential, the programming gate 19 will not adversely affect the erase operation. The reason for this is that, as already mentioned, electron emission from the top surface of the polycrystalline silicon layer is easy;
The thickness of the insulating film 20 in this part can be made relatively thick, and if the layout is devised to reduce the contact area between the programming gate 19 and the floating gate 12, the capacitance between this part is compared to the capacitance of other parts. This is because it can be made smaller.

As described above, if the cell of this embodiment is used, the source and drain are both at the same level during data erasing and programming, and a high potential is not applied to only one of them, so a high breakdown voltage structure is not required for the transistor. Therefore, the minimum dimension can be used for the channel length of the transistor, gm is large since there is no low concentration region, the channel width W can be made relatively narrow, and there is no need to take mask alignment margin into account. Further, as shown in FIG. 1, since the sources and drains of the MOS transistors are arranged so that they are not aligned in a straight line, the programming gate 19 is connected to the control gate 11 and the select gate 1.
It can be provided so as to be orthogonal to 6.
As a result, a memory device having memory cells with high integration density and large GM can be realized.

FIG. 3 is a pattern plan view showing an actual memory array configuration using a plurality of cells having a pattern as shown in FIG. 1 above. In FIG. 3, each cell is divided into control gates 11 for each byte, and each control gate 11 is a transfer gate, for example, a depletion type MOS transistor 3.
1 to the program line 32. Further, the gate of each MOS transistor 31 is connected to the selection gate 16 of the corresponding byte, and the source 1 of the cells arranged vertically in the figure is connected to the selection gate 16 of the corresponding byte.
4 and drains 15 are commonly connected by source wiring 33 and drain wiring 34, respectively.

In such a configuration, all the source wirings 33 and drain wirings 34 are set to the same potential, and the program line 32 is set to a high potential during data erasing and programming. Now, in FIG. 3, cells 41, 42, and 43 are selected for erasing or programming, and cells 44, 45, and 46 are left unselected. When erasing, selected selection gate 1
1 is set to a high potential and the non-selection gate 11 is set to a low potential, the corresponding control gate 11 is set to a high potential via the MOS transistor 31 whose gate is connected to the selection gate 11.
Since the programming gate 19 is brought to a low potential as described above, the control gate 11, source 14, common area 13, and programming gate 19 of cells 44, 45, and 46 are all brought to a low potential, and the inside of the floating gate 12 is brought to a low potential. Electrons are not affected by anything.

On the other hand, in cells 41, 42, and 43, a potential difference occurs between the control gate 11 and the common region 13, and electrons are injected into the floating gate 12 of this byte. In addition, regarding the byte of the same selection gate adjacent to the right side in the figure, since the program line 32 (not shown) is set to a low potential, the potential of the control gate 11 is set to a low potential, and therefore, the potential inside the floating gate 12 is set to a low potential. has no effect on electrons.

Next, the case of programming data into this memory cell will be explained. For example, assume that only 42 cells are to be programmed. At this time, the unselected selection gates 16 located on the lower side of the figure are set to a high potential, the selected selection gates 16 located on the upper side of the figure are set to a low potential, and the sources and drains of all cells are set to a high potential. set to potential. For programming gate 19, cells 41, which are not programmed,
43 is set to a low potential, and the cell 42 to be written is set to a high potential. At this time, since the unselected control gates 11 are at a high potential, the gates 44, 45, 46
The floating gate 12 of is raised to a high potential. cell 45
Since no potential difference is generated between the floating gate 12 and the programming gate 19, the electron storage state of the floating gate 12 is maintained as it is.
For cells 44 and 46, floating gate 12
An electric field is generated between the programming gate 19 and the programming gate 19 as described above.
Since the emission of electrons from the lower side to the floating gate 12 is unlikely to occur, the electron accumulation state of the floating gate 12 is similarly maintained as it is.

On the other hand, since the selected selection gate 16 is set to a low potential, the MOS transistor 31 connected thereto is turned off, the corresponding control gate 11 is also set to a low potential, and the programming gate 19 is set to a low potential.
An electric field is applied between the floating gate 12 and the programming gate 19 in a direction where electron emission is likely to occur only in the cell 42 where the voltage is set to a high potential. Note that for the non-selected byte adjacent to the right in the figure, the control gate 11 is at a low potential, but the programming gate 19 is also at a low potential, so the electron accumulation state of the floating gate 12 is maintained as is. Note that the bias states of cells 41, 42, and 43 are normal.
It is the same as in the EEPROM program mode, but the electrons passing through the tunnel part are the emission of electrons from the asperity (3 to 4 MV/cm).
The emission is much less likely to occur (10 MV/cm) than that of 1, and can be ignored if the programming potential is chosen appropriately.

FIG. 4 is a pattern plan view of a memory cell according to another embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view taken along line -B'. In the cell of this embodiment, a portion 18 of the thin insulating film between the common region 13 and the floating gate 12 is connected to the common region 13 and the source 14.
The insulating film portion 18 is placed on the side of the transistor portion formed between the insulating film portion 18 and the transistor portion. With such a configuration, it is possible to further increase the integration density. In the case of this cell, electrons are injected into the insulating film 22 for erasing.
Electrons for programming are emitted from the insulating film 20. Conventional. The disadvantage of this cell is that breakdown and leakage current occur due to electric field concentration in the insulating film 20 during programming, but if this invention is adopted, a tunnel current can be generated in the insulating film 20 with a relatively low electric field. Therefore, problems like the conventional ones can be avoided.

FIG. 6 is a pattern plan view showing the structure of a cell according to still another embodiment of the present invention. Said first
In both the embodiments shown in FIG. 4 and FIG.
It can also be realized using a two-layer polycrystalline silicon process as shown in the figure. That is, in FIG. 6, the floating gate 12 and the selection gate 16 are each made of the first polycrystalline silicon layer,
The control gate 11 is made of a second polycrystalline silicon layer, and the programming gate 19 is made of a metal such as aluminum.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a semiconductor memory device with a high integration density of memory cells and a high conductance of transistors.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a pattern of a memory cell of a semiconductor memory device according to the present invention, FIG. 2 is a cross-sectional view of the memory cell of FIG. 1, and FIG. 3 is a case where a plurality of memory cells of the above embodiment are integrated. FIG. 4 is a pattern plan view of a memory cell of a semiconductor memory device according to another embodiment of the present invention, and FIG.
6 is a pattern plan view of a memory cell according to still another embodiment of the present invention, FIG. 7 is a circuit diagram showing the basic configuration of an EEPROM memory cell, and FIG. FIG. 7 is a pattern plan view showing the conventional element structure of the cell, and FIG. 9 is a diagram summarizing the bias relationship and logic when programming or erasing data in the cell shown in FIG. 5. 11...Control gate, 12...Floating gate, 1
3... common area, 14... source, 15... drain, 16... selection gate, 19... programming gate.

Claims (1)

[Claims] 1. MOS transistor for data storage and selection
MOS transistors are connected in series to form a memory cell, the source of the data storage MOS transistor is formed by a first diffusion region, and the drain of the data storage MOS transistor and the source of the selection MOS transistor are connected to the first diffusion region. A common second diffusion region is arranged adjacent to the diffusion region, and the drain of the selection MOS transistor is connected to the drain of the selection MOS transistor.
a third diffusion region disposed adjacent to the second diffusion region in a direction perpendicular to an extension line formed by the first diffusion region and the second diffusion region; A control gate of the data storage MOS transistor is provided in a direction parallel to the extension line formed by the diffusion region, a floating gate is provided on the control gate with an insulating film interposed therebetween, and a part of the floating gate is connected to the first diffusion region. and a third diffusion region, and another part of the floating gate is arranged on the second diffusion region with an insulating film interposed between the second diffusion region and the third diffusion region. A selection gate is provided between the diffusion region via an insulating film and extends in a direction perpendicular to an extension line formed by the second diffusion region and the third diffusion region, and the selection gate is arranged between the first diffusion region and the second diffusion region. A programming gate is provided between the diffusion region and the floating gate via an insulating film, and extends in a direction perpendicular to an extension line formed by the first diffusion region and the second diffusion region, and the selection gate A semiconductor memory device characterized in that a memory cell is selected using the control gate and the programming gate, and data in the memory cell is erased and programmed using a tunneling phenomenon of an insulating film.