JPH0556718B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vector quantizer that blocks a plurality of input signal sequences and quantizes the block in a multidimensional signal space. [Prior Art] FIG. 11 shows an example of the configuration of an encoder in a conventional vector quantizer. In the figure, 1 is a blocked input signal series, 2 is a normalization circuit that normalizes the same series 1 for each block, and 3 is a normalization constant. Further, 4 is a normalized signal sequence (input vector), and 57, 58, and 59 are the first stage, second stage, seventh stage, 60, 61, and 8, which respectively constitute the tree search vector quantizer. 9 is a vector quantization index that is determined step by step; 9 is a multiplexing encoding unit that multiplexes the determined vector quantization index 8 and the normalization constant 3 and sends it to the transmission path; 10
is the encoder output signal. FIG. 12 shows an example of the configuration of the second stage 58 of the tree search vector quantizer shown in FIG. 11 in slightly more detail. In the figure, 62 is an input vector register, 63 is a codebook that stores a set of output vectors for tree search (codebook) in the form of difference vectors corresponding to pairs of output vectors, and 64 is a difference read from the codebook 63. Output vector, 46 is multiplier, 47
44 is a circuit for determining the sign (positive or negative) of the result of accumulation by the multiplier 47, 44 is the determination result, and 64 is an index. A register 61 is a new stage index determined by adding the judgment result 44 to the index 60 determined up to the previous stage. FIG. 13 shows an example of the configuration of a decoder in a conventional vector quantizer. In the figure, 50 is a received signal, 51 is a separation decoding unit that separates an index and a normalization constant, and 8
is an index, 3 is a normalization constant, 66 is a code table memory that stores only vectors corresponding to the terminal nodes of the tree-like output vector, 54 is an output vector read out according to the index 8,
55 is a normalization restoration circuit, and 56 is a reproduction signal sequence. FIG. 14 is an explanatory diagram for explaining the operating principle of a conventional vector quantizer. Next, the operation will be explained using FIG. 11, FIG. 12, FIG. 13, and FIG. 14. First, the concept of tree search vector quantization will be explained. In vector quantization, a digitized signal sequence is divided into blocks and treated as vectors in a multidimensional signal space. In advance, a representative point having an optimal distribution with respect to the distribution density when the input signal is vectorized is set in the signal space. These representative points are output vectors, and a set of output vectors is called a codebook. The encoder of the vector quantizer searches for an output vector that best approximates the input vector and outputs its index. The decoder reads out the output vector corresponding to the index from the codebook and outputs it. The critical path in the above process is the search for the optimal output vector. The efficiency of vector quantization improves as the number of signal sequences integrated during blocking, that is, the dimension of the vector, increases. However, the number of output vectors required to maintain reproduction quality becomes extremely large, and the search time required to find the optimal output vector also increases. Originally, the output vector provides a division of the signal space. The representative point of each division is the output vector. If the signal space is divided step by step until the target division is finally reached, and representative points are defined at intermediate stages, those vectors will form a tree structure as shown in Figure 14. becomes. In this example, each stage will perform a two-part split. Top of the tree (vector y ₀ is the representative point of the entire signal space = center)
If the branch is traced from the branch to the representative point that gives a better approximation by comparing with the paired output vector at each stage, in the case of an n-stage tree, (n is a positive integer) 2n By calculating the distortion with the N=2n representative points, one of the N=2n representative points is arrived at. The above is the concept of tree search vector quantization.
Next, an explanation will be given along with an actual configuration example. It is assumed that the input signal sequence 1 is divided into k blocks. (k is a positive integer) That is, s = [s ₁ s ₂ , ..., s _k ] In the normalization circuit 2, in order to use the codebook for general purpose when performing the following vector quantization, the vector is Normalize. For example, normalization is performed as follows. σ=[ _K 〓 ^j=1 (s _j ) ² ] ^1/2 x _j = s _j/ 〓 ( x = "x ₁ , x ₂ , ..., x _k ") The normalized input vector x4 is First stage 57 and second stage 5 forming a tree search vector quantizer
8, . . . In the n-th stage 59, comparison with the output vectors forming a pair is performed step by step. The comparison result is 0
Alternatively, the binary number expressed as 1 and arranged from the first stage to a certain stage becomes an address for reading a pair of output vectors to be compared in the next stage. 6
0→61→...→8 Therefore, the index information 8 is what is arranged up to the last stage. A multiplexing encoding unit 9 multiplexes the index 8 and the normalization constant 3, encodes the same on a transmission path, and sends the code 10 to the transmission path.
do. At each stage, distortions between the input vector x and two output vectors are calculated and compared. Let the two output vectors be y _L = [y _L1 , y _L2 , ..., y _Lk ], y _R = [y _R1 ,
y _R2 , ..., y _Rk ], distortion d for each x ( x , y
_L ), d( x , yR ) as d( x , _yL ) = _K 〓 ^j=1 ( _{x j} −y _{Lj )} ² d( x , yR )= _K 〓 ^j=1 (x _j − y _Rj ) ² . The magnitude of the two distortions is the same as the positive or negative sign of the difference between them. d( x , y _L ) − d( x , y _R ) = _K 〓 ^j=1 (x _j −y _Lj ) ² − _K 〓 ^j=1 (x _j −y _Rj ) ² = _K 〓 ^j=1 [ (y _Lj ) ² −(y _Rj ) ² −2x _j (y _Lj −y _Rj )] =−2 _K 〓 ^j=1 [x _j (y _Lj −y _Rj )] However, x , y _L , y _R Both assume that it has been normalized as mentioned earlier. In this case, the distortion comparison is performed by calculating the inner product of the input vector x and the difference vector between the paired output vectors y _L and y _R and determining its sign. Therefore, it is only necessary to select the branch that gives smaller distortion based on the sign. FIG. 12 shows an example of the configuration of the second stage of the tree search vector quantizer under the above conditions.
The difference vector 64 of the output vectors to be compared is read out from the codebook 63 according to the history 60 of comparison results up to the previous stage. The codebook 63 stores pairs of output vectors in the form of their difference vectors. The difference vector 64
and the input vector 4 are multiplied by a multiplier 46, and added by an accumulation circuit 47 to obtain an inner product. The sign determining circuit 48 determines whether it is positive or negative, and the determination result 44 of the current stage is added to the result 60 of the previous stage stored in the index register 65, and the result is sent 61 to the next stage. After the input vector 4 is stored in the input vector register 62, it is sent to the next stage. The other stages have the same configuration, except that the first stage does not have the results up to the previous stage, and the final stage does not need to send the input vector 4 to the next stage. In the decoder, the received signal 50
is subjected to transmission path decoding in the separation decoding section 51, and an index 8 and a normalization constant 3 are output. The normalization restoration circuit 5 outputs the output vector 54 read from the codebook 66 according to the index 8.
Regenerate the gain at 5. In the case of the normalization described above, the normalization constant is multiplied by each element of the output vector. Through the above processing, the reproduced signal sequence 56 is obtained. [Problems to be Solved by the Invention] Since the conventional vector quantizer is configured as described above, it has had the following problems.
That is, since it is the output vector stored in the codebook that determines the encoding performance, the output vector is required to have high efficiency and versatility. For example, when dealing with image signals, in order to handle images with significantly different statistical properties, it is necessary to increase the number of output vectors by increasing the number of stages in the output vector tree. However, an increase in the number of output vectors did not directly lead to an improvement in the quality of encoded and decoded data, and the design of the codebook was a complex problem. This invention was made to solve the above-mentioned problems, and when the properties of the input signal are significantly changed, it is possible to create a tree of output vectors with a symmetric structure in a new efficient multidimensional signal space. To obtain a vector quantizer that realizes high-speed generation of a versatile set of output vectors and reduction of codebook memory capacity by providing a high-speed generation method and adding a circuit for implementing the same method. The purpose is to [Means for solving the problem] A vector quantizer according to the present invention divides a set of vectors, which is a training sequence, into two, and inserts one set into a partial signal space to which the other set belongs. At the same time as repeating the operation of symmetrically folding and then further dividing into two, at each stage of repetition, the representative points of the set of vectors divided into two are calculated, and the resulting pairs of representative point vectors are searched through a tree. It has an added function to expand it into a tree with a symmetric structure for vector quantization. [Operation] In this invention, in order to obtain a tree search code table suitable for the signal to be vector quantized, a part of the input vector is used as a training sequence, and the signal space is divided into two parts in stages. A tree with a symmetrical structure is generated by folding the training sequence on one side of the space, and the code table obtained through the same procedure is transmitted together with index information obtained by vector quantizing the input vector using the same code table. do. [Embodiments of the Invention] The present invention will be explained below by giving examples. FIG. 1 shows an example of the configuration of an encoding section in a vector quantizer according to the present invention. In the figure, 1 is a block input signal series, 2 is a normalization circuit that normalizes the same series 1 for each block, 3 is a normalization constant, and 4 is a normalization circuit that normalizes the same series 1 for each block.
is a normalized signal sequence (input vector), 5 is a tree search vector quantizer, 6 is a code table update unit, 7 is a code table generated in the code table update unit, 8 is a vector quantization index, 9 1 is a multiplexing encoding unit that multiplexes the code table 7, the normalization constant 3, and the index 8 and encodes the same on a transmission path; 10 is an encoder output signal. FIG. 2 shows an example of the configuration of the code table updating section 6 in FIG. 1. In the figure, 11 is a vector memory that stores input vectors used as training sequences;
12 is a training sequence; 13 is a latch for storing temporary representative points for dividing the partial signal space to which the training sequence 12 belongs; and 14 is a subtracter for calculating the difference between the two vectors that are the temporary representative points. , 15 is a difference vector obtained by the subtracter 14, 16 is a multiplier for multiplying each element of the difference vector 15 and the training sequence 12, 1
7 is an accumulation circuit that adds up the products obtained by the multiplier 16 for each vector; 18 is the sum of the products of the difference vector 15 and the training sequence 12, that is, the original inner product; 19 is the sign of the inner product 18; 20 is a folding circuit that folds the training sequence 12 into a vector that is symmetrical with respect to a given vector; 21 is a training sequence folded back by the folding circuit 20; 22 is the training sequence that is folded back by the folding circuit 20; Sequence vector 12
and a vector 21 which is a folded version of the same vector, 23 is the training sequence 1.
2 is the union of one of the vectors obtained by dividing 2 into two and a vector obtained by folding the other vector to a symmetrical position in the two subspaces, 24 is the vector group 2
Vector group in the subspace opposite to 3, 25
26 is a representative point calculation circuit that calculates the representative points of the vector groups 23 and 24; 26 is the vector group 23 and 24;
27 is a latch for storing the representative points, and 7 is the two representative points stored in the latch 27. FIG. 3 is an explanatory diagram of symmetrically folding back a vector, and FIG. 4 is a configuration example of a folding circuit. In the figure, 28 is an input vector, 29 is a vector considered as the center of symmetry, 30 is a vector obtained by folding the vector 28 symmetrically about vector 29,
31 is a multiplier that multiplies each element of the vector 28 to be folded and the center vector 29; 32 is an accumulation circuit that adds the products obtained by the multiplier 31 for each vector; 33; is a multiplier that multiplies the inner product obtained by the accumulation circuit 32 by each element of the central vector 29, and 34 is a subtracter. Figures 5 and 6 are 2
An explanatory diagram for explaining the process of generating a code table in the code table update unit 6 whose configuration example is shown in FIG. 7. FIG. 7 shows an example configuration of the tree search vector quantizer in FIG. be. In the figure, 35 is a code table memory whose contents can be dynamically rewritten (the output vectors stored in this memory have a tree structure in which each stage has only one pair, as shown in Figure 5). ,36,3
7 and 38 are the first, second, and nth stages constituting a tree search vector quantizer, respectively; 39, 40, and 41 are input vectors that are adaptively folded back as they descend through the tree search stages; The output vector pair of the relevant stage is the output vector of the previous stage hanging on the tree, 43 is the difference vector between the output vector pair of the relevant stage, 44 is a 1-pit signal indicating the distortion comparison result at each stage, 45 is a register that combines the same signal 44 across all stages and maps it to the vector quantization index 8. FIG. 8 shows an example of the configuration of the second stage 37 of the tree search vector quantizer shown in FIG. 7 in slightly more detail. In the figure, 46 is a multiplier that multiplies the input vector 39 and each element of the difference vector 43, 47 is an accumulation circuit that adds up the products obtained by the multiplier 46 for each vector, and 48 is the accumulation circuit 47. A sign determination circuit 49 determines whether the inner product obtained by is positive or negative, and a folding circuit 49 folds the input vector to the output vector of the previous stage based on the determination result 44 of the same sign determination circuit 48. FIG. 10 shows an example of the configuration of a decoding section in a vector quantizer according to the present invention. In the figure, 5
0 is the received signal, 51 is the new code table 7, the index 8, and the normalization constant 3.
a separation decoding unit that separates and decodes the transmission path;
2 is a code table memory whose contents can be rewritten; 53 is a folding circuit for folding back the output vector to complete the code table; 54 is an output vector read out according to the index 8; 55 is a normalization restoration circuit. , 59 are reproduction signal sequences. Next, the operation will be explained. Basically, when signals with different properties are input and it is necessary to update the set of output vectors, a general-purpose tree search code table is generated using a group of input vectors as a training sequence, and this code table is used. This method attempts to cope with large changes in the input signal by vector quantizing the input signal and using the vector quantization information and the updated code table as the encoded output. In FIG. 1, it is assumed that the input signal sequence 1 is divided into k blocks. That is, s = [s ₁ , s _{2 ,} . For example, normalization is performed as follows. σ=[ _K 〓 ^j=1 (s _j ) ² ] ^1/2 x _j = s _j/ 〓 ( x = [x ₁ , x ₂ , ..., x _k ]) Normalized input vector x 4 A tree search code table 7 is generated in the code table update unit 6 using the set. Using the same code table 7, the input vector 4 is vector quantized by the tree search vector quantizer 5. The vector quantization index 8 obtained by the quantization, the code table 7, and the normalization constant 3 are multiplexed in a multiplexing encoder 9, encoded on a transmission path, and sent out 10 to the transmission path. The code table update unit 6 stores the normalized input vector 4 in the vector memory 11 in order to use it as a training sequence for generating a new code table. Vector 1 of the training series read from the same memory 11
Take in two pieces of 2 and latch 13. This vector pair becomes an initial representative point for dividing the signal space into two. In the initial state, the vector group 12 read out from the memory 11 is distributed over the entire signal space. First, in order to divide the vector group 12 into two according to the initial representative point, the distortion between the vector 12 and the two representative points is calculated and compared. The two representative point vectors are y _L = [y _L1 , y _L2 , ..., y _Lk ], y _R =
[y _R1 , y _R2 , ..., y _Rk ], the distortion d (x, y _L ), d (x, y _R ) for the vector x of the training sequence is expressed as d ( x , y _L ) = _K 〓 ^{j= 1} (x _j −y _Lj ) ² d( x , y _R )= _K 〓 ^j=1 (x _j −y _Rj ) ² . The magnitude of the two distortions is the same as the positive or negative sign of the difference between them. From the assumption of normalization, d( x , y _L ) − d( x , y _R ) = −2 _K 〓 ^j=1 [x _j (y _Lj − y _Rj )] is derived, and distortion comparison is performed using two representative points. This is attributed to finding the inner product of the vector difference vector and the vector of the training sequence and determining its sign.
Therefore, the subtracter 14 obtains a difference vector 15 between the representative point vectors, and the multiplier 16 and the accumulator 17
Calculate the inner product 18 by . Further, a sign determining circuit 19 determines whether the inner product 18 is positive or negative.
In the meantime, the vector x12 of the training sequence is folded symmetrically about the center vector in the folding circuit 20, resulting in a vector x ^s = [x ^s ₁ . x ^s ₂ ,...,
Obtain x ^s _k ]21. The center vector is initially the vector that is the center of the entire signal space. The operation of symmetrically folding is expressed as x ^s = ( c − x) + c = 2 c − x when the central vector is c = [c ₁ , c ₂ , ..., c _k ] be able to. However, the vector x ^s obtained as described above does not preserve the normalized property of the vector x 12. Therefore, in order to fold back the vectors x, c, and ^xs so that they are all in a normalized state, or in other words, so that they are in the same signal space, the procedure shown in FIG. 3 can be used. Here x is the vector to be folded 28, c
is considered to be the central vector 29, ^and xs is considered to be the folded vector 30. From the normalization conditions mentioned earlier, it must be _K 〓 ^j=1 (x _j ) ² = _K 〓 ^j=1 (c _j ) ² = _K 〓 ^j=1 (x ^s _j ) ² = 1, so All three vectors are on the same hypercircle. Therefore, x ^s is obtained as x ^s = [( c , x ) c − x ] + ( c , x ) c = 2 ( c , x ) c − x . However, ( c , x ) is the vector c and x
is the inner product of FIG. 4 shows an example of the configuration of the folding circuit. Vector 28 to fold and center vector 2
9, the inner product is calculated using the multiplier 31 and the accumulation circuit 32, the inner product is doubled by the multiplier 33 and multiplied by the center vector 29, and the subtracter 3
Subtract the element of vector 28 to be folded by 4,
We obtain a symmetrical vector 30. In FIG. 2, a switching circuit 22 inputs the training sequence vector 12 through a folding circuit 21, and switches it into two outputs 23 and 24 according to the determination result of the sign determination circuit 19. For example, vector group 23 is {x|sign determination result is positive}∪{x ^s | sign determination result is negative}, whereas vector group 24 is {x|sign determination result is negative}∪{x ^s | sign determination result is correct}. Two new representative points 26 are extracted from each vector group by the representative point calculation circuit 25.
seek. The representative point can be found by the arithmetic mean of a group of vectors, but since the arithmetic mean does not preserve the normal addition condition, it is necessary to renormalize after finding the mean.
The new representative point 26 is taken into the latch 13. With the above, the class ring for code table generation is 1.
This means the loop has ended. By repeating the same loop, the two representative points 26 will optimally divide the signal space into two. The number of loops may be determined in advance. During the final loop, the vector group 23 is written into the vector memory 11. This operation corresponds to dividing the entire training sequence into two and folding back to one half, which means that the signal space is halved. This is one of the tree-like stepwise divisions.
It is a stage. Latch 27 the representative point 26 at this time.
and outputs it as output vector pair 7. At the same time, the representative point of the vector group 23 on the side where the vector memory 11 has been replaced is transferred to the loop circuit 20.
This is because the vector group 23 given as the central vector defines the signal space of the next stage. With the operations up to this point, one output vector pair has been obtained. By performing this operation n times, n stages of output vector pairs are obtained. These pairs have a fifth
There is a relationship as shown in the figure. Each node in the tree of FIG. 5 is a representative point inside the signal space. Each pair is symmetrical about the representative point (vector) from which it hangs. Furthermore, the partial signal space defined by each representative point has a complete inclusive relationship above and below the tree shown in FIG. That is, if the partial signal space centered at y _b (b is a binary number) is R _b , then R _b = R _b0 ∪R _b1 From the tree-like output vector shown in Fig. 5, the 14th
A complete binary tree-like output vector as shown in the figure can be developed. This will be explained using FIG. Assume that the rectangle shown in FIG. 6a is the entire signal space. The representative point is y ₀ . First, the first step of dividing into two is shown in FIG. 6b. two representative points
y ₀₀ and y ₀₁ are symmetrical about the representative point y ₀ in the previous stage.
Upon completion of the division, the training sequence is symmetrically folded back into the partial signal space defined by one representative point. That is, the next stage of division is performed using the partial signal space surrounded by the thick line as a new signal space. 6th
In diagram c, a new pair of output vectors y ₀₀₀ and y ₀₀₁ is obtained, and the signal space is further halved. As shown in the figure, y ₀₁₀ and y ₀₁₁ are obtained by symmetric folding around the already determined y ₀ , y _{01 ,} etc. The situation is the same in FIG. 6d, which is a more advanced stage. By folding back, the output vector of the next stage can be generated.
It is clear that a complete binary tree-like output vector can be obtained by repeating the same procedure. Using the above method, the symmetry can be expanded into a complete binary tree by folding just by generating a small portion of the tree. The resulting tree is completely symmetric, creating a general-purpose tree search code table that is unaffected by the bias of the training sequence. Of course, it is also possible to write the completed code table into a dynamically rewritable code table memory and use it like a conventional tree search vector quantizer. In this embodiment, a method of performing tree search vector quantization using only the output vector pair shown in FIG. 5 by folding the input vector symmetrically will be explained using FIG. 9. Assume that the rectangle shown in FIG. 9a is a signal space. Now, assume that the input vector x is to be vector quantized. In FIG. 9b, if x is quantized toward y ₀₁ as a result of the first stage distortion comparison, the first stage first outputs "1". Furthermore, as shown in FIG. 5, what is divided into the next stage is the partial signal space to which the output vector y ₀₀ in the actually prepared direction belongs, so the output information of the previous stage is "1".
Fold x symmetrically about y ₀ based on , and obtain x ₁ . Furthermore, in FIG. 9c, it is assumed that the signal is quantized to y ₀₀₁ . At this time, x ₁ is folded symmetrically about y ₀₀ to obtain x ₂ and at the same time "1" is output. In Figure 9d, x ₂ is quantized to y ₀₀₀₀ , so
There is no need to fold back x ₂ , and it can be considered that x ₃ = x ₂ , and "0" is output. We will continue the above operations, but looking at the results so far,
“110” is output. If we consider that all vectors start from y ₀ , it is "0110". Actual x is in the space to which y ₀₁₀₀ belongs in the partial signal space. “0100” and the index “0100” of y ₀₁₀₀ have a one-to-one correspondence, but are not the same.
This is because each time the input vector is folded once, the direction of quantization in the next stage is reversed. Therefore, the correspondence from "0110" to "0100" can be obtained by the mapping shown in FIG. 9e. In this way, the same quantization index as when using a complete binary tree can be obtained by always folding the input vector back to the side having the representative point of the next stage. In the configuration examples shown in FIGS. 7 and 8, the code table memory 35 stores output vectors corresponding to the tree shown in FIG. The first stage 36 and the second stage 3 constitute a tree search vector quantizer.
7. Since the n-th stage 38 corresponds to a distortion comparison circuit for dividing into two in the code table update unit 6,
The representative point vector 42 of the next stage and the difference vector 43 of the representative point of the current stage are input, and the multiplier 46 calculates the inner product of the vectors 39, 40, 41, etc. folded appropriately at each stage and the difference vector 43. , accumulation circuit 47
Find it using The sign determination circuit 48 determines the sign of the inner product, and according to the determination result 44,
The input vector folding circuit 49 controls whether or not to fold back the input vector, and sends the folded (or not folded) input vector to the next stage. The index register 45 integrates the sign determination results 44 in all stages and outputs the result as shown in FIG.
Perform the mapping shown in Quantization index 8
Output. In the decoder, a received signal 50 is subjected to transmission line decoding in a separation decoding section 51, and an output vector pair 7, a quantization index 8, and a normalization constant 3 are output. Output vectors corresponding to all terminal nodes are obtained from the vector pair 7 by the output vector folding circuit 53 and written into the output vector code table memory 52. The configuration of the folding circuit 53 may be as shown in FIG. 4. According to the index 8, the code table memory 5
A normalization restoration circuit 55 reproduces the gain for the output vector 54 read from the output vector 2. In the normalization described above, the normalization constant is multiplied by each element of the output vector. Through the above processing, the reproduced signal sequence 56 is obtained. The code table can be updated in various ways, such as periodically, or in advance every time a still image is encoded and transmitted according to a manual switch. In the above embodiment, the normalization constant is defined as the square root of the sum of squares, and the distortion distance between vectors is defined as the square distance, but other definitions may be used.
However, in that case, the distortion cannot be compared by simply calculating the inner product with the difference between the output vectors, so it is necessary to calculate the distortion between each of the two output vectors and the input vector and compare the distortions. Although the operation for performing symmetric folding changes depending on the normalization method, it is preferable to renormalize using the square root of the sum of squares, fold back, and then renormalize using the actually adopted normalization method. In practice, appropriate approximation calculations may be introduced. In the example above, a symmetric complete binary tree has one stage in each stage.
Although it has been shown that the vectors can be reduced to one pair of output vectors, it is also possible to further reduce the number of output vectors to one output vector for each stage. This is because, as is clear from FIGS. 5 and 6, the representative point y ₀ ... ₀₁ is obtained by folding y ₀ ... ₀ to y ₀ ... ₀ (m is an integer). This can also be used to reduce the number of output vectors to be transmitted. Furthermore, instead of picking up the input signal and using it as a training sequence, it is also effective to perform the tree generation described above using a mathematical random number model and generate a completely free code table from the signal characteristics. [Effects of the Invention] As described above, according to the present invention, a tree search code table can be generated in a short time even if signals with widely different properties are input, and the generated tree is completely symmetrical. , it is a general-purpose one that is not affected by the bias of the training sequence, so
Efficient tree search vector quantization can be performed on various signals, and the capacity of code table memory can also be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of the encoding section of a vector quantizer according to the present invention, FIG. 2 is a block diagram showing an example of the configuration of the code table updating section in the encoding section, and FIG. An explanatory diagram for explaining the operation of the loopback circuit in the table update section, FIG. 4 is a block diagram showing a configuration example of the loopback circuit, and FIG. 5 is an explanatory diagram for explaining the tree generated in the code table update section. FIG. 6 is an explanatory diagram for explaining the process of tree generation in the code table updating section; FIG. 7 is a block diagram showing an example of the configuration of a tree search vector quantizer in the encoding section; Figure 8 is a block diagram showing a configuration example of one stage of the same tree search vector quantizer having a stepwise structure;
10 is an explanatory diagram for explaining the process of vector quantization in the tree search vector quantizer; FIG. 10 is a block diagram showing an example of the configuration of the decoding section of the vector quantizer according to the present invention; Fig. 11 is a block diagram showing an example of the configuration of the encoding section of a conventional vector quantizer, and Fig. 12 shows an example of the configuration of one stage of the tree search vector quantizer in the encoding section of the conventional vector quantizer. Block diagram, 1st
FIG. 3 is a block diagram showing an example of the configuration of a decoding section of a conventional vector quantizer, and FIG. 14 is an explanatory diagram for explaining tree search vector quantization in the conventional vector quantizer. In the figure, 1 is a blocked input signal sequence, 2
is a normalization circuit, 3 is a normalization constant, 4 is a normalized input vector, 5 is a tree search vector quantizer, 6
is a code table update unit, 7 is a set of output vectors, 8 is a vector quantization index, 9 is a multiplexing coding unit, 10 is an encoder output signal, 11 is a vector memory, 12 is an input vector as a training sequence, 13 is a representative point latch, 14 is a subtracter, 15 is a difference vector of representative points, 16 is a multiplier, 17 is an accumulation circuit, 18 is an inner product, 19 is a sign determination circuit, 20 is a folding circuit, and 21 is a folding circuit. 22 is a switching circuit, 23 is a vector folded into one of the partial signal spaces divided into two, 24 is a vector folded in the opposite direction to 23, 25 is a representative point calculation circuit, 2
6 is a pair of updated representative points, 27 is a latch of representative points, 28 is a vector to be folded, 29 is a vector serving as the center of symmetry, 30 is a folded vector, 31 is a multiplier, and 32 is an accumulation circuit, 33 is a multiplier, 34 is a subtracter, 35 is a code table, 36
is the first stage of the tree search vector quantizer, 37 is the second stage of the tree search vector quantizer, 38 is the nth stage of the tree search vector quantizer, and 39 is folded or not folded in the first stage. Input vector, 40 is an input vector that is folded or not folded in the second stage, 41 is an input vector that is folded or not folded in the n-1th stage,
42 is a representative point vector of the previous stage, 43 is a difference vector between a pair of representative points of the current stage, 44 is a distortion comparison result at each stage, 45 is an index register, 46 is a multiplier, 47 is an accumulation circuit, and 48 is a code Judgment circuit, 49
is an input vector folding circuit, 50 is a received signal, 5
1 is a separation decoding unit, 52 is an output vector code table, 53 is an output vector folding circuit, 54 is an output vector, 55 is a normalization restoration circuit, 56 is a reproduced signal sequence, and 57 is a first tree search vector quantizer.
stage, 58 is a tree search vector quantizer second stage, 59
is the nth stage of the tree search vector quantizer, 60 is the distortion comparison result of the first stage, 61 is the distortion comparison result up to the second stage,
62 is an input vector register, 63 is a differential output vector code table memory, 64 is a differential output vector, 65 is an index register, and 66 is an output vector code table memory. In addition,
Identical or corresponding parts in the figures are indicated by the same reference numerals.

Claims (1)

[Claims] 1. A normalization circuit that normalizes a blocked input signal sequence using an amplitude component and outputs the result as an input vector and a normalization constant, and stores a certain amount of the input vector as a training vector. A vector memory that can be used as a vector memory, and a group of training vectors stored in the vector memory according to the norm of which of two initially set symmetrical output vectors is closer in the signal space. A vector quantization unit that divides the training vector into two sets, and an operation that calculates a new pair of output vectors by finding representative points for each of the two sets of training vectors divided by the vector quantization unit. a representative point calculation section that repeatedly obtains an optimal pair of output vectors until the sum of distortions between the two vectors is minimized; a training vector folding unit that updates the content of the training vector by folding the set of training vectors around a representative point of the set and then writing the set of training vectors to the vector memory together with the set of training vectors divided on the opposite side; and from a set of output vector pairs corresponding to a binary tree obtained by repeatedly operating the vector quantization section, the representative point calculation section, and the training vector folding section, a complete binary system corresponding to the hierarchical division of the signal space. An output vector folding unit performs symmetric folding to generate a set of tree-shaped output vectors, and a tree search vector quantization process is performed on the complete binary tree-shaped set of output vectors obtained by the output vector folding unit. an encoding code table memory into which one of the sets of output vectors can be written as a code table for vector quantization of the input vector; The operation of determining the pair of output vectors to be read next based on the results of comparison according to the norm of which vector is closer to the input vector in the signal space is performed according to the stage of the tree structure. a tree search vector quantization unit that repeatedly obtains one vector quantization index from the comparison results of each stage; a set of output vectors corresponding to the normalization constant and the terminal node of the complete binary tree; a multiplexing encoding unit that multiplexes the quantization index and performs transmission line encoding; and separating the normalization constant, the complete binary tree-like output vector set, and the vector quantization index from the multiplexed signal. a separate decoding unit that performs transmission path decoding, a decoding code table memory into which a set of output vectors corresponding to the terminal nodes of the complete binary tree can be written, and a decoding code table memory that A vector quantizer comprising: a normalization and restoration circuit for restoring the amplitude of an output vector read out according to the vector quantization index using the normalization constant to obtain a reproduced signal sequence. 2 Using a certain set of training vectors, 2
A code table memory that permanently stores a symmetric complete binary tree code table obtained by performing operations to form a set of output vectors having a symmetrical tree-like structure in advance on a computer of another system. The transmitter side encoder is equipped with a code table memory that fixedly stores only the output vector corresponding to the terminal node of the binary tree, and the receiver side decoder is equipped with a code table memory to transmit only the vector quantization index and normalization constant. A vector quantizer according to claim 1, characterized in that: 3. When one symmetric output vector pair is generated for each stage, the set of output vector pairs is written into the encoding code table memory, and in the process of performing tree search vector quantization, each stage It is determined whether the output vector pair giving the division is quantized to the side of the prepared output vector, and if it is quantized to the opposite side, the input vector is centered around the output vector quantized in the previous stage. is symmetrically folded along the tree, and one vector quantum is uniquely created based on the information on whether folding has been performed across all stages and the information on which output vector has been quantized. The receiving decoder includes a tree search vector quantization unit that determines a vector quantization index, transmits the set of output vector pairs, the vector quantization index, and a normalization constant, and a reception decoding unit calculates an output corresponding to a terminal node from the set of output vector pairs. 2. The vector quantizer according to claim 1, wherein the vector is written into the decoding code table memory after the vector is formed by symmetric folding.