JPH0556659B2 - - Google Patents
Info
- Publication number
- JPH0556659B2 JPH0556659B2 JP60001071A JP107185A JPH0556659B2 JP H0556659 B2 JPH0556659 B2 JP H0556659B2 JP 60001071 A JP60001071 A JP 60001071A JP 107185 A JP107185 A JP 107185A JP H0556659 B2 JPH0556659 B2 JP H0556659B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- temperature
- voltage
- threshold voltage
- mosfet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000005669 field effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
- H01L27/0211—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique adapted for requirements of temperature
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、基板温度の変化に伴ない生ずる電界
効果トランジスタのしきい値電圧変動を緩和する
ものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention alleviates threshold voltage fluctuations of field effect transistors that occur with changes in substrate temperature.
従来の技術
本来、絶縁ゲート型（IG）電界効果トランジ
スタ（FET）のしきい値電圧は、第２図に示し
た様な温度依存性を有する。この温度依存性は、
ゲート絶縁膜厚、チヤンネル基板濃度等に依存す
るが、一般に、次式で表わすことができる（参考
文献：Sze 2nd edition Physics of
Semiconductor devices P451）。Prior Art Originally, the threshold voltage of an insulated gate (IG) field effect transistor (FET) has a temperature dependence as shown in FIG. This temperature dependence is
Although it depends on the gate insulating film thickness, channel substrate concentration, etc., it can generally be expressed by the following formula (Reference: Sze 2nd edition Physics of
Semiconductor devices P451).
dVT／dT＝dΨB／dT（２＋１／Ci√εsqNA／ΨB）……
(1)
ただし、dΨB／dT±１／Ｔ〔Eg（Ｔ＝Ｏ）／2q−｜
ΨB
（Ｔ）｜〕 ……（1a）
ここで、Ｔ：基板温度（Ｋ）
ΨB：半導体のフエルミ準位と真性フエルミ
準位との差
Ci：絶縁膜容量（Ｆ／cm2）
Εs：半導体の誘電率（Ｆ／cm）
ｑ：電子の電荷（Ｃ）
NA：半導体内の不純物濃度（ ／cm3）
Eg：禁制帯幅（eV）
たとえば、絶縁膜厚100nm、不純物濃度１×
1015／cmの酸化シリコンを絶縁膜とするｎ型シリ
コンMOSFETの場合、その温度依存性は約２ｍ
Ｖ／℃となる。 dV T /dT=dΨ B /dT (2+1/C i √ε s qN A /Ψ B )...
(1) However, dΨ B /dT±1/T[E g (T=O)/2q−|
Ψ B (T) |] ... (1a) Where, T: Substrate temperature (K) Ψ B : Difference between the Fermi level of the semiconductor and the intrinsic Fermi level C i : Insulating film capacitance (F/cm 2 ) E s : Dielectric constant of semiconductor (F/cm) q : Electron charge (C) N A : Impurity concentration in semiconductor (/cm 3 ) E g : Forbidden band width (eV) For example, insulating film thickness 100 nm, impurity Concentration 1×
In the case of an n-type silicon MOSFET whose insulating film is silicon oxide of 10 15 /cm, its temperature dependence is approximately 2 m.
V/°C.
従来、IGFETは、通常デジタル回路に用いら
れる事が多く、また微小電圧差の検出には、セン
スアンプ回路のように、まつたく同じ構造の隣接
しあつたトランジスタを対象に使用する事から、
この様な温度差を問題にする事は少なく、これを
緩和しようとする従来例も見当らない。 Conventionally, IGFETs are often used in digital circuits, and to detect minute voltage differences, they are used to detect adjacent transistors with the same structure, such as in sense amplifier circuits.
Such a temperature difference is rarely a problem, and there are no conventional examples that attempt to alleviate it.
一方、近年素子の物理寸法の縮小に伴ない、電
界が強まる事により生ずるホツト・キヤリア効
果、移動度の低下、キヤリア速度飽和等の諸問題
をさける為、電源電圧やしきい値電圧（VT）も
下げる必要性が生じて来た。しかし、(1)式からも
わかる様に、しきい値電圧の温度依存性は、電源
電圧の低下等と共に、単純に縮小する事はできな
い。このため、このVT温度依存性により、しき
い値電圧（VT）の下限が制限されてしまう。た
とえば、G.Baccarani，M.R.Wordeman，R.H.
Dennard等がアイイーイーイー トランスアクシ
ヨン オン エレクトロンデバイシズ，イーデー
−31巻、４号、452−462頁、1984年４月（IEEE
Transaction on Electron Devices，Vol.ED−
31，No.４，PP.452−462，Apr.1984）の“一般測
定理論及びその1/4マイクロメータ MOSFET
設計への応用（Genaralized Scaling Theory
and Its Application to ａ 1/4Micrometer
MOSFET Design）”の中で述べられている様
に、0.25μmレベルのMOSFETを実現しようとし
た時、使用温度範囲の上限を70℃と設定すると、
VTの下限は常温では250mVとなつてしまう。 On the other hand, as the physical dimensions of devices have decreased in recent years, the power supply voltage and threshold voltage (V T ) has also become necessary. However, as can be seen from equation (1), the temperature dependence of the threshold voltage cannot be simply reduced as the power supply voltage decreases. Therefore, this V T temperature dependence limits the lower limit of the threshold voltage (V T ). For example, G. Baccarani, MR Wordeman, RH
Dennard et al., IEEE Transaction on Electron Devices, Vol. 31, No. 4, pp. 452-462, April 1984 (IEEE
Transaction on Electron Devices, Vol.ED−
31, No. 4, PP. 452-462, Apr. 1984) “General measurement theory and its 1/4 micrometer MOSFET
Application to design (Generalized Scaling Theory)
and Its Application to a 1/4 Micrometer
MOSFET Design)”, when trying to realize a 0.25μm level MOSFET, if the upper limit of the operating temperature range is set at 70℃,
The lower limit of V T is 250mV at room temperature.
発明が解決しようとする問題点
以上、述べた様に、MOSFETのしきい値電圧
の温度依存性は、素子寸法や、電源電圧を縮小し
ても同様に縮小する事ができないため、VTの値
に対するVTの温度依存性の比が大きくなり、VT
の下限、ひいては、電源電圧の下限を決める要因
となる。Problems to be Solved by the Invention As stated above, the temperature dependence of the MOSFET threshold voltage cannot be reduced even if the element size or power supply voltage is reduced . The ratio of the temperature dependence of V T to the value increases, and V T
This is a factor that determines the lower limit of power supply voltage and, in turn, the lower limit of power supply voltage.
本発明は、かかる点を解決するためになされた
もので、１つの基板電位をコントロールする回路
を、半導体集積回路の内部に付加することだけ
で、基板上のすべての同一タイプ（ｎ型か、ある
いはｐ型）のIGFETの温度依存性を緩和するこ
とを目的としている。 The present invention was made to solve this problem, and by simply adding a circuit for controlling the substrate potential inside the semiconductor integrated circuit, all the same type (n type, The purpose is to alleviate the temperature dependence of p-type (or p-type) IGFETs.
問題点を解決するための手段
本発明は、上記問題点を解決するため、半導体
基板の電位を、基板温度に応じて変えてやる事に
より、閾値電圧の温度依存性を緩和するものであ
る。Means for Solving the Problems In order to solve the above problems, the present invention alleviates the temperature dependence of the threshold voltage by changing the potential of the semiconductor substrate depending on the substrate temperature.
作 用
本発明は、上記した構成により、基板電位を基
板温度に応じて、コントロールし、基板バイアス
効果を利用し、基板温度変化により生じたVT変
動を補正する。Effects The present invention, with the above-described configuration, controls the substrate potential according to the substrate temperature, utilizes the substrate bias effect, and corrects the V T fluctuation caused by the change in the substrate temperature.
実施例
第１図は、本発明を構成する基板電位設定回路
の一実施例である。第１図において、１は基板電
圧設定回路ブロツクを示し、２はそれにより、補
償を受けるIGFETを示している。本実施例では、
これらの回路をSi基板上に形成する。３はダイオ
ードを示し、PN接合から成るダイオードを順方
向に４段直列に用いる。４は抵抗であり、半導体
基板内の拡散層を用いて、約5KΩになるよう形
成する。端子５はグランド（oV）に接続し、端
子６は−3.8Vの負バイアスに接続して使用する。
端子７は、基板電圧の出力端子であり、ブロツク
２のFETに供給される。また端子７の電位は、
ダイオード３の順方向電圧（VD）が、0.2mA常
温で流した時0.7Vであることから、−3.8＋4VD＝
−1.0（Ｖ）である。一方、ブロツク２に示され
た、補償を受けるFETと、ゲート酸化膜厚
20nm、基板濃度３×1016／cm3のｎ型MOSFETで
あり、温度補償される前には、第３図ａに示した
様に、そのしきい値電圧は−30℃から＋70℃の使
用設定温度範囲において、dVT／dT−
1.8mV／℃程度の温度依存性を有する。基板電圧
設定回路１の基板電圧出力端子７の電位依存性
は、第３図ｂの実線で示した様になる。これは、
pn接合ダイオードの順方向電圧（VD）の温度依
存性が１つ当たりΔVD／ΔT＝−1.8mV／℃であ
るためで、これを直列に４段接続した回路３では
温度依存性は４倍の−7.2mV／℃となる。従つて
−30℃から70℃の間ではしきい値電圧は−0.64V
から−1.36Vまで変化させる事ができる。この基
板電圧の変化は、FET2のしきい値電圧を基板バ
イアス効果により第３図ｂの破線で示したように
変化させる。この基板電圧によつて受けるFET2
のしきい値電圧の変化は、同じFET2が温度変化
によつて受けたしきい値電圧の変化とちようど打
ち消し合う方向に働く。したがつて、この温度補
償を受けたMOSFETのVTの温度依存性は第３図
ｃの様になり、−30℃から70℃の間で、変動幅は、
20mVと、補償を受けないMOSFETの変動幅
180mVに比べ1/9と軽減されることがわかる。Embodiment FIG. 1 shows an embodiment of a substrate potential setting circuit constituting the present invention. In FIG. 1, 1 indicates a substrate voltage setting circuit block, and 2 indicates an IGFET compensated thereby. In this example,
These circuits are formed on a Si substrate. Reference numeral 3 indicates a diode, and four stages of diodes consisting of a PN junction are used in series in the forward direction. 4 is a resistor, which is formed using a diffusion layer in the semiconductor substrate to have a resistance of approximately 5KΩ. Terminal 5 is connected to ground (oV), and terminal 6 is connected to -3.8V negative bias.
Terminal 7 is a substrate voltage output terminal and is supplied to the FET of block 2. Also, the potential of terminal 7 is
Since the forward voltage (V D ) of diode 3 is 0.7 V when 0.2 mA is applied at room temperature, -3.8 + 4 V D =
-1.0 (V). On the other hand, the compensated FET shown in block 2 and the gate oxide film thickness
It is an n-type MOSFET with a thickness of 20 nm and a substrate concentration of 3 x 10 16 /cm 3. Before temperature compensation, its threshold voltage can be used between -30°C and +70°C, as shown in Figure 3a. Within the set temperature range, dV T /dT−
It has a temperature dependence of about 1.8mV/℃. The potential dependence of the substrate voltage output terminal 7 of the substrate voltage setting circuit 1 is as shown by the solid line in FIG. 3b. this is,
This is because the temperature dependence of the forward voltage (V D ) of a pn junction diode is ΔV D /ΔT = -1.8 mV/℃ per pn junction diode, and in circuit 3 in which four stages are connected in series, the temperature dependence is 4. This is twice as high as -7.2mV/℃. Therefore, the threshold voltage is -0.64V between -30℃ and 70℃.
It can be varied from -1.36V. This change in substrate voltage causes the threshold voltage of FET 2 to change as shown by the broken line in FIG. 3b due to the substrate bias effect. FET2 received by this substrate voltage
The change in threshold voltage of FET2 works in the direction of exactly canceling out the change in threshold voltage that the same FET2 receives due to temperature change. Therefore, the temperature dependence of V T of the MOSFET that has received this temperature compensation is as shown in Figure 3c, and the fluctuation range is between -30°C and 70°C.
20mV and uncompensated MOSFET fluctuation range
It can be seen that the voltage is reduced to 1/9 compared to 180mV.
また、基板電位コントロールによるIGFETの
温度補償は、第４図ａに示した様に、サブスレツ
シユホール領域におけるVG−log IDカーブの傾き
が温度の上昇と共に、小さくなるのに対し、基板
電圧を下げる事により、第４図ｂに示す様に、傾
きを大きくするといつた効果もあり、温度上昇に
伴なう、傾きの低下のために生ずる、ソース・ド
レイン間のリーク電流の増大をおさえる。 In addition, as shown in Figure 4a, the temperature compensation of the IGFET by controlling the substrate potential is such that the slope of the V G -log I D curve in the subthreshold hole region decreases as the temperature rises, while the substrate voltage As shown in Figure 4b, lowering has the effect of increasing the slope, suppressing the increase in leakage current between the source and drain that occurs due to the decrease in slope as the temperature rises. .
発明の効果
以上、述べた様に、本発明によれば、半導体集
積回路内の同一基板内に、基板電圧をコントロー
ルする回路を設ける事により、きわめて、温度の
影響の受けにくい、集積回路が実現できる。Effects of the Invention As described above, according to the present invention, by providing a circuit for controlling substrate voltage within the same substrate in a semiconductor integrated circuit, an integrated circuit that is extremely unaffected by temperature can be realized. can.
第１図は本発明の一実施例を示した回路図、第
２図はMOSFETのしきい値電圧の温度依存性を
示した図、第３図ａは一実施例に用いた
MOSFETが、温度補償を受けない時のVTの温度
依存性を示す図、同図ｂは基板電圧設定回路の出
力電圧（VB）とそれにより補償を受けると想定
されるΔVTの補償分を示した図、同図ｃは実施例
において補償を受けたMOSFETの温度依存性を
示した図、第４図ａはMOSFETのサブスレツシ
ユホールド特性の傾きの温度依存性を示す図、同
図ｂは同じ傾きの基板バイアス依存性を示す図で
ある。
１……基板電圧設定回路ブロツク、２……
IGFETブロツク、３……ダイオード、４……抵
抗、７……基板電圧出力端子。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a diagram showing the temperature dependence of the threshold voltage of a MOSFET, and Fig. 3a is a circuit diagram showing an embodiment of the present invention.
A diagram showing the temperature dependence of V T when the MOSFET is not subjected to temperature compensation. Figure b shows the output voltage (V B ) of the substrate voltage setting circuit and the compensation amount of ΔV T that is assumed to be compensated by it. FIG. 4c is a diagram showing the temperature dependence of the MOSFET compensated in the example, FIG. 4a is a diagram showing the temperature dependence of the slope of the subthreshold characteristic of the MOSFET, and FIG. are diagrams showing substrate bias dependence of the same slope. 1...Substrate voltage setting circuit block, 2...
IGFET block, 3...Diode, 4...Resistor, 7...Substrate voltage output terminal.
Claims (1)
る電界効果トランジスタのしきい値電圧変動を補
償する様な基板電位を発生する基板電位設定回路
を同一基板上に設けた事を特徴とする半導体集積
回路。1. A semiconductor integrated circuit characterized in that a substrate potential setting circuit that detects substrate temperature and generates a substrate potential that compensates for threshold voltage fluctuations of a field effect transistor caused by the substrate temperature is provided on the same substrate. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60001071A JPS61160960A (en) | 1985-01-08 | 1985-01-08 | Semiconductor ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60001071A JPS61160960A (en) | 1985-01-08 | 1985-01-08 | Semiconductor ic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61160960A JPS61160960A (en) | 1986-07-21 |
| JPH0556659B2 true JPH0556659B2 (en) | 1993-08-20 |
Family
ID=11491285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60001071A Granted JPS61160960A (en) | 1985-01-08 | 1985-01-08 | Semiconductor ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61160960A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7129745B2 (en) * | 2004-05-19 | 2006-10-31 | Altera Corporation | Apparatus and methods for adjusting performance of integrated circuits |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5232278A (en) * | 1975-09-05 | 1977-03-11 | Matsushita Electronics Corp | Semiconductor device |
-
1985
- 1985-01-08 JP JP60001071A patent/JPS61160960A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5232278A (en) * | 1975-09-05 | 1977-03-11 | Matsushita Electronics Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61160960A (en) | 1986-07-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |