JPH0556288A - Horizontal deflecting device - Google Patents

Abstract

PURPOSE:To decrease the loss of an output transistor and a deflection coil even when a horizontal deflection frequency is high. CONSTITUTION:The output pulse of an oscillating circuit 3 is (1/2)-divided by a divider 7, the width of the pulse is adjusted by a width adjusting circuit 8, and a sawtooth deflection current at the frequency (1/2)-divided through a first driving circuit 4a and a first output circuit 5a to a first deflection coil 13a is made to flow. On the other hand, at the rear step of the divider 7, a delaying circuit 9, a second driving circuit 4b and a second output circuit 5b are provided, and the deflection current in which the current to flow at the first deflection coil 13a at a second deflection coil 13b and the phase are dislocated only by pi[rad] is made to flow.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal deflection device used for electromagnetic deflection in a display device such as a display monitor using a CRT, a high-definition display monitor or an auto scan monitor.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a circuit configuration of a conventional horizontal deflection apparatus described in, for example, page 168 of a color television textbook (upper) (NHK edition), in which 1 is a horizontal synchronizing signal. An input terminal (hereinafter referred to as an input terminal), 2 is an AFC (Auto Frequency Control) circuit,
Reference numeral 3 denotes a horizontal oscillation circuit (hereinafter referred to as an oscillation circuit) arranged in the latter stage of the AFC circuit 2, 4a denotes a horizontal drive circuit (hereinafter referred to as a drive circuit) arranged in the latter stage of the oscillation circuit 3, and 5a denotes A horizontal output circuit (hereinafter referred to as an output circuit) arranged in the latter stage of the drive circuit 4a, 6 is a CRT as a display device, and 13a is a horizontal deflection coil attached to the neck portion of the CRT 6 (hereinafter referred to as a deflection coil). ).

Next, the operation of the above configuration will be described.
The horizontal synchronizing signal input to the input terminal 1 is input to the AFC circuit 2. The AFC circuit 2 is composed of a comparison signal generation circuit, a phase detection circuit, and an integration circuit, detects a phase difference between an input synchronization signal and a comparison signal based on a collector pulse generated in an output circuit 5a described later, and performs AFC control. Output a signal. Then, the oscillation circuit 3 outputs a horizontal oscillation pulse whose oscillation frequency and phase are controlled by the input AFC control signal. The drive circuit 4a is composed of, for example, a drive transistor and a drive transformer, and amplifies the horizontal oscillation pulse output from the oscillation circuit 3 and supplies a base current sufficient to turn on and off the output transistor of the output circuit 5a. ..

The output circuit 5a and the deflection coil 13a apply the switching function of a transistor and are combined with a damper diode, a resonance capacitor or the like to form the deflection coil 13a.
This is a circuit that causes a sawtooth wave current to flow through. The saw-tooth wave current flows as in equations (1) and (2) during the scanning period and the blanking period, respectively. I _S (t) = (V _CC / L) · t (1) I _R (t) = (I _PP / 2) · cos (ω _O · t) (2) ω _O = (L · C) ^-1/2 where L is the inductance of the deflection coil, C is the capacitance of the resonance capacitor, V _CC is the output power supply voltage, and I _PP
Is the peak value of the deflection current. A flyback pulse is generated in the collector of the transistor during the retrace period of the sawtooth current. The flyback pulse is divided and fed back to the AFC circuit 2 to control the phase and frequency of the horizontal oscillation pulse output from the oscillation circuit 3.

The loss in the transistor of the output circuit is
As shown in FIG. 8, V _CE of the output transistor in the ON state
Due to the saturation voltage of the transistor, the accumulation loss of the transistor caused by the collector current continuing to flow due to the accumulation effect when the base current is decreasing, and the switching (cutoff) loss due to the collector current drop time of the transistor. In FIG. 8, I _B is the base current,
I _C indicates a collector current, and V _CP indicates a collector pulse (flyback pulse). In order to reduce these losses, the positive peak value I _B1 and the negative peak value I _B2 of the base current of the transistor must be optimized, but the above-mentioned respective losses are correlated with each other, and therefore, the respective losses are minimized at the same time. You cannot do it. Moreover, the storage loss and the switching loss tend to increase as the deflection frequency increases.

The loss in the deflection coil is proportional to the product of the resistance of the coil and the square of the current flowing through the coil. When the deflection frequency becomes high, the skin effect and the adjacency effect occur and the AC resistance of the coil becomes high, so that the loss of the deflection coil also increases.

[0007]

Since the conventional horizontal deflection apparatus is constructed as described above, the horizontal deflection frequency f _H becomes high in a display monitor having high definition and auto scan, and the transistors and the deflections are made. There is a problem in that the loss in the coil increases, the thermal runaway of the transistor, the heat generation of the deflection coil, and the like reduce the reliability of these elements.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a deflection device capable of reducing the loss of a transistor and a deflection coil even when the horizontal deflection frequency becomes high. And

[0009]

Means for Solving the Problems Claims 1 and 3
The horizontal deflection device according to the invention of (1)
n), adjust the width of the divided output pulse, and let the sawtooth wave flow through the n deflection coils by the n sets of drive circuits and the n sets of output circuits to display on the screen of the CRT. A horizontal deflection frequency is obtained so that the phase of the sawtooth wave is 2 · π · i / n (i = 1, 2, ..., N) [ra
d] is different from each other.

In the second and fourth aspects, flyback pulses for phase control are combined from n sets of output circuits through an adder and fed back to the AFC circuit.

[0011]

According to the present invention, the horizontal oscillation pulse of the frequency input to the input terminal is divided, the width is adjusted, and the above-mentioned input is applied to the n deflection coils via the n sets of drive circuits and the n sets of output circuits. By flowing a sawtooth wave having a frequency of (1/2) of the frequency, the output circuit is operated at a frequency lower than the input frequency and acts to reduce the loss of the output transistor and the deflection coil.

Further, by combining the flyback pulses generated in the n sets of output circuits and feeding them back to the AFC circuit, it is possible to perform control such that the frequency and phase of the output pulses of the oscillation circuit are kept constant.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a circuit configuration of a horizontal deflection apparatus according to an embodiment of the present invention. In FIG. 1, an input terminal 1, an AFC circuit 2, an oscillation circuit 3, a first drive circuit 4a, and a first drive circuit 4a are provided. Output circuit 5a, CRT 6, first
The deflection coil 13a is completely the same as that of the conventional device shown in FIG. 7, and the corresponding portions are designated by the same reference numerals and their description is omitted.

In FIG. 1, reference numeral 7 denotes a (1/2) frequency divider arranged at the subsequent stage of the oscillator circuit 3, and 8 denotes the (1/2) frequency divider 7 described above.
A width adjusting circuit arranged in a rear stage of the delay adjusting circuit 9, a delay circuit 9 arranged in a rear stage of the width adjusting circuit 8 in parallel with the first drive circuit 4a, and a second driving circuit 4b arranged in a rear stage of the delay circuit 9. Circuit, 5b is a second output circuit arranged in the latter stage of the second drive circuit 4b, 13b is a second deflection coil attached to the neck portion of the CRT 6, and 10 is the first output circuit 5a.
Is an adder for synthesizing collector pulses output from the second output circuit 5b and the synthesized pulse by AFC.
It is designed to feed back to the circuit 2. The first and second drive circuits 4a and 4b,
First and second output circuits 5a, 5b, first and second
The deflection coils 13a and 13b of the same have the same configuration.

Next, the operation of the above configuration will be described.
The horizontal sync signal of frequency f _H input to the input terminal 1 is A
The FC circuit 2 and the oscillation circuit 3 generate an oscillation pulse having a frequency f _H. This oscillation pulse is input to the (1/2) frequency divider 7. The (1/2) frequency divider 7 is composed of, for example, a counter, and divides the input pulse of the frequency f _H in half to generate a pulse of (f _H / 2).
The output of this (1/2) frequency divider 7 is (f _H /
Since the pulse duty ratio of the pulse 2) is 1: 1, the pulse width is adjusted by the width adjusting circuit 8 so as to correspond to the ON period of the output transistors of the first and second output circuits 5a and 5b. It Thus, the base current of the output transistors of the output circuits 5a and 5b can be optimized by adjusting the pulse width.

The (f _H / 2) pulse whose width has been adjusted by the width adjusting circuit 8 is then supplied to the first deflection coil 13 by the first drive circuit 4a and the first output circuit 5a.
A sawtooth wave current having a frequency (f _H / 2) is applied to a. on the other hand,
The (f _H / 2) pulse output from the width adjustment circuit 8 is
It is also input to the delay circuit 9. The delay circuit 9 delays the phase of the input (f _H / 2) pulse by shifting it by π [rad], and the delayed (f _H / 2) pulse output from the delay circuit 9 is the second pulse. Drive circuit 4b and second output circuit 5b of the second deflection coil 13
In (b), a sawtooth wave current having a phase difference of (f _H / 2) from the first deflection coil 13a is passed by π.

The magnitude of deflection of the electron beam in the CRT is the magnetic flux density B = k · μ generated by the current flowing in the deflection coil.
・ Proportional to the size of N ・ I. Here, k is a constant, μ is the magnetic permeability of the core, N is the number of turns of the deflection coil, and I is the magnitude of the current passed through the deflection coil. Now, assuming that μ and N of the deflection coils 13a and 13b attached to one CRT 6 are constant, the magnitude of deflection of the electron beam in the CRT 6 is proportional to the sum of the respective magnetic flux densities, and therefore the deflection coil is made to flow. Proportional to the sum of currents. FIG. 2 shows the waveform of the current flowing through the deflection coils 13a and 13b by the first and second output circuits 5a and 5b. In FIG. 2A, the solid line shows the waveform of the current flowing through the first deflection coil 13a,
The broken line shows the waveform of the current flowing through the second deflection coil 13b. Further, FIG. 2B shows the sum of the deflection currents, and as shown in FIG. 2B, by combining the sawtooth waves of (f _H / 2) whose phase is shifted by π, A sawtooth wave of f _H can be obtained. Therefore, CR
The electron beam on the screen at T6 is deflected at the frequency f _H.

Assuming that the scanning period and the blanking period of the deflection current of (f _H / 2) are T _S and T _R , respectively, as shown in FIG. 2, the scanning period and the blanking period due to the deflection of the frequency f _H of the electron beam. T1 _S and T1 _R are respectively T1 _S = (T _S −T _R ) / 2 T1 _R = T _R. When T1 _R is sufficiently small compared to T1 _S, deflection current width of the frequency f _H is approximately equal to the deflection current width I _PP frequency (f _H / 2).

The flyback pulses generated in the first and second output circuits 5a and 5b during the blanking period of the deflection current have a frequency of (f _H / 2), and their phases are shifted by π. There is. By combining these two flyback pulses with the adder 10, it is possible to obtain a Flanback pulse of frequency f _H , and by feeding this back to the AFC circuit 2, the frequency and phase of the output pulse of the oscillation circuit 3 are made constant. Can be controlled to keep on.

In the above embodiment, an example in which two deflection coils are used is shown, but the deflection coil, the drive circuit, and the output circuit may be more than that, and the same effect as the above embodiment can be obtained. However, when a deflection sawtooth wave current having an n-fold frequency is obtained using n deflection coils, the phase difference between the deflection currents is 2 · π · i / n (i = 1, 2,
..., n-1). As a second embodiment, FIG. 3 shows a block diagram of the circuit configuration of the deflecting device when n = 3. In the figure, input terminal 1, AFC circuit 2, oscillator circuit 3, first drive circuit 4a, second drive circuit 4b, first output circuit 5a, second output circuit 5b, CR
T6, width adjusting circuit 8, adder 10, first deflection coil 1
Since 3a and the second deflection coil 13b are exactly the same as those in the above-mentioned embodiment, the corresponding parts are designated by the same reference numerals and their description is omitted.

In FIG. 3, 11 is a (1/3) frequency divider arranged between the oscillation circuit 3 and the width adjusting circuit 8, and 12a is the (1/3 frequency divider 11) and the second drive. A first delay circuit arranged between the circuit 4b and a second delay circuit 12b arranged in parallel with the second drive circuit 4b at a subsequent stage of the first delay circuit 12a and a second delay circuit 4c. The third drive circuit 5c is arranged in the latter stage of the circuit 12b, 5c is the third output circuit arranged in the latter stage of the third drive circuit 4c, and 13c is C.
It is a third deflection coil attached to the neck of RT6. Here, the first to third drive circuits 4a, 4b and 4c, the first to third output circuits 5a, 5b and 5c, the first to third
The third deflection coils 13a, 13b, and 13c have the same configuration, and the delay amounts of the first and second delay circuits 11a and 11b are (2/3) of the cycle of the output of the frequency divider 11. The phase is set to be shifted by π [rad].

FIG. 4 shows the first to third deflection coils 13a, 13 in the horizontal deflection apparatus of the embodiment shown in FIG.
The waveforms of the deflection currents flowing in b and 13c are shown such that the blanking period can be ignored for simplicity. In FIG. 7A, the solid line, the broken line, and the alternate long and short dash line are the deflection coil 13
represents the deflection current flowing in a, 13b, 13c,
FIG. 4B shows a state of combined deflection of the electron beam in the CRT 6 by the deflection current of FIG.

FIG. 5 is a block diagram showing a circuit configuration of a horizontal deflection apparatus according to another embodiment of the present invention. In FIG. 5, an input terminal 1, an AFC circuit 2, an oscillation circuit 3, (1 /
2) Frequency divider 7, first drive circuit 4a, first output circuit 5a, second drive circuit 4b, second output circuit 5
b, the CRT 6, the first deflection coil 13a, the second deflection coil 13b and the adder 10 are exactly the same as those in the embodiment shown in FIG.
The description thereof will be omitted. 5 is different from the embodiment of FIG. 1 in that a first width adjusting circuit 8a is provided in the preceding stage of the first drive circuit 4a and a second drive circuit 4a is provided.
The second width adjusting circuit 8b is arranged at the stage before b
The delay circuit 9 is arranged between the width adjusting circuit 8b and the (1/2) frequency divider 7.

The operation of the embodiment shown in FIG. 5 is basically the same as that of the embodiment of FIG. 1, except that (1/2)
The pulse width of (f _H / 2) output from the frequency divider 7 is set to the first
The base current of the output transistor of the first output circuit 5a can be optimized by adjusting the width adjustment circuit 8a, and the output of the (1/2) frequency divider 7 is (f _H / 2) pulse is input to the delay circuit 9,
After delaying its phase by π [rad], the width of the delayed (f _H / 2) pulse is set to the second value.
The base current of the output transistor of the second output circuit 5b can be optimally adjusted by adjusting the width adjustment circuit 8b, and the same effect as that of the above-described embodiment can be obtained.

FIG. 6 is a block diagram showing a circuit configuration of a deflection device constituted by using the first to third three deflection coils 13a, 13b and 13c.
First and second delay circuits 12a and 12b, first to third width adjusting circuits 8a, 8b and 8c, and first to third drives are provided between the third output circuits 5a, 5b and 5c. It is configured by arranging the circuits 4a, 4b, 4c, and the operation in this case is basically the same as that of the embodiment shown in FIG. 3 and has the same effect as each of the above embodiments.

[0026]

As described above, according to the inventions of claims 1 and 3, since the output circuit can be operated at a frequency lower than the input frequency f _H , high definition and auto scan can be realized. Even when the horizontal deflection frequency f _H is high like the above-mentioned display monitor, the loss of the transistor and the deflection coil can be reduced, the thermal runaway of the transistor and the heat generation of the deflection coil can be prevented, and the reliability of each element is improved. There is an effect that can be done.

According to the second and fourth aspects, the flyback pulses for phase control are combined and fed back to the AFC circuit, so that the frequency and the phase of the output pulse are kept constant. Therefore, the loss of the deflection coil and the like can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a deflection device according to an embodiment of the present invention.

FIG. 2 is a current waveform diagram showing an operation of the deflecting device according to the embodiment.

FIG. 3 is a block diagram showing a circuit configuration of a deflection device according to another embodiment of the present invention.

FIG. 4 is a current waveform diagram showing an operation of the deflecting device according to the embodiment shown in FIG.

FIG. 5 is a block diagram showing a circuit configuration of a deflection device according to still another embodiment of the present invention.

FIG. 6 is a block diagram showing a circuit configuration of a deflection device according to another embodiment of the present invention.

FIG. 7 is a block diagram showing a circuit configuration of a conventional deflection device.

FIG. 8 is a diagram showing a loss of an output transistor in a horizontal deflection output circuit.

[Explanation of symbols]

 2 AFC circuit 3 Horizontal oscillation circuit 4a, 4b, 4c Horizontal drive circuit 5a, 5b, 5c Horizontal output circuit 6 CRT 7 (1/2) frequency divider 8, 8a, 8b, 8c Width adjustment circuit 9, 12a, 12b Delay Circuit 10 Adder 11 (1/3) Frequency divider 13a, 13b, 13c Deflection coil

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[Procedure amendment]

[Submission date] December 4, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 3

[Correction method] Change

[Correction content]

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

[0009]

The horizontal deflection device according to the inventions of claims 1 and 3 has a frequency of a horizontal oscillation pulse .
The number is divided into (1 / n), the width of the divided output pulse is adjusted, and a sawtooth wave is applied to the n deflection coils by the n sets of drive circuits and the n sets of output circuits. A horizontal deflection frequency is obtained on the screen of the CRT, and the phase of the sawtooth wave is set to 2 · π · i / n (i = 1, 2, ...,
n) [Rad] is different from each other.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

[0011]

SUMMARY OF] According to the present invention divides the frequency of the input to the input terminal horizontal oscillation pulse (1 / n), and width adjustment,
By passing a sawtooth wave having a frequency of (1 / n ) of the input frequency to the n deflection coils through the n sets of drive circuits and the n sets of output circuits, the output circuit operates at a frequency lower than the input frequency. It will be operated to serve to reduce losses in the output transistors and deflection coils.

Claims (4)

[Claims] 1. A horizontal deflection circuit comprising an AFC circuit, a horizontal oscillation circuit, a horizontal drive circuit and a horizontal output circuit, and C
A horizontal deflection device comprising a horizontal deflection coil attached to a neck portion of the RT, wherein the horizontal oscillation pulse of the frequency of the output of the horizontal oscillation circuit is divided by (1 / n), and A width adjusting circuit that adjusts the width of the output pulse of the frequency divider and the phase of the output pulse of this width adjusting circuit (n
-1) sets of delay circuits, (n-1) sets of delay circuits and n sets of horizontal drive circuits arranged in the latter stage of the width adjustment circuit, and n sets arranged in the latter stage of the horizontal drive circuits Of the horizontal output circuit and n horizontal deflection coils attached to the neck portion of the CRT. The n horizontal deflection coils have a phase of 2.pi.i / n [red] (i = 1,2). ，
The horizontal deflection device is characterized in that a predetermined horizontal deflection frequency is obtained on the screen of the CRT by causing a sawtooth wave having a 1 / n cycle different for each n. 2. An adder for synthesizing flyback pulses generated in the n sets of horizontal output circuits is provided, and phase control is performed by feeding back the output of the adder to the AFC circuit. The horizontal deflection device according to item 1. 3. A horizontal deflection circuit comprising an AFC circuit, a horizontal oscillation circuit, a horizontal drive circuit and a horizontal output circuit, and C
A horizontal deflection device comprising a horizontal deflection coil attached to a neck portion of the RT, wherein the horizontal oscillation pulse of the frequency of the output of the horizontal oscillation circuit is divided by (1 / n), and Adjust the phase of the output pulse of the frequency divider (n-
1) sets of delay circuits, (n-1) sets of delay circuits and n sets of width adjusting circuits for adjusting the width of the output pulse of the frequency divider, and n sets of width adjusting circuits are arranged in the subsequent stage. The horizontal drive circuits of n sets, the horizontal output circuits of n sets arranged at the subsequent stage of the horizontal drive circuits, and the n horizontal deflection coils attached to the neck portion of the CRT. The horizontal deflection coil has a phase of 2.pi.i / n [red] (i
= 1, 2, ..., N) different sawtooth waves having a 1 / n cycle, so that a predetermined horizontal deflection frequency is obtained on the screen of the CRT. 4. An adder for synthesizing flyback pulses generated in the n sets of horizontal output circuits is provided, and phase control is performed by feeding back the output of the adder to the AFC circuit. The horizontal deflecting device according to item 3.