JPH0795600A - Timing pulse generating circuit - Google Patents

Abstract

PURPOSE:To attain the correction not attended with the increase in a power loss when a phase lag of a signal processing process of a convergence circuit is corrected. CONSTITUTION:The circuit is provided with a horizontal oscillation circuit 1 outputting a horizontal pulse S1, a delay circuit 2 delaying the horizontal pulse S1 from the horizontal oscillation circuit 1 and a horizontal output transistor(TR) 4 comprising a MOS TR amplifying an output pulse from the delay circuit 2 and applying the amplified pulse to a horizontal deflection coil 5, the pulse S1 before a delay outputted from the horizontal oscillation circuit 1 is shaped by a waveform shaping circuit 6 to obtain a timing pulse S8 and it is used to generate various signal voltages for a horizontal period fed to convergence or screen distortion correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention corrects a phase delay during signal processing in a convergence circuit or a screen distortion correction circuit when generating various signal voltages for convergence correction or screen distortion correction in a projection type receiver. The present invention relates to a timing pulse generation circuit that generates a timing pulse for

[0002]

2. Description of the Related Art In a projection type image receiver, three images of three primary colors from red, green and blue projection tubes arranged at distant positions are enlarged and projected on a screen by using optical lenses.
In terms of constituting one color image, misconvergence occurs when the image distortions of the three images on the screen surface are different, so a convergence circuit is generally provided. The types of signal voltage required for this convergence correction include sawtooth wave voltage of horizontal and vertical periods, parabolic wave voltage, and modulated wave signal voltage obtained by modulating various signal voltages of horizontal period and various signal voltages of vertical period. Is. These signal voltages are generally produced by using a blanking pulse obtained by a horizontal deflection circuit and a vertical deflection circuit as a timing pulse. The sawtooth voltage is obtained, for example, by resetting the constant current integrator circuit by this timing pulse, and the parabolic wave voltage is obtained by integrating the sawtooth wave voltage or squaring with a multiplier circuit. Further, the modulated wave signal voltage can be obtained by multiplying the signal voltage of the vertical cycle and the signal voltage of the horizontal cycle by the multiplication circuit. After adjusting the required amount of the signal voltage obtained in this way, mixing and amplifying it, add it to the convergence yoke provided at the neck of the projection tube via the current feedback type amplification circuit (output circuit) to correct A current can be supplied and convergence correction can be performed.

FIG. 4 shows a conventional example of such a correction circuit. In this figure, the horizontal retrace pulse output from the horizontal deflection circuit 11 is sent to the horizontal sawtooth voltage generation circuit 12 to generate a sawtooth voltage. This horizontal sawtooth wave voltage is sent to the horizontal parabolic wave voltage generation circuit 13, the modulation wave signal voltage generation circuits 14 and 18, and the adjustment circuit 20. In the horizontal parabolic wave voltage generation circuit 13, a parabolic wave voltage is generated based on the input horizontal sawtooth wave voltage and sent to the modulation wave signal voltage generation circuit 19 and the adjustment circuit 20. On the other hand, the vertical retrace pulse output from the vertical deflection circuit 15 is sent to the vertical sawtooth voltage generation circuit 16 to generate a sawtooth voltage. This vertical sawtooth wave voltage is applied to the vertical parabolic wave voltage generation circuit 17 and the modulation wave signal voltage generation circuit 1.
4, 19 and the adjusting circuit 20. In the vertical parabolic wave voltage generation circuit 17, a parabolic wave voltage is generated from the input vertical sawtooth wave voltage, and the modulated wave signal voltage generation circuit 18 is generated.
Is sent to the adjusting circuit 20. Modulation wave signal voltage generation circuit 1
In 4, the horizontal sawtooth wave voltage and the vertical sawtooth wave voltage are multiplied to generate a modulated wave signal voltage, which is sent to the adjustment circuit 20. The modulation wave signal voltage generation circuit 19 multiplies the horizontal parabolic wave voltage and the vertical sawtooth wave voltage to generate a modulation wave signal voltage, which is sent to the adjustment circuit 20. In the modulation wave signal voltage generation circuit 18, the horizontal sawtooth wave voltage and the vertical parabolic wave voltage are multiplied to generate a modulation wave signal voltage, which is sent to the adjustment circuit 20. The adjustment circuit 20 adjusts the required amount of each signal voltage, mixes and amplifies it, and adds it to the convergence yokes (coils) 24, 25, 26 of the respective colors via the convergence circuits 21, 22, 23 of red, green, and blue, respectively. To be
Since the convergence correction of the projection type receiver is performed by adjusting the screen distortion of each projection tube, so-called screen distortion such as pincushion distortion and trapezoidal distortion can also be corrected, and the signal voltage waveform required for it can also be converged. It may be the same as the signal voltage waveform required for correction.

As described above, various signal voltages are produced through processing circuits such as an integrating circuit, an amplifying circuit, a modulating circuit, an adjusting circuit, and an output circuit. Therefore, it depends on the characteristics of the circuit configuration and the elements to be used. There is a phase lag in the signal voltage. Moreover,
Since the processing path differs depending on the type of signal voltage, the amount of phase shift also differs. This phase delay is not a problem for various signal voltages in the vertical cycle, but cannot be ignored when the signal voltage is in the horizontal cycle and the horizontal deflection frequency is particularly high. The signal voltage of the horizontal cycle is generated by using the horizontal retrace pulse as the timing pulse as described above. An example of the timing relationship of various signals at this time is shown in FIG. The signal timing shows the current waveform at the stage of being supplied to the convergence yoke. In the figure, A is a horizontal retrace pulse, B is a horizontal sawtooth current, C is a horizontal parabolic wave current, D is a horizontal sawtooth component of the modulated wave signal current, and E is a horizontal parabolic wave component of the modulated wave signal current. Since the horizontal retrace pulse is a pulse generated when the current flowing in the horizontal deflection coil retraces (flyback), the timing of this pulse coincides with the retrace period. Therefore, as shown in the timing chart of FIG. 5, the phase delay amounts t1, t2, t3, t4, respectively.
If various correction signal currents having the above are directly supplied to the convergence yoke, the timing of the convergence correction is delayed as compared with the horizontal scanning, so that the convergence at the left end of the screen cannot be matched in a phenomenon.

In order to correct this, conventionally, the retrace time of the convergence correction signal current is shortened as shown in FIG. 6 so that the retrace periods of all the signal currents fall within the retrace period of horizontal deflection. Was there. However, this causes the following problems. Since the convergence yoke is an inductance, the waveform of the voltage required to supply a current to it is a differential waveform of the current waveform, and that voltage must be supplied from the convergence output circuit. Further, it is necessary to add to the convergence output circuit a power supply voltage having a voltage amplitude equal to or higher than the voltage amplitude supplied from the convergence output circuit. Here, if the current waveform flowing in the convergence yoke is a sawtooth wave, the convergence output circuit needs to output a rectangular wave pulse voltage. The sawtooth current amplitude is determined by the amount of convergence or screen distortion correction,
The value becomes the same when the blanking period of the signal waveform is narrowed. Strictly speaking, the slope of the sawtooth wave is constant, and therefore the direction is slightly increased as the retrace line period is narrowed. To shorten the retrace time of the sawtooth voltage applied to the convergence yoke,
The peak value of the rectangular wave voltage output from the convergence output circuit must be increased. This is because the retrace period of the sawtooth current is tr, the inductance of the convergence yoke is Ly,
It is clear from the following equation that holds when the peak value of the rectangular wave voltage is Vp and the sawtooth current is ip. In order to increase ip = (Vp / Ly) tr∴Vp = ip (Ly / tr) Vp, it is necessary to increase the power supply voltage of the convergence output circuit. The convergence output circuit is generally configured with transistors, but since the load is an inductance, the power loss of the load is theoretically zero, and the power supplied from the power source is mostly consumed by the output transistor. Become. Therefore, increasing the power supply voltage directly increases the loss in the output transistor. If Ly is reduced from the above equation,
Although it can be seen that the increase in Vp can be suppressed, the increase in loss cannot be avoided even in this case. This is because Ly × ip ² must be constant in order to obtain the required amount of convergence correction, and if Ly is reduced, ip must be increased. The loss in the output transistor increases.

Let us consider this with numerical values when the horizontal deflection frequency is high. When the horizontal deflection frequency is high, the blanking period of the horizontal deflection current becomes short, and naturally the blanking time of the convergence correction current also needs to be narrowed. Although this alone leads to an increase in power loss, if the retrace time is shortened to correct the phase delay of the signal voltage, the power loss further increases. For example, the horizontal sync frequency is 64k
Around 2.5 Hz, the blanking time of the image monitor signal is about 2.5 μs, but the blanking time of the horizontal deflection current must be set to 2.5 μs or less in order to receive an image from this signal source. At this time, in the convergence correction current, if the delay amount of the signal with the most delayed phase is 1 μs, it is necessary to set the retrace time of the convergence correction signal to at least 1.5 μs or less in order to correct this. is there.
If the phase delay is zero, the retrace time may be 2.5 μs, but setting the retrace time to 1.5 μs means that the power supply voltage must be increased by 1.7 times, and the power loss of the convergence output circuit It will increase 1.7 times.

[0007]

As described above, in the past, in order to correct the phase delay generated in the signal processing process of the convergence circuit, it is necessary to shorten the retrace time of the correction signal, and as a result, the convergence output circuit. Power loss.

The present invention has been proposed in order to solve the problems of the prior art, and in correcting the phase delay in the signal processing process of the convergence circuit, the correction is performed without increasing the power loss. It is an object of the present invention to provide a timing pulse generation circuit capable of performing

[0009]

To achieve this object, a timing pulse generating circuit according to the present invention comprises a horizontal oscillation circuit for outputting a horizontal pulse, and a delay circuit for delaying the horizontal pulse from the horizontal oscillation circuit. A horizontal output transistor including a MOS transistor for amplifying an output pulse from the delay circuit and applying the pulse to the horizontal deflection coil, and outputs the pulse before delay output from the horizontal oscillation circuit as it is or after shaping the waveform to converge or It is configured to be used as a timing pulse for generating various signal voltages having a horizontal cycle for screen distortion correction.

[0010]

The phase relationship between the horizontal pulse output from the horizontal oscillator circuit and the blanking pulse generated in the horizontal output circuit becomes constant if a MOS transistor is used as the horizontal output transistor. The timing of the start of the line period can also be detected by the output pulse of the oscillation circuit. Therefore, if the phase of the drive pulse supplied to the horizontal output transistor is delayed, the phase of the output pulse of the oscillation pulse will advance by that amount, and this can be used as the timing pulse supplied to the convergence circuit. As a result, the various signal waveforms created by the convergence circuit have a phase advance compared with the case where the conventional retrace pulse is used as a timing pulse, so that the phase delay in the signal processing process can be corrected.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the timing pulse generating circuit according to the present invention will be described in detail below with reference to the drawings. An embodiment of this timing pulse generation circuit is shown in the block diagram of FIG. In this figure, the horizontal pulse output from the horizontal oscillation circuit 1 is sent to the waveform shaping circuit 6 and also delayed by the delay circuit 2 and sent to the horizontal drive circuit 3.
The output signal of the horizontal drive circuit is amplified by the horizontal output transistor 4 formed of a MOS transistor (metal gate type field effect transistor) and supplied to the horizontal deflection coil 5. On the other hand, the waveform shaping circuit 6 waveform-shapes the horizontal pulse to generate a timing pulse. Figure 1
In FIG. 4, the configuration of the convergence circuit part is omitted, but this timing pulse is supplied to the part of the horizontal sawtooth voltage generating circuit 12 of FIG. FIG. 2 shows an embodiment in which the delay circuit 2 and the waveform shaping circuit 6 are embodied. In this figure, the delay circuit 2 has a resistor R for integrating a horizontal pulse.
1 and a capacitor C1 and a buffer gate G1 that shapes the output of the integrator circuit. Further, the waveform shaping circuit 6 shapes an inverter gate G2 that inverts a horizontal pulse, a differentiation circuit including a capacitor C2 and a resistor R2 for differentiating the inverted output, a clipping diode D1, and an output of the differentiation circuit. And a buffer gate G3.

Next, the operation of the timing pulse generating circuit thus constructed will be described with reference to the waveform diagram of FIG. The horizontal pulse voltage waveform S1 shown by A in the figure output from the horizontal oscillation circuit 1 is integrated by the resistor R1 and the capacitor C1, and an integrated waveform S2 of B in the figure is obtained. By shaping the waveform of the integrated waveform S2 by the buffer gate G1, a pulse voltage waveform S3 shown in C in the figure, which is delayed in phase from the horizontal pulse S1, is obtained. The pulse voltage S3 is supplied to the horizontal output transistor 4 via the horizontal drive circuit 3, and the horizontal output transistor 4 receives the pulse voltage S3.
Is on during a high level (“H” level). Therefore, the pulse voltage S3 is low level (“L” level)
When the horizontal output transistor 4 turns off,
From this point, the horizontal blanking period starts, and the blanking pulse voltage S4 shown by D in the figure is obtained at the collector of the horizontal output transistor 4. By shaping the waveform of this pulse voltage S4, a retrace pulse voltage S5 (corresponding to the waveform A in FIGS. 5 and 6) shown by E in the figure is obtained. Conventionally, this retrace pulse S5 is used as a timing pulse of the convergence circuit. Was.
Here, it is described that the horizontal output transistor 4 is turned off at the timing when the pulse voltage S3 becomes "L" level, but this is limited to the case where the horizontal output transistor 4 is composed of a MOS transistor. In the switching operation by the bipolar transistor, the transistor is not immediately turned off by the minority carriers accumulated in the base layer even after the supply of the base current is cut off by overdriving, and the transistor is kept on for a short period of time. The time during which the transistor continues to be turned on is called storage time, but the storage time varies depending on the overdrive condition, the ambient temperature, and the individual bipolar transistors. Therefore, the horizontal output transistor 4 cannot be configured by the bipolar transistor.

On the other hand, since the horizontal pulse voltage waveform S1 output from the horizontal oscillation circuit 1 is inverted by the inverter gate G2, the output terminal of the inverter gate G2 is F in the figure.
A pulse voltage S6 shown in is obtained. This pulse voltage S6
Is differentiated by the capacitor C2 and the resistor R2, and the negative side is clipped by the diode D1, so that a waveform S7 as shown by G in the figure is obtained. This waveform S7 is the gate buffer G
The waveform is shaped in 3 to obtain a pulse voltage S8 indicated by H in the figure. This pulse voltage S8 is supplied to the convergence circuit as a timing pulse.

Here, as is apparent from FIG. 3, the pulse voltage S8 leads the phase of the pulse voltage S4 or S5. The amount of phase advance can be freely set by manipulating the value of the resistor R1 or the capacitance value of the capacitor C1 which is the integration time constant, and the amount of phase advance determines the amount of phase delay of the signal voltage of the convergence circuit. Can be corrected. At this time, the effect of reducing the loss can be obtained by correcting only the phase delay amount of the horizontal sawtooth current shown in B in FIG. 5 and shortening the blanking period of the signal current for other signals. However, in order to further improve the effect, the phase delay amount of the signal current (waveform shown by E in FIG. 5) having the most phase delay may be corrected. In this way, the phases of the signal currents indicated by B, C, and D in FIG. 5 advance, but the phases of these signals may be delayed through the delay circuits so that they are in phase with the signal current of E in FIG. . It is difficult to advance the phase of the signal voltage, but it is easy to delay it.For example, it is possible to delay the phase simply by inserting an amplifier circuit, and the delay amount can be adjusted to some extent by manipulating the phase characteristic of the amplifier circuit. It can be set freely. As a result, the retrace time of the convergence correction signal current may be the same as the retrace time of the horizontal deflection current, and the power loss can be minimized.

The waveform shaping circuit 6 in FIG. 1 is not essential, and although it depends on the horizontal sawtooth voltage generation circuit 12 of the convergence circuit, the pulse voltage output from the horizontal oscillation circuit 1 may be used as it is. Good. Also, the resistance R
The delay circuit 2 including the capacitor 1, the capacitor C1 and the buffer gate G1 is not limited to that of the embodiment, and a dedicated delay element may be used. Further, the resistor R1 may be configured by a variable resistor so that the delay amount can be adjusted.

[0016]

As described above, according to the present invention, since it is possible to obtain a timing pulse capable of correcting the phase delay of the signal voltage generated in the convergence correction or the screen distortion circuit, the power loss in the convergence output circuit can be obtained. Can be suppressed. Further, since the phases of various correction signal currents can be aligned with the phase of the horizontal deflection current, the quality of the screen obtained by correction is also improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a timing pulse generating circuit according to the present invention.

FIG. 2 is a circuit diagram specifically showing a main part of the timing pulse generation circuit of FIG.

FIG. 3 is a waveform diagram for explaining the operation of the timing pulse generation circuit.

FIG. 4 is a block diagram showing a configuration of a conventional deflection circuit and a convergence circuit.

FIG. 5 is a waveform diagram showing an example of the timing of a convergence correction signal according to a conventional technique.

FIG. 6 is a waveform diagram showing another example of the timing of the convergence correction signal according to the conventional technique.

[Explanation of Codes] 1 horizontal oscillation circuit 2 delay circuit 3 horizontal drive circuit 4 horizontal output transistor 5 horizontal deflection coil 6 waveform shaping circuit G1, G3 buffer gate G2 inverter gate

Claims (1)

[Claims] 1. A horizontal oscillation circuit for outputting a horizontal pulse,
The horizontal oscillation circuit includes a delay circuit for delaying the horizontal pulse from the horizontal oscillation circuit, and a horizontal output transistor including a MOS transistor for amplifying the output pulse from the delay circuit and applying the pulse to the horizontal deflection coil. A timing pulse generation circuit characterized by using the pulse before delay as it is or by shaping the waveform, and using it as a timing pulse for producing various signal voltages of a horizontal period used for convergence or screen distortion correction.