JPH0556062B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field] The present invention relates to an image processing device that can be used in copying machines, facsimile machines, etc., and in particular, it divides pixels into a plurality of regions, and each region is subjected to a plurality of image processing processes. The present invention relates to an image processing apparatus that performs parallel processing using means.

[Prior Art] Conventionally, in this type of apparatus, images are raster-scanned and read using a CCD or the like, and image processing such as binarization processing and gradation processing is performed. Recently, however, it has been proposed that this type of processing involves recognizing the tone of an image in real time, selecting and switching a process suitable for the tone, and reproducing the image.

However, in conventional digital copying machines, processing selection keys are used depending on the type of document.
If the original is expressed in halftones like a photograph, dither processing is performed, and if the original is text, slice binarization processing is performed using a certain threshold. Only the same processing is performed on the entire original. It wasn't.

On the other hand, if the image tone is identified for each region in a document containing text and photographs, it is possible to reproduce an image faithful to the document by switching the processing even within the same document. However, although many methods have already been proposed for this type of processing method, all of them are based on two-dimensional information of the image centered on the pixel of interest. In order to perform the above-mentioned image tone recognition, it is essential to have a means to store the image information obtained by raster scanning over at least two lines, which requires a huge circuit size, and therefore it is desirable to miniaturize the device. It was rare.

In addition, the processing algorithm is complicated to accurately identify it, and therefore, when considering the circuit size or processing speed when configured with hardware, it cannot be said that it has reached a practical level that can be applied to general-purpose copying machines. .

[Purpose] The present invention has been made in view of the above points, and its purpose is to process image data of a pixel of interest using image data of surrounding pixels at high speed and to suppress deterioration of image quality. An object of the present invention is to provide an image processing device that can process images with high accuracy.

In order to achieve such an object, the image processing device of the present invention includes an input means for inputting image data for each pixel (corresponding to the sensor cell in FIG. 1 in the embodiment), and an image processing apparatus for inputting image data input by the input means. A first processing means for processing image data at pixel positions included in the first region (also shown in FIG.
SH0, CPU1), and a second processing means (also a second processing means) for processing image data at pixel positions included in a second region adjacent to the first region among the image data input by the input means. SH3, CPU2 in FIG. 1); and output means (SR1, SR2 in FIG. 1) for outputting image data processed by the first and second processing means. When processing the image data of the pixel of interest included in the first region and the second region, respectively, the first and second processing means process the image in parallel using image data around the pixel of interest. Further, when processing image data of a pixel of interest located at least at the boundary between the first region and the second region, the first processing means Data input via processing means (line connecting SH3 and CPU1 in Figure 1, or
It is characterized by using data transferred between CPUs via B0 to B7 shown in FIG.

[Embodiment] First, the feature of this embodiment is that parallel image processing is performed using a plurality of one-chip image processing-dedicated microcomputers (hereinafter referred to as CPUs).

The output of the same-magnification line sensor cell is divided into multiple blocks, and the cell output of each block is calculated as described above.
Allocate each CPU's share so that parallel input is made to the A/D conversion input port of the CPU.

In order to eliminate processing inconsistencies that occur between adjacent CPUs, boundary cell information is imported and image processed in an overlapping manner by both adjacent CPUs.

The same-size line sensor and processing CPU are placed on the same board.

etc.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the image processing apparatus of the present invention. The components of each block are a sensor cell, a sample and hold circuit, the aforementioned CPU and shift register SR, etc. Each component will be explained.

In the figure, E1, E2...E41... are sensor cell groups arranged linearly. In this example, the sensor cell is a thin film type made of amorphous silicon, and its resistance value changes depending on the amount of light.A region covered with a light-shielding mask is connected in series with the cell region, and a power source is connected to both ends. The amount of light received by the cell region can be determined by detecting the potential change at the connection point between both regions. The configuration of the sensor can be similarly realized using a type that generates an electromotive force depending on the amount of light.

Due to the high output impedance or responsiveness of this type of sensor, the outputs are sent to the CPU1, SH0, SH3, etc. via sample and hold circuits (although not necessary in principle).
One to one for A/D input ports of CPU2, CPU3...
You can connect with In conventional single-magnification sensors, analog signals are serially transferred over long distances, making it impossible to read at high speed even though the response of the cell itself is fast. By using only the photodiode part of a 1x CCD sensor, the time required for serial transfer is unnecessary, allowing high-speed reading.

A well-known method in which the original is illuminated with a linear light source such as a fluorescent lamp or LED, an image is formed on a sensor array using a one-to-one imaging optical system such as a self-occurrence sensor, and the sensor and the original are moved relative to each other perpendicular to the cell arrangement direction. The scanning means performs sub-scanning. By sample-holding a signal with a predetermined period output from the scanning means (for example, in this embodiment, the LA signal shown in FIG. 1 which is input with a period of 400 usec), the divided image information is simultaneously read one line at a time. Can be read by the CPU. or,
Since the same type can be used for each sample hold circuit (SH), CPU, and shift register (SR), many can be placed on the same board, contributing to the miniaturization of the device. Furthermore, since the distance from the sensor cell to the A/D conversion is the shortest, highly reliable image reading with a good S/N ratio is possible.

In addition, each CPU during one input cycle (400 USEC)
The image tone recognition/image processing that is performed by is performed on only 8 pixels as described later, and the load placed on one CPU for image processing is small, so it is possible to perform quite complex processing in terms of time (described later). Real-time image processing is also possible by converting the image into a microcomputer and executing microcode.

In the image processing apparatus of this embodiment, the image tone is identified during the above-mentioned cycle and the binarization process is performed. 2
The converted image signal is sent to output port 01 of each CPU.
Shift registers SR1 and SR2 output from ~08 (Figures 1 and 2) and concatenated, respectively.
...(FIG. 1), the signals are latched in parallel, and sequentially output as a serial binary signal to a printer or the like using the high-speed clock CLK.

By the way, in Figure 1, the information for one line is divided into 8 pixel units, and each unit is divided into 8 pixel units.
Since the tasks are allocated to the CPUs, if continuous two-dimensional processing of image signals is performed, there is a possibility that inconsistencies in image processing between adjacent CPUs will occur as described below.

That is, focusing on the cell information of the cell E8 that the CPU 1 is in charge of, as an example of the two-dimensional processing described above, 3×
Processing that convolves the pixel of interest using a mask composed of 3 pixels (for example, 3×3 edge enhancement, etc.)
For example, in order to process the cell information of cell E8 as described above, the CPU 1 also needs each cell information of E7, E9, etc. In particular, cell information about the cell E9, which the CPU 2 is in charge of, becomes necessary. Similarly, when the CPU 2 processes the cell E9 as the pixel of interest, information on the cell E8 becomes necessary.

Therefore, in this embodiment, pixels to be input by each CPU are determined by pixel allocation as follows.
If the size of the mask applied to image tone recognition or image processing is (2n+1) x (2n+1), each CPU will further input n pieces of cell information from among the cell information handled by two adjacent CPUs. . Furthermore, the number of blocks into which one line of cell information is divided is determined by how many CPUs are assigned to one line. Therefore, in the CPU of this embodiment shown in Figs. 1 and 2, the size of the mask (matrix) for image tone recognition is 9 x 9.
Also, since the input capacity of the CPU is 16 pixels, for example, the output of the sensor cell is divided into 8 pixels each, and each CPU is responsible for the 8-pixel cell information, and the first 4 pixel cell information and the last The 4-pixel cell information is also input to two adjacent CPUs, respectively. Of course, 4-pixel cell information is also input to the CPU from two adjacent CPUs.

For example, if the number of pixels for image processing on each CPU is 32 pixels, in order to be able to process up to 9 x 9 two-dimensional image processing, a CPU that can input 40 pixels is the most practical, and it is recommended to reduce the number of CPUs. However, in the following explanation, we will explain a CPU with 16 pixel input.

Each CPU has its own CPU as shown in Figure 2.
4 pixels are further input from the adjacent CPU, overlapping with the pixels in charge of processing. For example, pixel information from E8, E7, E6, and E5 is input for the left-most pixel E9 of the CPU 2, and similarly, E17, E18, E19, and E20 are input for the right-most pixel E16. In other words, CPU2 has E to process E9 to E16.
5 to E20 will be input.

With the above configuration, in principle, the pixel of interest is surrounded by 9
Two-dimensional image processing based on ×9 pixel information becomes possible, and high-precision processing is also possible for pixels located in the vicinity between two adjacent CPUs without losing continuity.

However, when a large number of CPUs are mounted on a printed circuit board, the wiring method greatly affects the mounting density. Therefore, next is the sensor cell and CPU described above.
The connection with the chip will be explained.

The connection example shown in Figure 1 is an example when the cell arrangement density and CPU input port terminal density are equal, and when each cell is connected redundantly as described above (when the CPU input port terminal density is higher than the pattern density) ) uses a chip carrier, etc. to arrange input terminals on opposite sides of each adjacent CPU chip, and forms a pattern in which the opposite terminals of both adjacent chips are arranged in a "staggered" pattern, thereby achieving high density on three sides. Wiring is configured by mounting.
It should be noted that if the CPU input port terminal density is lower than the cell arrangement density, it goes without saying that connection can be made on only one side of the chip.

Other connection methods include the wiring methods shown in FIGS. 6a-d. However, the connection method in FIG. 6a is the same as that in FIG. 1. Figures 6a to 6d focus on the input wiring from the sample and hold circuit SH to the CPU. That is, Figure 6 a and d are QIP (Quad
This is a wiring diagram when using an IC package (Inline Package) type or chip carrier. In the figure,
The dot at the intersection of the IC package and the wiring is an input terminal, indicating that input is being input into the IC chip from there. Also, the dotted lines indicate the wiring on the printed wiring board.
Indicates that it is hidden by an IC package etc.
For example, if a large number of CPUs are mounted on a ceramic thick film multi-chip substrate as shown in FIGS. 6a to 6d, high-density mounting is possible without wiring crossing.

Next, the CPU will be explained. FIG. 2 is a block diagram showing the internal configuration of a one-chip microcomputer (hereinafter referred to as CPU) of the image processing device. First, the part surrounded by the dotted line is the CPU,
It has a 16-channel successive approximation type A/D converter built into an 8-bit microprocessor. These 16 analog inputs (An1 to An16)
is multiplexed by two multiplexers within the chip, one input is selected according to the setting of the A/D channel mode register, and the selected analog input is multiplexed by two A/D multiplexers with the following configuration.
It is digitized by a D converter.

The configuration of each A/D converter is a sample hold circuit (SH4 or SH5), voltage comparator 3
(or 4), tap decoder 3 (or 4) and
Consists of SAR3 (or 4). SAR
(Successive Approximation Register) 3 (or 4) constitutes a D/A converter together with a tap decoder 3 (or 4) and a control 3 (or 4) that generates timing.

Voltage comparator 3 (or 4) connects the sampled and held analog input to tap decoder 3.
(or 4) Compare the difference with each voltage tap of the series resistor string. This series resistor string is connected between a terminal (not shown) that receives an external A/D reference voltage (Vref) and an A/D ground terminal (not shown), and converts the voltage between the two terminals into 256 equivalent consists of 256 equivalent resistors for voltage steps.

The voltage taps of the series resistor strings are selectively driven by an 8-bit shift register SAR3 (or 4). SAR3 (or 4) is the most significant bit (MSB) of SAR3 (or 4) until the output of the voltage tap of the series resistor string matches the analog input (until the output of the comparator is inverted).
Set one bit at a time.

In other words, when A/D conversion starts, SAR
Set the 3 (or 4) MSB and select 1/2Vref of the series resistor string voltage tap to compare with the analog input. If the analog input is 1/2Vref
If it is greater, leave the MSB of SAR 3 (or 4) set, and if it is less than 1/2Vref, reset the MSB. Next, set the next lower bit of the MSB, set the voltage tap of the series resistor string to 3/4Vref or 1/4Vref, and compare with the analog input. In this way, each bit from the most significant bit to the least significant bit is sequentially changed and compared with the voltage value selected by SAR 3 (or 4) to determine.

When the 8-bit comparison is completed, SAR3 (or 4) holds the digital value of the analog input, and the result is latched into the CR1-CR4 (CR5-CR8) registers.

The A/D channel mode register is set to An1 to An4 (and An9 to An12) or
The analog inputs of An5 to An8 (and An13 to An16) can be selected in units of 4 channels. For example, if you select An1 to An4 (An9 to An12), the analog input will be An1 (An9).
→An2 (An10) →An3 (An11) →An4
(An12) are selected and A/D converted. The A/D conversion value of each input is CR1 (CR5) → CR2
They are stored in the order of (CR6) → CR3 (CR7) → CR4 (CR8).

When the converted values are aligned in the four CR registers, that is, when the A/D conversion in units of four channels is completed, an internal interrupt request (hereinafter referred to as A/D interrupt) is generated. Priorities are set for interrupts on the CR1 to CR4 side and CR8 side, and two A/D
Even if an interrupt request occurs, it will be processed in priority order. The priority is higher for CR1 to CR4.

The interrupt procedure in the control flow of FIGS. 5a to 5j, which will be described later, first starts A/D conversion of each channel An1 to An4 and An9 to An12. Each A/
The D converter performs A/D conversion, and when there is an A/D interrupt, the channel An stored in CR1 to CR4 is
Perform the processing of 1 to An4, and A/
Has D interrupt. When the next A/D interrupt occurs
Channels An9 to An1 stored in CR5 to CR8
2, then An5 to An8, An13
~An16 A/D conversion is started and the same processing as described above is performed. Another method is to improve the overall throughput by overlapping the A/D conversion of the four pixels in the group An9 to An16 while image processing the four pixels in the group An1 to An8.

Next, the components of the 8-bit microprocessor within the CPU will be explained. ALU that performs calculations
(Arithmetic Logic Unit) section, input ports I ₀ to I ₇ (signals of MOD 1 to 8 are input to the input ports) that perform input/output interface from the outside, and output ports O ₁ to _{O 8} , and Fig. 5 A program memory that stores a control program that describes control procedures/processing procedures such as a to j, a program counter that holds the instruction execution address, an instruction register that holds the instruction code pointed to by the program counter, an instruction decoder that analyzes the instruction, and a microprocessor. High-speed internal registers used by the processor when executing instructions (details will be explained later), data memory which is main memory that can be read and written, and data memory that temporarily saves the contents of the various registers etc. during interrupts or subroutine calls.
PSW Program Status Word) registers and internal buses.

In this embodiment, as an example, a program memory capacity of 2 Kbytes and a data memory (RAM) capacity of 256 bytes are provided. By replacing the data processing program in the program memory, various image processing can be flexibly handled. For example, by inputting an external signal from the input ports of MODs 1 to 8, it is possible to replace the program in the program memory and change the processing contents from the outside.

The terminals of the CPU are An1 to An16, I ₀ to _{I 7} (input port), O ₁ to O ₈ (output port, INT terminal which is an external interrupt input), and power terminals Vcc, Vss, AVcc (not shown). A/D power supply, AVss
(GND for A/D), Vref (reference voltage input for A/D), RESET terminal, START signal terminal, STOP signal terminal, X1 and X2 (crystal connection terminals for built-in clock oscillation, etc.).

In this embodiment, an interrupt signal from outside the CPU, such as an LA (Line Advance) signal obtained from a horizontal synchronization signal in the sub-scanning direction of the input system, is input to the INT terminal in this embodiment.

Figure 3a shows the A/D stored in the data memory.
It shows the memory layout of image signals, etc. after conversion. The main thing that is stored is the image signal A
(X, Y) (X=1 to 16, Y=1 to 9) b(Y) (Y=
1 to 9), and a(X) that holds the sum of density differences between adjacent pixels in the sub-operation direction. X and Y are an X counter and a Y counter in internal registers of the CPU, which will be described later. If the X direction is the main scanning direction and the Y direction is the sub scanning direction, A(X, Y) is the coordinate (X, Y)
The image information in the 16×9 memory map is shown by , and a(X)=Σ|A(X,Y)−A(X,Y−
1) |, b(Y)=Σ|A(X,Y)-A(X-1,Y)
becomes ｜.

A (X, Y) in Fig. 3a is a memory map obtained when the control procedures shown in Fig. 5 a to j are executed in the state of the sensor cell, sample board circuit CPU, and their wiring shown in Fig. 2. be. As can be seen from the comparison with Figure 2, A (X, Y) (X = 1 ~
4, Y=1-9) is image information of sensor cells E5-E8, A(X, Y) (X=5-12, Y=1-9) is image information of E9-E16, A(X, Y) (X=13～
16, Y=1 to 9) is the image information of E17 to E20. The image processing procedure shown in FIG. 5 a to j is the third
As shown in Figure c, A(X,
The center pixel (W
+5, 5) (W=0 to 7). When this 9x9 matrix is binarized while sequentially shifting from the left end to the right end of the 16x9 memory map (while changing W) and performing image tone recognition, this CPU will convert the coordinates (5, 5), (6 , 5), ~
This means that the image information at the position (12, 5), that is, the image information of the sensor cells E9 to E16, is binarized while considering the image information E5 to E8, E17 to E20 of the adjacent sensor arrays.

A plurality of such CPUs perform binarization while recognizing the image tone in parallel, and when all the CPUs complete the binarization of one line, the sensor cell advances one line in the sub-scanning direction. At this time, the image information in the 16×9 memory map is shifted by one line in the sub-scanning direction (in the direction of the arrow in the figure). Then, add a new A/
D-converted image information is stored. Then, the above-described image tone recognition, binarization, and line shift are repeated. In this way, the CPU is E9~
It becomes possible to perform image tone recognition and binarization two-dimensionally and continuously on the image information from E16 in the main scanning direction and the sub-scanning direction.

Since such binarization is performed simultaneously by a plurality of CPUs, binarization processing can be realized while performing two-dimensional image tone recognition in real time.

To supplement the explanation of Figure 3c, if we assume that the 9x9 matrix in the 16x9 memory map is shifted by W pixels (W = 0 to 7) from the left edge, then any image information coordinate in the 9x16 memory map is (X+W,
The center pixel position that is converted to the absolute position of Y) (X=1 to 9, Y=1 to 9) and binarized is (W+5,
5). The 9×9 matrix can be shifted by changing the variable W from 0 to 7.

FIG. 3b shows the layout of the internal registers.
Inside there are various 8-bit wide registers, counters, and 1-bit flags. RES (Result) register is (5, 5), (6, 5), ~ (12, 5) 8
The result of binarizing pixels based on the T (threshold value) register is held. The max register holds the maximum density value within the 9x9 matrix, and the min register similarly holds the minimum density value. The BLC counter is a counter that selects one threshold value from a threshold value matrix (8×8) to be described later, and takes a value of 0 to 63. The C registers are (5, 5), (6, 5), ~ (12,
This is a register for inputting the 8-pixel binarization result of 5) into a predetermined position of the RES register.

The role of the F/FL (Flag for First Line completed) flag and the F/out (Flog for Output) flag is to distinguish between the initial start of the image processing device and other times for processing control purposes. . In other words, the F/FL flag is used to differentiate between pixels since it is not possible to obtain the density difference between adjacent pixels in the sub-scanning direction for the first line at the initial start.On the other hand, the F/OUT flag is set to 9
Image tone recognition of the ×9 matrix cannot be performed until all data is stored in the 16 × 9 memory map,
After that, image tone recognition can be performed every time one line is A/D converted, so this is for the purpose of distinguishing between them.

Figure 4 shows that the CPU performs two-dimensional image tone recognition.
This is a schematic flowchart at a macro level of a processing procedure for selecting a threshold value and binarizing it. First, explanation will be given according to this general flowchart.

In step 10, one line of An1 to An16 is A/D converted and stored in the CR register, and then in step 11.
Then, the sum of absolute values of density differences between adjacent pixels in the main scanning direction is stored in b(y). In step 12, as described above, it is determined whether all the image information has been stored in the 16×9 memory map. The F/out flag performs image tone recognition while shifting one pixel at a time in the main scanning direction in the 9x9 matrix of this embodiment, and
In order to perform image tone recognition while shifting line by line in the sub-scanning direction, once the image information is stored in the 16×9 memory map, the flag is used to perform image tone recognition for each line thereafter. Therefore, the process first proceeds to step 13, where the sum of density differences between adjacent pixels in the sub-scanning direction (pixels of the previous line) is integrated into a(x), and at step 14, the contents of the CR register (that is, the A/D (image information of the converted line)
Store in a 16x9 memory map. Proceed by one line in the sub-scanning direction (step 15). Repeat steps 10 to 16 until 9 lines are completed. 16
If everything is stored in ×9 memory map, F/
Set the out flag (step 17).

Next, a 9x9 matrix is set from the left end of the 16x9 memory map (step 18), and the sum of density differences between adjacent pixels in both the main and sub-scanning directions is accumulated in register S (at this time, (Using the sum a(x) of density differences between adjacent pixels in the scanning direction) (Step 19), Step
In steps 20 and 21, the maximum/minimum density values in the 9×9 matrix are determined and stored in the max and min registers, respectively. In step 22, image tone recognition is performed based on the formula. In addition, if the values within 9×9 are the same density value, S/
(max-min) is 0/0, but it is set to 0. In step 23, a threshold value is selected according to the image tone recognition result, and the 9×9 center pixel is binarized using the threshold value and stored in the RES register (step 24). The 9.times.9 matrix is shifted in the main scanning direction (step 25), and the above operation is repeated until the center pixels of 8 pixels are processed.

When the binarization of 8 pixels is completed, preparations are made for shifting the memory map line by line in step 27. That is, the density difference between adjacent pixels on lines 1 and 2 is subtracted from a(x) (step 27).
Then, the memory map is advanced one line at a time (step 28). The contents of the RES register (the CPU
(binarized data of the 8 pixels in charge) is output from the output port (step 29), the RES register is cleared (step 30), and the process returns to step 10.

From then on, each time one line is A/D converted, the density difference between the image information and line 8 is calculated and a(x) is updated (step 31), and the image information is converted into the 16 x 9 line of line 9.
The image is stored in the memory map (step 32), and the image tone recognition and binarization described above are repeated.

Next, the operation of the CPU will be explained in more detail using FIGS. 5a to 5j.

FIG. 5a shows the main flow of the processing program. In step 1, the CUP initializes input/output ports, data memory, A/D channel registers, and interrupts, and in step 41, the CUP initializes input/output ports, data memory, A/D channel registers, and interrupts.
Waiting for START signal. This START signal is
This is a signal from other control means that controls the entire CPU, and is used to start image input. this
Upon receiving the START signal, the CPU permits interrupts in step 42, and enters the HALT state in step 43 to stop processing. This HALT state can only be released by incrementing the program counter by a return command after processing an interrupt, or by RESET (signal or power cycle). Therefore, after processing interrupts such as external interrupts (LA) or A/D interrupts, the main flow is step 44.
Proceed to. In step 44, it is determined whether or not to end the process. If there is no STOP signal, the process returns to step 43 and the HALT state is established again. If there is a STOP signal, the process proceeds to step 45. This STOP signal is also the START signal mentioned above.
Similar to signals, these are sent from other control means. In step 45, external interrupt (LA) and A/D
After disabling interrupts, the process returns to step 40 and repeats the above process.

FIG. 5b is a flowchart of interrupt waiting and interrupt processing during HALT. Therefore, after the above-mentioned external interrupt is enabled or the later-described A/D interrupt is enabled, interrupt waiting is performed at step 50 in FIG. 5b. First, at step 50, an interrupt is waited for. If there is an interrupt, is it an external interrupt or an A/D interrupt (there are 4 types as explained later)?
The interrupt address is determined from the interrupt vector (step 52).

Next, in step 54, a return address is determined (in this embodiment, step 44 is the return destination),
In order to be able to return to the original state even if the program returns at step 56, various registers in the microprocessor and the return address are saved in the PSW register, and the interrupt address (in this embodiment, steps 60, 70, 70, etc. depending on the type of interrupt) is saved. 100, 130, or 160).

Next, using the flowchart of FIG. 5c, an explanation will be given of the external interrupt processing routine using the LA signal, which is a reference for all processing and is generated every 400 μsec.
First, when an external interrupt occurs at step 50 (FIG. 5b), the program jumps to the address indicated by the interrupt vector address (step 60 in this embodiment). In step 60, the flag F/OUT is checked (this flag indicates whether or not all of the first nine lines after the initial start described above have been stored in the data map).

The fact that this flag is set indicates that at least the density data of all pixels has been stored in the data map, and that the image processing up to the previous line (binaryization of 8 pixels in this example) has also been completed. Therefore, the process proceeds to step 62, and the register storing the image-processed 8-bit output data is stored.
Output RES to output port, then register
Clear RES and proceed to step 64. On the other hand, if the flag F/OUT is not set, all data has not been stored in the data map yet, so step 64 is directly executed without outputting the register RES.
Proceed to.

In step 64, An1 to An4 are stored in the A/D channel register for setting the A/D conversion mode.
and data for selecting channels An9 to An12, and in step 66, disables external interrupts (LA signal) and A/D interrupts,
In step 68, an A/D start command is sent to the A/D converter to perform A/D conversion according to the contents of the A/D channel register, and the A/D converter returns to the return destination address where the interrupt occurred. Wait for D interrupt.

5d to 5j are all A/D interrupt processing routines. Interrupts occur 4 times during 400 μsec of reference signal LA, and the timing is 1st = An
1~An4, 2nd time=An9~An12, 3rd time=
An5 to An8, 4th time = 4 each of An13 to An16
This occurs for each channel A/D conversion.

At step 50, when an A/D interrupt occurs, the program jumps to the address indicated by the vector address as described above. This vector address is step 70 if the first time = An1 to An4, and the second time =
For An9 to An12, step 100, 3rd time =
If An5 to An8, step 130, 4th = An
13 to An16, step 160 is reached.

The processing flow for the first line, ie, the A/D interrupt for starting storage in the memory map, will be explained below. In the processing for the first line, the flags F/FL and F/OUT are of course reset. The first A/D interrupts to occur will be An1-An4.

When an interrupt from An1 to An4 occurs, the process jumps to step 70, and from step 70 to step 74, An1 to An4 are processed.
The absolute value of the difference between the registers CR1 to CR4 in which the results of A/D conversion of the four channels of An4 are stored is determined and stored in b(y) in the data memory.
Next, in step 76, check the status of flag F/FL,
Since this flag is not set for the first line, the process advances to step 78. In step 78, CR1 to CR4 store the pixel density of the current line.
The contents of are stored as they are in A(1,1) to A(4,1). The reason why it is stored as is is that there is no previous line for the first line. Then, the process returns to step 50 and waits for the next An9 to An12 interrupt.

When An9 to An12 interrupts occur, An9 is stored in CR5 to CR8 in steps 100 to 104.
〜The sum of the absolute values of the differences in concentration of An12 is b as described above.
It accumulates in (y). Then, proceed from step 106 to step 108, and step A (9, 1) to A (12, 1).
The density of pixels An9 to An12 is stored in . Next, proceed to step 122, set channels (5, 8) to (13, 16) in the A/D channel register, and then
Start D conversion and return to step 50 to wait for the next interrupt.

The next interrupt occurs from channels 5-8. When the interrupt occurs, steps 130 to 134 are executed.
Then step b in the same way as steps 100 to 104 described above.
The absolute value of the density difference in the main scanning direction is accumulated in (y). Then, in step 136, the flag is checked, and since the processing of the first line has not yet been completed, the process proceeds to step 138, where An5 to An5 stored in CR1 to CR4 are stored.
The pixel density of An8 is stored in A(5,1) to A(8,1), and the process returns to step 50 to wait for an interrupt from channels 13 to 16.

When an A/D interrupt from channels 13 to 16 occurs, the absolute values of pixel density differences in the main scanning direction are similarly accumulated in steps 160 to 164, and the pixel density of the first line is set to A( 13, 1) ~
Store in A(16,1). The process then proceeds to step 200 in FIG. 5h. At this point, the absolute value of the density difference in the main scanning direction of the first line is b(y), An1 to An1
This means that the pixel density of 6 is stored in A(1,1) to A(16,1). Also, since other CPUs are also performing the above operations at the same time, pixel data for one entire line is stored.

Next, in step 200, the y counter is incremented by one in preparation for the next line. In step 202, it is checked whether the processing of 9 lines has been completed, and since it has not been completed (NO), the process advances to step 204 and the flag F/OUT is checked. The reason why the flag F/OUT is checked in step 204 after checking y=10 in step 202 is as follows. In other words, when 9 lines of data have been stored (if y=10), the step
At 208, return the counter y to the initial value 1 and continue the steps.
At 210, flag F/OUT is set. In the subsequent flow, the center pixel is binarized while recognizing the image tone in the 16×9 memory map, but from the 10th line onward, image tone recognition is performed line by line and the center pixel is binarized. Since value conversion is to be performed, step 204 is provided in order to proceed to step 212 and subsequent steps even if y≠10 in step 202.

Now, after checking the flags in step 204, the process goes to step 206 and sets the flag F/FL indicating that data storage of the pixels of the first line has been completed.
Step to wait for next external (LA signal) interrupt
Return to 50.

Occurs when the scanning system moves in the sub-scanning direction.
When the LA signal is generated again, the interrupt processing flow shown in FIG. 5b is transferred to the external interrupt flow shown in FIG. 5c, and steps 60 to 68 described above are repeated to start A/D conversion. Then, it waits for interrupts from channels 1 to 4 and channels 9 to 12 again.

When an interrupt from channels 1 to 4 occurs, the process jumps to step 70, repeats steps 70 to 74, and then proceeds to step 76. Since the flag F/FL has been set this time, proceed to step 80 and read CR1, which stores the pixel density of the current line (second line).
~CR4 and the pixel density A (1, y-1) stored in the data memory of the previous line (y-1) ~A
(4, y-1), that is, the sum of the absolute values of density differences in the sub-scanning direction, are accumulated in a(1) to a(4). Next, in step 88, the flag F/OUT is checked and since the processing of 9 lines has not yet been completed (NO), the process proceeds to step 90, where the process A(1, y) to A corresponding to the current line indicated by the counter y. (4,y)
The density of pixels An1 to An is stored, and the process returns to step 50 to wait for the next interrupt from An9 to An12.

When an interrupt from An9 to An12 occurs, the sum of the absolute values of the density differences in the main scanning direction in steps 100 to 104 is cumulatively processed, and then in step 106,
In steps 110 to 116, the sum of absolute values of density differences in the sub-scanning direction is accumulated, and then in steps 118 and 116, the sum of absolute values of density differences in the sub-scanning direction is accumulated.
A(9, y) indicated by counter y at step 120
A(12, y) stores the contents of CR5 to CR8 in which the pixel density of the current line is stored. Then, in step 122, An5 to An8 and An13 to
In order to perform A/D conversion of An16,
Set the D channel register, execute the A/D conversion start command to perform A/D according to the contents of this A/D channel register, and step to wait for an interrupt from channels (5 to 8).
Return to 50.

FIG. 5f shows the flow of interrupt processing from channels (5 to 8). Also, Figure 5g shows the channel (13
This is the interrupt processing flow from 16) to 16). The details of the processing are basically the same as those for channels (1 to 4) and channels (9 to 12), and will therefore be omitted.

Next, step 200 → step → 202 step →
Return to step 50 from step 204 → 206. The flow shown in FIGS. 5c to 5g is repeated until y=10 in step 202, that is, until all the pixel density information is stored in the memory map of FIG. 3a. After the above repetition, y=10 in step 202
Then, in step 208, set y to the initial value (y=1)
Then, in step 210, a flag F/OUT indicating that image processing calculations and output of the results are now possible is set, and the process then proceeds to the image tone determination flow.

Next, calculations for image tone determination are performed from step 212 onwards, but the conditions for this are as follows: First, the first 9 lines (line 1 to line 9) x (An1 to An16), 144 This is after all pixel data has been stored. That is, once the first nine lines of data have been stored, image tone determination is performed every time one line of 16 pixels is stored.

In this embodiment, by using an image processing processor, pixel judgment can be performed sequentially.
It is no longer necessary to perform judgment and output for each block each time a block such as 8 is shifted.
For this reason, line 5 of the memory map shown in Figure 3a
8 pixels from (5, 5) to (12, 5) (encircled by a solid line) are subjected to predetermined calculations on a 9x9 pixel block centered on each pixel, and a threshold value suitable for the pixel is calculated. Binarization is performed using this method.

Next, counters and the like used in the following flow will be explained again with reference to FIGS. 3b and 3c. The range for image tone recognition is the 9×9 matrix shown in FIG. 3c. The counter W is changed so that the matrix can be moved within the 16×9 memory map.
Further, pixels in the 9×9 matrix are designated by (x+w, y) as shown in FIG. 3c. (w+5, 5) is the center pixel position where binarization is performed. Counter c is a counter for specifying the bit position in the RES register. Also, max register and min
The register is a register that holds the maximum and minimum density within 9x9, and their initial values are 0 and 0, respectively.
It is 63. The max register can take values from 0 to 63. Originally, since it is an 8-bit A/D conversion, the range should be 0 to 255, but the processing capacity becomes large, and processing with the upper 6 bits of the 8 bits has almost no effect on the image. For this reason, all calculations and judgments are performed within the range of 0 to 63 of the upper 6 bits.

Next, image tone recognition will be explained. step
Counters c, x, y, w and registers from 212 to 219
Initialize min and max respectively. At this point 9×9
The matrix is located at the left end of the 16x9 memory map.

Next, steps 220 to 228 are repeated until the counter x reaches 9 (until it reaches the right end of the 9x9 matrix), and the absolute value of the density difference between adjacent pixels in the main scanning direction within 9x9 is stored in the register S. Value | A(x
+w, y) - A(x+w, y) | stores the cumulative value,
Similarly, the maximum density value in the main scanning direction within 9×9 is stored in the register max, and the minimum density value is stored in the register min.

Next, return the counter x to 1 (step 230)
Counter y is counted up and steps 220 to 234 are repeated until y=10. Thus, the S, max, and min registers store the cumulative values, maximum values, and minimum values of all 9 lines.

The repeating flow from step 236 to step 240 is the cumulative value a of the density difference in the sub-scanning direction mentioned above.
This is a flow for adding (x) to register S. The result register S stores the sum of density differences between adjacent pixels in both the main and sub-scanning directions within 9×9.

In steps 242 and 244, counters x and y are returned to their initial values, and in step 246, the contents of register S are divided by register max minus register min, and the quotient is stored in register S. This quotient should reflect the image tone within 9×9, and the binarization threshold may be selected according to this number. Step 250 of Figure 5 i
~Step 266 is the flow for selecting this threshold value. The selected threshold value is stored in register T.

As the threshold value, first, one of the matrices BL (block) 1 to BL8 is selected according to the value of S, as shown in FIGS. 7a to 7h. Each BL is 8
One threshold value of the ×8 matrix is selected according to the value of the counter BLC. counter BLC
can take values from 1 to 64, so by sequentially changing the value of the counter BLC, the center pixel is binarized using the optimal threshold while continuously recognizing the tone of the 9 x 9 pixel block. be. Details of each matrix BL will be described later.

At step 268, the density value A(w+5,5) of the center pixel (w+5,5) and the register T are compared for binarization. If the pixel density is greater than the threshold, in step 270 register RES and counter c
Take a Logical Or with. counter c
Since there are eight pixels of interest, the role of is to store the binarized result in a predetermined bit position of the 8-bit register RES.

When the binarization result is stored in the register RES, in step 272, the counter w is incremented by one. By incrementing the counter w, the 9x9 matrix can be moved within the 16x9 memory map.

The loop from step 274 to step 278 is a counter.
This is a flow for counting up BLC in order.

At step 280, the contents of counter c are shifted to the left by one bit. Therefore, the values of C are 1, 2, 4,
It will be either 8, 16, 32, 64, or 128. thus,
In step 270, the binarization result can be stored in the register RES with the bit positions sequentially shifted. In step 282, check whether the counter w has become equal to 8 or not, and repeat steps 220 and subsequent steps until all eight pixels at the center have been binarized, and register the binarization results.
Store in RES.

Next, in steps 290 and 292, counters x and w are initialized. Furthermore, in steps 300 to 314
In order to sequentially shift the data stored in the 16×9 memory map upward one line at a time, a(x) is executed in step 294.
The density difference |A(x, 1)−A(x, 2)| between adjacent pixels in the sub-scanning direction between the first line and the second line is subtracted from the subtracting value, and this is performed for all pixels in the main-scanning direction.
In this way, each a(x) stores the pixel density difference in the sub-scanning direction from line 2 to line 9.

Therefore, in steps 300 to 314, the memory map is sequentially shifted. Therefore, the ninth line in the memory map becomes empty, allowing data to be stored by scanning the next line. Then, in step 316, the program returns to the return destination address to wait for the next external interrupt.

The flow from step 212 to step 314 has been described above until the binarization of the first nine lines is completed. At this point, register RES contains 16x9
The binarization results of the middle pixels of the memory map are stored, and the pixel density data of the previous eight lines are stored in the first to eighth lines of the 16×9 memory map.

Therefore, when the scanning means moves one line in the sub-scanning direction and the next external interrupt occurs, the process goes to step 60 in FIG. death,
Repeat the above flow for the next line.

From this point on, the flag F/OUT remains set, so step 88 in Figure 5 d and Figure 5 e
step 118 of FIG. 5f, step 148 of FIG.
At step 178 in Figure G, the steps proceed to steps 92, 124, 152 and 182, respectively, and the pixel densities stored in the CR register are sequentially stored in the ninth line of the memory map. In this way, thereafter, image tone recognition and binarization within the 9×9 matrix are performed every time one line is read.

The output from the register RES is temporarily held in the shift register SR shown in FIG. 1, and is serially output from the concatenated shift registers SR. In this way, the parallel-processed image signals are recognized in real time and binarized.

The image tone recognition method explained above is performed by shifting the center pixel one pixel at a time, but of course the 16x9 memory map is divided into blocks of the size of the threshold matrix, and each block is divided into binary values using the threshold matrix. The same effect can be obtained even if Even in this case, the image signal of the adjacent CPU is imported, so
There is no mismatch between CPUs, and even faster image processing is possible.

Next, the matrix BL1~ shown in Figure 7 a~h
I will explain BL8.

BL1 (Figure 7a): Dot concentrated matrix with emphasis on gradation reproduction. The threshold range is 32 gradations from 2 to 62, and the output format is 2 dots/8×8.

BL2 (Fig. 7b): A dot-concentrated matrix that emphasizes gradation reproduction and takes resolution into account, with a threshold of 32 gradations from 2 to 62, and an output format of 4 dots/8 x 8.
becomes.

BL3 (Figure 7c): A dither processing matrix that takes resolution into consideration and emphasizes contrast. The threshold is 17 gradations from 16 to 48, and the output format is 4 dots/8×
It becomes 8.

BL4 (Fig. 7d): Matrix with constant threshold value (32). The binarization process results in two gradations.

BL5 (Fig. 7e): Same as BL3, a dither processing matrix that takes resolution into consideration and emphasizes contrast. The threshold value is 17 gradations from 16 to 48, and the output format is 4 dots/8×8.

BL6 (FIG. 7f): A dither processing matrix consisting of a small matrix targeted for halftone dot originals. The threshold is
The output format is 16 dots/8×8 with 5 gradations of 20, 28, 36, and 44.

BL7 (Figure 7g): A matrix in which the phase of BL6 is changed by 90° for the purpose of suppressing moiré.

BL8 (Fig. 7h): This is a matrix in which the phase of BL6 is changed by 180° for the purpose of moire suppression.

By selectively using the above eight types of matrices according to the image tone, it is possible to provide realistic reproducibility of halftones, characters, and halftone dots.

FIGS. 8 and 9 are diagrams of other embodiments of the CPU. The CPUs shown in Figures 1 and 2 input image signals from adjacent CPUs into the A/D conversion section, but
In this embodiment, the pixel density A/D converted by the adjacent CPU is taken in via external buses B0 to B15. Even in this manner, a memory map as shown in FIG. 10 can be obtained.

[Effects] As described above, according to the image processing device of the present invention, when processing image data of a pixel of interest using image data of surrounding pixels, accuracy can be improved at high speed while suppressing deterioration of image quality. This allows for better processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention and a diagram explaining the wiring of each component, FIG. 2 is a block diagram showing the internal configuration of the CPU in the image processing means,
Figure 3a shows the memory layout of the data memory in the CPU and the image signal input and processing system, Figure 3b shows the layout of the internal registers in the CPU, and Figure 3c shows the data memory. 4 is a flowchart showing an outline of image processing related to one method of the embodiment, and FIG. 5a is a main flow chart showing the image processing of the embodiment. Chart, Figures 5b-j are flowcharts showing details of image processing, Figures 6a-d
is a diagram showing the wiring method on the board, Figures 7 a to h are diagrams of the threshold matrix for binarization, and Figures 8 to 9
The figure shows another method of coupling between CPUs.
FIG. 0 is a diagram showing an input system when image information is input using another combination method. In the figure, E...sensor cell, SH...sample hold circuit, CPU...image processing means, SR...shift register, An...image information signal, SAR...
Successive approximation register, CR...A/D conversion value storage register, Alu...Logic operation section, F/FL...1st
Line processing flag, F/OUT... Output enabled flag.

Claims (1)

[Scope of Claims] 1. An input means for inputting image data for each pixel; and a first processing means for processing image data at a pixel position included in a first region among the image data input by the input means. and a second processing means for processing image data at pixel positions included in a second region adjacent to the first region among the image data input by the input means; and the first and second processing means. and an output means for outputting image data processed by the processing means, wherein the first and second processing means are arranged to output image data processed by the first and second processing means, respectively. When processing the image data of a pixel, the image data is processed in parallel using image data around the pixel of interest, and further, the first processing means processes at least the first region and the second region. An image processing apparatus characterized in that when processing image data of a pixel of interest located at a boundary with a region, data inputted via the second processing means is used.