JPH0555974A - Transmission timing control circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of a line by controlling a load signal for an address counter for a transmission timing ROM so as to avoid overlap of in-band data on a satellite. CONSTITUTION:A variable shift register 2 delays a frame synchronization timing detected by a reception frame synchronizing circuit 1 in response to an external shift quantity control signal 103. The delayed frame synchronizing signal is used to load an address counter 3 generating an address signal for a timing ROM 4. A transmission frame generating circuit 5 outputs in-band data in response to a timing signal 107 from the timing ROM 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission timing control circuit, and more particularly to an SCPC (Single Channel).
The present invention relates to a transmission timing control circuit used in a VSAT system operated by a demand assign multiple access system of a Per Carrier type.

[0002]

2. Description of the Related Art In a satellite communication system to which a demand assign multiple access system is applied, as shown in FIG. 5, a central control station 100 includes a satellite channel controller 10 and a common channel connected to the satellite channel controller 10 for modulating and demodulating a common channel signal. A circuit switching modulator / demodulator 13 that is connected to the modulator / demodulator 11 and the data terminal equipment (DTE) 12 and modulates / demodulates individual line signals is installed.
At the stations 2-1 and 2-2, a circuit switching system indoor device 20, a circuit switching system outdoor device 21, and a DTE 22 are installed.

The connection method is SCPC (Single Ch
Since the circuit is a demand-assign multiple access by an Anne Per Carrier, the circuit switching system modulator / demodulator 13 installed in the centralized control station 100 is also connected to the VSAT station 2-.
The line switching indoor units 20 of 1 and 2 are also synchronized with the common channel shared by the network during standby, and when a call occurs, the satellite line controller 10 of the central control station 100.
To issue a channel allocation request to the satellite channel control device 10,
The circuit switching system modulator / demodulator 20 (or circuit switching system indoor unit 21) of the station where the call originated and the circuit switching system modulator / demodulator 20 (or circuit switching system indoor unit 21) of the communication partner station are pooled in advance. Allocate one set of the individual line channels that have been set. In response to this, the calling station and the communication partner station perform transmission / reception using the assigned individual channel. When the call ends, both the calling station and the communication partner station wait in synchronism with the common channel again.

Normally, in the common line channel, the common line signal is exchanged between the common line modulation / demodulation device 11 and the circuit switching system indoor unit 20 of the VSAT station as shown in FIGS. 6 (a) and 6 (b). The slot aloha format is used for. The signal output from the common line modulation / demodulation device 11, that is, the out-band data, is the continuous signal shown in FIG. 7A and has a periodic frame structure. On the other hand, the signal input to the common line modulation / demodulation device 11, that is, the in-band data is the burst signal shown in FIG. 9B, and the transmission timing of the burst signal is synchronized with the frame of the out-band data. Specifically, a transmission frame generation circuit (described later) is operated by a detection signal when a frame synchronization signal (PB) periodically inserted in the outband data sent from the satellite line control device 10 is detected. It has started. Also, there is no signal period between bursts of in-band data, and this is called a guard time. This is provided to prevent the in-band data from overlapping due to fluctuations in the transmission / reception frequency that accompany the satellites constantly changing within the orbit holding range and differences in the distance from the VSAT station on the ground to the satellites. It is a period of time. The satellite line control device 10 uses a common channel to perform a health check on whether or not the circuit switching indoor device 20 of each VSAT station is operating normally, and controls and monitors the device.

Next, FIG. 2 shows a configuration example of a conventional transmission timing control circuit used in the common line modulation / demodulation device 11. A reception frame synchronization circuit 1 for detecting a frame synchronization signal (FB) periodically inserted in the reception signal 101 from the demodulator to establish frame synchronization on the reception side and outputting a reception frame signal 102; Frame signal 10
2 and the transmission clock signal 105 are input, the transmission clock signal 105 is counted up from an initial value preset corresponding to the reception frame signal 102, and the count value is output as the address signal 106. A timing ROM 4 for inputting the address signal 106 and outputting the data stored in the corresponding address as the timing signal 107;
07 and common line signal 108 are input, and timing signal 1
The transmission line generation circuit 5 outputs the transmission data signal 109 after performing the signal processing of the common line signal 108 corresponding to 07.

FIG. 3 is a block diagram showing a configuration example of the reception frame synchronization circuit 1. First, a reference pattern (frame synchronization pattern) is set in the shift register 15 in advance, the received signal 101 is captured in the shift register 16, and then the exclusive logic circuit 17 detects a mismatch bit, and the total number thereof is added by an adder. When the total number is smaller than the allowable error bit number ε, the frame detection pulse is output as the reception frame signal 102.

FIG. 4 is a block diagram showing a configuration example of the transmission frame generation circuit 5. A speed conversion circuit 110 for synchronizing the asynchronous common line signal 108 with the transmission frame, a scrambler circuit 111, a convolutional encoder 112 for error correction, a frame synchronization signal, and carrier regeneration in a demodulation board and clock regeneration. Frame sync signal preamble word adder 113 for adding a preamble word
It consists of

[0008]

When the number of VSAT stations in the demand assign multiple access system is small,
Even if the gate time between bursts is set sufficiently to prevent the overlap of in-band data due to the difference in the distance from the VSAT station to the satellite, the line throughput does not decrease much.
When the number of SAT stations is large, the throughput of the line is reduced if sufficient guard time is taken as described above, and the simultaneous command command is sent out-band to the VSAT stations and the response is sent from all VSAT stations. When receiving, it takes a long time until all the responses are returned, which is not practical. Therefore, it is necessary to make the guard time as short as possible, but the arrival time to the satellite differs due to the difference in the distance from the VSAT station to the satellite. Therefore, shortening the guard time causes in-band data to overlap on the satellite and conversely the line throughput. However, there is a problem in that

[0009]

A transmission timing control circuit of the present invention detects a frame period signal periodically inserted in a received signal from a demodulator, obtains a frame period on the receiving side, and obtains its timing. A frame synchronization circuit for outputting a received frame signal, a shift amount control signal for instructing the magnitude of a timing shift given from the outside, and the received frame signal, and the received frame signal according to the shift amount control signal. A variable shift register for delaying and outputting as a counter load signal, and inputting the counter load signal and the transmission clock signal, and counting up the transmission clock signal from an initial value preset according to the counter load signal. An address counter that outputs the count value as an address signal and the address signal that is input Timing ROM for outputting the data stored at the address corresponding to the record as the timing signal
And a transmission frame generation circuit for inputting the timing signal and the common line signal, performing signal processing of the common line signal in response to the timing signal, and outputting as a transmission data signal.

[0010]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Input from a frame synchronization circuit 1 that detects a frame synchronization signal that is periodically inserted in the reception signal 101 from the demodulator, synchronizes the frame on the receiving side, and outputs a reception frame signal 102, and a switch or keyboard. The variable shift register 2 that receives the shifted shift amount control signal 103 and the received frame signal 102, delays the received frame signal 102 according to the shift amount control signal 103, and outputs the delayed frame signal as a counter load signal 104; The transmission clock signal 105 is input, the address counter 3 that counts up from an initial value preset according to the counter load signal 104, and outputs the count value as the address signal 106, and the address signal 106 are input. , The data stored in the corresponding address is A timing frame 4 for outputting as a timing signal 107, a timing signal 107 and a common line signal 108 are input, signal processing of the common line signal 108 is performed corresponding to the timing signal 107, and then a transmission frame is output as a transmission data signal 109. It is composed of a generation circuit 5.

Outband data from the satellite is transmitted to each VSAT.
When transmitted to a station, the amount of delay of out-band received data received by each VSAT station differs depending on the distance from the satellite to the VSAT station.
The time until 2 is detected also differs. After that, the transmission frame generation circuit 5 is started by the counter load signal 104 obtained by delaying the reception frame signal 102 corresponding to the shift amount control signal 103. And each VSAT
Although the station transmits in-band data and reaches the satellite,
After all, the arrival time of in-band data on the satellite varies depending on the difference in the distance from the VSAT station to the satellite. Therefore, the in-band data arriving at the satellite from each VSAT station moves forward or backward with a time difference of twice the delay amount depending on the distance from the VSAT station to the satellite. To deal with this,
The value of the shift amount control signal 103 of the VSAT station farthest to the satellite is set to a minimum, and the value of the shift amount control signal 103 is increased and the counter load signal 104 is delayed as the distance to the satellite becomes shorter. .. By doing so, the intervals between the in-band data that reach the satellite from each VSAT station become substantially uniform, and even if the guard time is made shorter than before, it is possible to prevent the in-band data on the satellite from overlapping, and the stations of the VSAT station can be prevented. Even if the number increases,
It is possible to minimize the decrease in line throughput.

[0013]

As described above, according to the present invention, each V voltage is set by variably setting the load signal of the timing ROM address counter by the variable shift register.
It is possible to prevent the in-band data from overlapping on the satellite due to the difference in the distance from the SAT station to the satellite. As a result, even if the number of VSAT stations increases, it is possible to minimize the decrease in line throughput, and it is possible to provide an economical and stable satellite communication system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional transmission timing control circuit.

FIG. 3 is a block diagram showing a configuration example of a reception frame synchronization circuit in FIG.

4 is a block diagram showing a configuration example of a transmission frame generation circuit in FIG.

FIG. 5 is a network diagram of a demand assign multiple access system in which the present invention and a conventional transmission frame generation circuit are used.

FIG. 6 is a signal format diagram of a common channel in FIG.

[Description of Codes] 1 reception frame synchronization circuit 2 variable shift register 3 address counter 4 timing ROM 5 transmission frame generation circuit 101 reception signal 102 reception frame signal 103 shift amount control signal 104 counter load signal 105 transmission clock signal 106 address signal 107 timing Signal 108 Common line signal 107 Transmission data signal

Claims (1)

[Claims] 1. A frame synchronization circuit for detecting a frame period signal periodically inserted in a received signal from a demodulator, taking a frame period on the receiving side, and outputting a received frame signal indicating its timing, A variable shift register which receives a shift amount control signal for instructing the magnitude of a timing shift given from the outside and the received frame signal, delays the received frame signal according to the shift amount control signal, and outputs the delayed signal as a counter load signal. An address counter for inputting the counter load signal and the transmission clock signal, counting up the transmission clock signal from an initial value preset according to the counter load signal, and outputting the count value as an address signal; Input the address signal and timing the data stored in the corresponding address. Timing RO to output as a signal
M, and a transmission frame generation circuit for inputting the timing signal and the common line signal, performing signal processing of the common line signal in response to the timing signal, and outputting as a transmission data signal. Transmission timing control circuit.