JPH0555468A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0555468A JPH0555468A JP21341491A JP21341491A JPH0555468A JP H0555468 A JPH0555468 A JP H0555468A JP 21341491 A JP21341491 A JP 21341491A JP 21341491 A JP21341491 A JP 21341491A JP H0555468 A JPH0555468 A JP H0555468A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- power supply
- output
- semiconductor device
- outside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置、特に半導体
装置外からの電源を受ける取り入れ部に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an intake portion for receiving power from outside the semiconductor device.
【0002】[0002]
【従来の技術】従来の半導体装置の例を図2に示す。図
2に於いて1は入力回路、2は処理回路、3は出力回
路、VDD3は3に対する電源電位取り入れ部、N03は3に
対する電源電位供給配線、VSS3は3に対する接地電位取
り入れ部、N13は3に対する接地電位供給配線、VDD4は
1と2に共通の電源電位取り入れ部、N04は1と2に共
通の電源電位供給配線、VSS4は1と2に共通の接地電位
取り入れ部、N14は1と2に共通の接地電位供給配線で
ある。電源電位取り入れ部、及び接地電位取り入れ部は
図2に示すように出力回路に対しては独立した1経路が
用意され、入力回路、及び処理回路に対しては共通の電
源電位取り入れ部、及び接地電位取り入れ部から電源が
供給されていた。2. Description of the Related Art An example of a conventional semiconductor device is shown in FIG. In FIG. 2, 1 is an input circuit, 2 is a processing circuit, 3 is an output circuit, VDD3 is a power supply potential intake section for 3, N03 is a power supply potential supply wiring for 3, VSS3 is a ground potential intake section for 3, and N13 is 3. Ground potential supply wiring for VDD4, VDD4 is a common power supply potential supply section for 1 and 2, N04 is a common power supply potential supply wiring for 1 and 2, VSS4 is a common ground potential supply section for N1 and N14 is N1 and 2 Common ground potential supply wiring. As shown in FIG. 2, an independent path for the output circuit is prepared for the power supply potential intake section and the ground potential intake section, and a common power supply potential intake section and ground are provided for the input circuit and the processing circuit. Power was being supplied from the potential intake.
【0003】[0003]
【発明が解決しようとする課題】このような電源供給形
態の場合、処理回路に含まれるセンスアンプ回路、デー
タバスイコライズ回路などから発生するノイズが共通の
電源経路を伝わり入力回路に入り、入力信号の波形に影
響を及ぼし、誤動作を引き起こす原因となっていた。In the case of such a power supply form, noise generated from the sense amplifier circuit, the data bus equalize circuit, etc. included in the processing circuit propagates through the common power supply path and enters the input circuit, and the input signal is inputted. It affected the waveform of and caused a malfunction.
【0004】本発明はかかる点を改善し、処理回路から
発生するノイズの影響を受けることなく、安定した動作
を保証する半導体装置を提供するものである。The present invention has improved these points and provides a semiconductor device which guarantees stable operation without being affected by noise generated from a processing circuit.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置は、
外部からの入力信号を受ける入力回路、外部に出力信号
を出す出力回路、及び該入力回路で受けた信号に基づき
処理を行い該出力回路への出力信号を発生する処理回路
からなる半導体装置において、前記半導体装置外からの
電源を受ける取り入れ部を前記入力回路、出力回路、及
び処理回路に対し別々に設けたことを特徴とする。The semiconductor device of the present invention comprises:
In a semiconductor device comprising an input circuit that receives an input signal from the outside, an output circuit that outputs an output signal to the outside, and a processing circuit that performs processing based on the signal received by the input circuit to generate an output signal to the output circuit, An intake section for receiving power from outside the semiconductor device is separately provided for the input circuit, the output circuit, and the processing circuit.
【0006】[0006]
【作用】本発明の上記構成によれば、処理回路でノイズ
が発生しても入力回路がその影響を受けることはなくな
り、誤動作を防ぐことができる。According to the above configuration of the present invention, even if noise occurs in the processing circuit, the input circuit is not affected by the noise, and malfunctions can be prevented.
【0007】[0007]
【実施例】本発明の実施例を図1に示す。図1に於いて
1は入力回路、2は処理回路、3は出力回路、VDD1は1
に対する電源電位取り入れ部、N01は1に対する電源電
位供給配線、VSS1は1に対する接地電位取り入れ部、N1
1は1に対する接地電位供給配線、VDD2は2に対する電
源電位取り入れ部、N02は2に対する電源電位供給配
線、VSS2は2に対する接地電位取り入れ部、N12は2に
対する接地電位供給配線、VDD3は3に対する電源電位取
り入れ部、N03は3に対する電源電位供給配線、VSS3は
3に対する接地電位取り入れ部、N13は3に対する接地
電位供給配線である。電源電位取り入れ部、及び接地電
位取り入れ部は入力回路、出力回路、及び処理回路のそ
れぞれに対し別々に設けている。FIG. 1 shows an embodiment of the present invention. In FIG. 1, 1 is an input circuit, 2 is a processing circuit, 3 is an output circuit, and VDD1 is 1
N01 is the power supply line for the power supply, N1 is the power supply for N1
1 is a ground potential supply wire for 1, VDD2 is a power supply potential supply part for 2, N02 is a power supply potential supply wire for 2, VSS2 is a ground potential supply part for 2, N12 is a ground potential supply wire for 2, and VDD3 is a power supply for 3. A potential intake portion, N03 is a power supply potential supply wiring for 3, VSS3 is a ground potential intake portion for 3, and N13 is a ground potential supply wiring for 3. The power supply potential intake section and the ground potential intake section are separately provided for each of the input circuit, the output circuit, and the processing circuit.
【0008】[0008]
【発明の効果】本発明によれば、処理回路でノイズが発
生してもその影響を入力回路が受けることはなくなる。According to the present invention, even if noise occurs in the processing circuit, the input circuit is not affected by the noise.
【図1】本発明の実施例を示す回路構成図。FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.
【図2】従来の実施例を示す回路構成図。FIG. 2 is a circuit configuration diagram showing a conventional embodiment.
1 ・・・・ 入力回路 2 ・・・・ 処理回路 3 ・・・・ 出力回路 4 ・・・・ 半導体装置 VDD1 ・・・・ 1に対する電源電位取り入れ部 VDD2 ・・・・ 2に対する電源電位取り入れ部 VDD3 ・・・・ 3に対する電源電位取り入れ部 VDD4 ・・・・ 1と2に共通の電源電位取り入れ部 VSS1 ・・・・ VDD1と対になる接地電位取り入れ部 VSS2 ・・・・ VDD2と対になる接地電位取り入れ部 VSS3 ・・・・ VDD3と対になる接地電位取り入れ部 VSS4 ・・・・ VDD4と対になる接地電位取り入れ部 N01 ・・・・ 1に対する電源電位供給配線 N02 ・・・・ 2に対する電源電位供給配線 N03 ・・・・ 3に対する電源電位供給配線 N04 ・・・・ 1と2に共通の電源電位供給配線 N11 ・・・・ 1に対する接地電位供給配線 N12 ・・・・ 2に対する接地電位供給配線 N13 ・・・・ 3に対する接地電位供給配線 N14 ・・・・ 1と2に共通の接地電位供給配線 1 ・ ・ ・ ・ Input circuit 2 ・ ・ ・ ・ Processing circuit 3 ・ ・ ・ ・ Output circuit 4 ・ ・ ・ ・ Semiconductor device VDD1 ・ ・ ・ ・ Power supply potential intake part for 1 VDD2 ・ ・ ・ ・ Power supply potential intake part for 2 VDD3 ・ ・ ・ ・ Power supply potential intake part for 3 VDD4 ・ ・ ・ ・ Power supply potential intake part common to 1 and 2 VSS1 ・ ・ ・ ・ Ground potential intake part paired with VDD1 VSS2 ・ ・ ・ ・ Paired with VDD2 Ground potential take-in section VSS3 ・ ・ ・ ・ Ground potential take-in section paired with VDD3 VSS4 ・ ・ ・ ・ Ground potential take-in section paired with VDD4 N01 ・ ・ ・ ・ Power supply line for 1 N02 ・ ・ ・ ・ 2 Power supply potential supply wiring N03 ・ ・ ・ Power supply potential supply wiring for 3 N04 ・ ・ ・ Power supply potential supply wiring common to 1 and 2 N11 ・ ・ ・ Ground potential supply wiring for 1 N12 ・ ・ ・ Ground potential for 2 Supply wiring N13 ・ ・ ・ ・Common ground potential supply line to the ground potential supply line N14 · · · · 1 and 2 for
Claims (1)
外部に出力信号を出す出力回路、及び該入力回路で受け
た信号に基づき処理を行い該出力回路への出力信号を発
生する処理回路からなる半導体装置において、前記半導
体装置外からの電源を受ける取り入れ部を前記入力回
路、出力回路、及び処理回路に対し別々に設けたことを
特徴とする半導体装置。1. An input circuit for receiving an input signal from the outside,
In a semiconductor device comprising an output circuit for outputting an output signal to the outside and a processing circuit for performing processing based on the signal received by the input circuit to generate an output signal to the output circuit, receiving a power source from outside the semiconductor device A semiconductor device, wherein parts are separately provided for the input circuit, the output circuit, and the processing circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21341491A JPH0555468A (en) | 1991-08-26 | 1991-08-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21341491A JPH0555468A (en) | 1991-08-26 | 1991-08-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0555468A true JPH0555468A (en) | 1993-03-05 |
Family
ID=16638837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21341491A Pending JPH0555468A (en) | 1991-08-26 | 1991-08-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0555468A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9022801B2 (en) | 2012-08-21 | 2015-05-05 | Dai-Ichi Seiko Co., Ltd. | Electric connector |
US9054438B2 (en) | 2012-07-27 | 2015-06-09 | Dai-Ichi Seiko Co., Ltd. | Connector terminal |
-
1991
- 1991-08-26 JP JP21341491A patent/JPH0555468A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9054438B2 (en) | 2012-07-27 | 2015-06-09 | Dai-Ichi Seiko Co., Ltd. | Connector terminal |
US9022801B2 (en) | 2012-08-21 | 2015-05-05 | Dai-Ichi Seiko Co., Ltd. | Electric connector |
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