JPH0553584A - Signal processing method - Google Patents

Abstract

PURPOSE:To reduce the capacity of a memory by decoding encoded data into blocks consisting of a different number of words from the encoded data and storing the data in the memory whose memory capacity is three times as large as the different number of words. CONSTITUTION:The data encoded by an encoding method which puts, for example, 16 samples in one block has every four samples decoded so that, for example, four sample data can be decoded at a time. Then the decoded data are stored in the buffer RAM which has 12-sample capacity three times as large as, at least, four samples. Then the stored data are read out of the buffer RAM and converted in pitch. The pitch conversion extends over two sections like sections 1 and 2 at a maximum. Therefore, the buffer RAM needs to have only capacity which is large enough for two sections plus one section to be decoded, i.e., three sections consisting of 12 samples.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method for decoding encoded excitation data, for example.

2. Description of the Related Art Generally, sound sources used for electronic musical instruments, TV game machines, etc. are analog sound sources such as VCO, VCA, VCF, etc., and digital sound sources such as PSG (programmable sound generator) and waveform ROM read type. Is roughly divided into As one type of this digital sound source, in recent years, there is a so-called sampler sound source that samples raw musical instrument sounds and digitally processes the data and stores the data in a memory or the like, and reads out a signal of a desired musical instrument from the memory or the like. is there.

In this sampler sound source, since a memory for storing sound source data generally requires a large capacity, various techniques for saving the memory capacity have been proposed. For example, a bit by nonlinear quantization or the like is proposed. Typical examples thereof include compression processing and looping processing using the periodicity of the musical tone signal.

In the bit compression encoding process, the tone signal is compressed and encoded by bit rate reduction (BRR) for reducing the bit rate of the input digital data which is the sound source data, thereby saving the memory.

In the above bit compression encoding processing system,
For example, if 16 blocks are set as one block and the compression range and filter are set in the above block units,
Decoding is also performed by using 16 samples of the compressed data read from the memory as a unit of one block.

The data compressed by the bit compression encoding process as described above is stored in the external memory, and the compressed data read from the external memory is BRR decoded by the digital signal processing (DSP) to obtain the buffer R.
The data is once stored in AM and subjected to arithmetic processing such as pitch conversion.

Here, the pitch conversion is to convert the sampler sound source data read from the memory (buffer RAM) from a signal with a specific pitch for each musical instrument to a signal with a desired pitch. is there.

The above pitch conversion will be described with reference to FIGS. 4 and 5. The compressed data stored in the external memory 22 of FIG. 4 is selected by the sound source selection data. First, the compressed data stored in the external memory 22 will be described with reference to FIG.

FIG. 5 shows an example of output data for one block which is bit-compression-coded and stored in the external RAM 22. The data for one block is composed of 1-byte header information (parameter information or auxiliary information on bit compression) RF and 8-byte sample data D _{A0 to} D _B3 . The header information (adjunct information) RF includes 4-bit range information, 2-bit mode selection information or filter selection information, and two 1-bit flag information, for example, a loop start point in a looping process described later. Information indicating a block (loop start flag LSF)
And information indicating a block at the end point of the loop (loop end flag LEF). Here, the crest value data of one sample is bit-compressed and represented by 4 bits, and 16-sample 4-bit data D _{A0H -D B3L} is included in the data D _A0 -D _B3 . ..

The 8-bit compressed data D _A0 , D _B0 selected by the sound source selection data SRC21 from the external RAM 22 storing the compressed data as described above is a DSP.
Is decoded by the BRR decoder 23 of the buffer RA
Once stored in M24. At the time of sound generation, the decoded sample is read from the buffer RAM 24 according to the pitch height, supplied to the pitch conversion circuit 25, and pitch conversion is performed. The sound source selection data SRC2
1 to 0-25 in the sound source data storage section of the external RAM 22.
The sound source data of various musical instruments such as pianos, saxophones, cymbals, etc., which are stored with the numbers of 5, are designated and selected.

In the calculation processing when a 4-tap FIR filter is used as the pitch conversion circuit 25, the data read from the buffer RAM 24 is converted into, for example, X ₀ , X.
₁ , X ₂ and X ₃ and the filter coefficients of the FIR filter are K ₀ , K ₁ , K ₂ and K ₃ , they are expressed by the following equation. _{X 0 K 0 + X 1 K} 1 + X 2 K 2 + X 3 K 3 = X P above equation X _P is derived from the terminal 26.

The looping process is also a method for continuously producing a sound for a time longer than the original duration of the sampled musical sound. That is, for example, when considering a musical tone signal, the same waveform is repeated at the basic period corresponding to the pitch (pitch, pitch) of the musical tone, except for the formant portion where the periodicity of the waveform is generally unclear immediately after the start of sounding. By appearing, it is possible to obtain a long-lasting sound with a small memory capacity by repeating n cycles (n is an integer) of this repetitive waveform as a looping section and repeatedly reproducing as necessary.

[0012]

Since the pitch conversion filter has 4 taps in the above-described pitch conversion calculation process, the sample may extend over two blocks.
The buffer RAM requires a capacity of 2 blocks, that is, a capacity of 32 samples. In addition, since the number of samples that can be decoded at one time is as small as four samples, it is difficult to manage decoding in block units.

The present invention has been proposed in view of the above situation, and an object thereof is to provide a signal processing method for suppressing the capacity of the buffer RAM to be small.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object, in which data encoded by a predetermined encoding method using a plurality of first words as one block is 1 is decoded for each second plurality different from the plurality of ones, the decoded data is stored in a memory having at least a triple capacity of the second plurality, and the stored data is read from the memory, The predetermined arithmetic processing is performed.

[0015]

According to the present invention, the number of decoded samples (for example, 4 samples) that can manage the decoding of the data encoded by the encoding method in which, for example, 16 samples are used as one block is set. Then, the decoded data of 4 samples per unit is stored in a memory having a capacity three times that of the decoded data. Therefore, the capacity of the memory (buffer RAM) can be reduced by reading the stored data, performing a predetermined signal processing, and then storing the data again every four sample words.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The signal processing method of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a signal processing method according to an embodiment of the present invention. In this embodiment, the pitch of the decoded data read from the buffer RAM is converted.
For example, the four sample data in the section 1 is set as the number of decode samples that can be performed at one time and is set as one unit. Similarly, section 2,
Each 4 samples in the section 3 is set as one unit as the number of decode samples that can be performed once. The unit of the number of decoded samples that can be made once is, for example, QB (quarter block).

Further, in the embodiment of the present invention, since the number of taps of the pitch conversion filter is 4, the pitch conversion covers at least two QBs such as section 1 and section 2 as shown in FIG. Therefore, the capacity of the buffer RAM is 3Q by adding 1QB to be decoded next to the above 2QB.
B, that is, 12 samples are enough.

In FIG. 1, the pitch conversion for four samples extending over the section 1 and the section 2 proceeds to the right side. When a used QB, that is, an empty area indicated by ● or an area immediately after rewriting is formed, a BRR decode sample is filled in the area, and pitch conversion is performed. Thus, the buffer area of the buffer RAM is cyclically used.

Next, the reason why the minimum required capacity of the buffer RAM is set to 12 samples in the signal processing method of the above-described embodiment of the present invention will be described with reference to FIG. Figure 2
Is a model of the state of the buffer RAM when the BRR decode sample is written in the used area by the pitch conversion. In order to make it easier to think, it is assumed that there is a free area in which the decode sample can be written at the beginning of the area. The section 11 in FIG. 2 is a vacant area that can be decoded, and this is defined as the number of decoded samples d per cycle. The portion indicated by t in the section 12 corresponds to the number of taps of the pitch conversion filter. The portion indicated by k extending over the sections 11 and 12 is the number of sample progresses per cycle at the pitch upper limit. The above d, t, and k are variables.
However, as a necessary condition, d is k or more. The case where the capacity of the buffer RAM is most required is when the pointer 13 pointing to the first sample of the pitch conversion filter is at the position P1 and the pitch is at the maximum value. At this time, in the current cycle, the pointer 13 indicating the leading sample is at the position P2. Therefore, the minimum required buffer RAM capacity S _R is represented by d + k + t−1.
In the case of the present embodiment, d = 4, k = 2 ² = 4, t = 4, and therefore the minimum required RAM capacity S _R is 11. However, considering the ease of decoding, the RAM capacity is set to 12 samples.

The configuration of writing decoded data to the buffer RAM to which the signal processing method of the present invention is applied will be described with reference to FIG. DECP1 in FIG. 3 is a pointer that points to the location in the buffer RAM 37 where the decoding result should be placed in the current cycle. The QB 32 is a pointer that points to the first sample for which pitch conversion calculation is performed in the current cycle. DECP above
31 and QB 32 are connected to the comparator 33. The NDEC 34 becomes "H" or "L" according to the comparison result of the comparator 33. The NDEC 34 supplies "H" or "L" as a flag to the AND circuit 35, the AND circuit 40, and the AND circuit 41. The AND circuit 35 includes a WR
The WR pulse is also supplied from the pulse generator 36. The output of the AND circuit 35 is supplied to the buffer RAM 37. The output of the +1 adder 39 is also supplied to the AND circuit 40. The output of the AND circuit 40 is the DECP3
1 is supplied. The DECP 311 is the comparator 3 described above.
In addition to being connected to 3, the +1 adder 33 and the multiplexer (MPX) 35 are also connected. The output of the adder (updater) 12 is also supplied to the AND circuit 41. The output of the AND circuit 31 is the external memory address generation circuit 43.
Is supplied to. The output of the external memory address generation circuit 43 is returned to the adder (updater) 42 while the terminal 4
4 is derived. The MPX45 has the DECP31
Besides, the QB 32 is also connected. The output of the MPX 45 becomes an address signal and is supplied to the buffer RAM 37. When the NDEC 34 is "H", the buffer RAM 37 is instructed to write an address and write by the address signal from the MPX 45 and the WR pulse from the AND circuit 35, and the decoded data is written.

The operation of writing the decoded data to the buffer RAM, to which the signal processing method of the present invention is applied, is shown in FIG.
Will be explained. First, the comparator 33 compares the position indicated by the DECP 31 with the position of the leading sample indicated by the QB 32,
When not in the same block, the NDEC 34 is set to "H", and when not in the same block, the NDEC 34 is set to "L". For example, when the NDEC 34 is “H”, the AND circuit 35 supplies the WR pulse for writing the decoding result to the buffer RAM 7. An address is supplied to the buffer RAM 37 from the MPX 45. Therefore, the buffer RAM 37
The decode data is supplied from the terminal 46, and the decode data is written by the address and the WR pulse. When "H" is supplied from the NDEC 34 to the AND circuit 40, the DECP 31 is updated. Similarly, when "H" is supplied from the NDEC 34 to the AND circuit 41, the counter / pointer for generating the address of the sound source data is updated.

On the other hand, when the NDEC 34 is "L", the writing to the buffer RAM 37 is prohibited, and the DECP 31 and the counter / pointer for generating the addresses of the sound source data are not updated.

As described above, the unit of BRR decoding is set to be smaller than one block, and by using the unit, when pitch conversion is completed and a used portion is formed, the management of filling the decoded sample into the portion is performed next. The capacity of the buffer RAM can be reduced.

[0024]

According to the signal processing method of the present invention, the number of words different from the number of words per block of data in the case of encoding is decoded as one block, and the capacity is three times as large as the number of different words. The capacity of the memory (buffer RAM) can be reduced by having a configuration of a main part that stores data in the memory and performs predetermined arithmetic processing after reading.

[Brief description of drawings]

FIG. 1 is a diagram showing a signal processing method according to an embodiment of the present invention.

FIG. 2 is a model diagram for obtaining a required minimum capacity of a buffer RAM when the signal processing method of the embodiment is executed.

FIG. 3 is a block circuit diagram to which the signal processing method of the embodiment is applied.

FIG. 4 is a block circuit diagram showing an arithmetic circuit for pitch conversion.

FIG. 5 is a schematic diagram showing a specific example of one block of data obtained by bit compression encoding.

Claims (1)

[Claims] 1. The data encoded by a predetermined encoding method using a first plurality of words as one block is decoded for each second plurality different from the first plurality, and at least the decoded data is obtained. Second plurality 3
Store in the memory with double capacity, read the above stored data from the memory,
A signal processing method characterized by performing predetermined arithmetic processing.