JPH0553572A - Effect addition device - Google Patents

Abstract

PURPOSE:To alter a combination of effect given to an input sound signal without altering connection wiring nor requiring any large-capacity memory. CONSTITUTION:This effect addition device is provided with a ROM 2 stored with effect algorithm for adding plural kinds of acoustic effect to an inputted sound signal, algorithm by algorithm, corresponding to the respective kinds of acoustic effect, a ROM 2 stored with combination algorithm for combining the plural kinds of acoustic effect to the inputted sound signal in various forms, a CPU 1 which reads the effect algorithm and combination algorithm out of the ROM 2 according to the combination form of plural kinds of acoustic effect for the inputted sound signal and generates and transfers one program to the CPU 1, and a DSP 4 which adds plural kinds of acoustic effect to the inputted acoustic signal according to the program generated by the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effect adding device for adding a plurality of sound effects to an audio signal input from an electronic musical instrument or the like.

[0002]

2. Description of the Related Art Conventionally, a plurality of acoustic effects such as chorus, delay, etc. have been applied to an acoustic signal input from an electronic musical instrument or the like.
A so-called multi-effector (effect adding device) that imparts reverb and the like has been proposed and put into practical use.

This effector has a plurality of effectors for imparting a single effect and is constituted by connecting a plurality of these effectors serially or in parallel, or is constituted by a DSP, and effect processing is performed on each DSP. By transferring a program that contains multiple algorithms, multiple acoustic effects are obtained.

Further, in recent years, in order to change the mode of the acoustic signal output from the multi-effector, it is attempted to change the manner in which each effect is applied or the number of effects to be applied. Attempts are being made.

This becomes necessary when the atmosphere of musical tones generated by using the above-described multi-effector in an electronic musical instrument is changed (usually, the playing style is changed).

[0006]

However, in such a conventional effect adding device, in the case where a plurality of effectors are connected, in order to give a plurality of acoustic effects, the connecting method is to be changed. It has to be changed, and it is extremely difficult to change the connection method for a plurality of effectors during a performance, and there is a problem that the performance as a multi-effector cannot be fully exhibited.

In this case, for example, it is possible to switch the connection of the effector with a changeover switch or the like during a performance, but there is a drawback that the wiring for that is complicated.

On the other hand, in the case where the multi-effector is constituted by a DSP, it is only necessary to change the program to be input, but it is necessary to have the number of algorithms for changing the combination of each effect processing, which is inevitable. There is a problem in that the capacity of the memory connected to the CPU that controls the DSP (transfers the program) becomes extremely large.

It is therefore an object of the present invention to provide an effect adding device capable of changing the combination of effects applied to an input acoustic signal without changing the connection wiring or requiring a large capacity memory.

[0010]

The effect adding device according to the present invention stores each effect algorithm for adding a plurality of sound effects to an input sound signal in association with each sound effect. Effect algorithm storage means, combination algorithm storage means for storing a combination algorithm for combining a plurality of sound effects in various forms with respect to an input sound signal, and combination of a plurality of sound effects with respect to an input sound signal Depending on the form, the effect algorithm is read from the effect algorithm storage means, the combination algorithm is read from the combination algorithm storage means to create one program, and the program creation means for transferring this program and the program creation means are created. Based on the program Characterized by comprising a effect adding means for adding a plurality of sound effects on the force is the acoustic signal.

[0011]

In the present invention, the effect algorithm and the combination algorithm are stored in advance. For example, when a combination form of a plurality of acoustic effects for an input sound signal is selected from the outside, a plurality of effect algorithms and a combination of the stored effect algorithms are stored. The combination algorithm is read and one program is created. And this program
For example, it is transferred to the DSP, and the DSP executes a process of adding a plurality of sound effects to the input sound signal based on the transferred program.

Therefore, it is not necessary to previously store all combinations of effect forms in the form of programs, the storage capacity is significantly reduced, and the memory capacity is small.

Further, it is not necessary to switch the connection of the effector with a change-over switch or the like during a performance, and the combination of effects to be added to the input audio signal can be changed without changing the connection wiring or a large capacity memory. It becomes possible to do.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram of an embodiment when the effect adding apparatus according to the present invention is applied to an electronic musical instrument. In FIG. 1, reference numeral 1 denotes a CPU (program creating means), and the CPU 1 stores a program stored in the ROM 2 as R
By using AM3 as a work memory, D
Controls SP (Digital signal Proccesor) 4. Further, the CPU 1 scans various switches provided in the switch section 5 and performs a control operation according to changes in the states thereof.

The ROM 2 has a function as an effect algorithm storage means and a combination algorithm storage means,
Each of these algorithms is stored in advance. here,
The effect algorithm is an algorithm for adding a predetermined sound effect (that is, an effect such as reverb) to an input sound signal. Each effect algorithm that adds multiple sound effects is
It is stored for each algorithm in association with each sound effect.

The combination algorithm is an algorithm for combining a plurality of acoustic effects (for example, reverb or chorus) in various forms with respect to an input acoustic signal.

The various switches provided in the switch section 5 are operated to select, for example, one of a plurality of effects or a plurality of effects and a mode in which these effects are appropriately combined. ,
When a certain switch is operated, the corresponding effect is added to the input audio signal.
A control signal is output to PU1.

When the two switches are operated, similarly, a control signal is output so that a plurality of effects corresponding thereto are added in a desired combination form. Further, it is also operated to add one or two of the plurality of effects to the plurality of channel signals.

The CPU 1 determines a combination form of a plurality of effects with respect to an audio signal input based on control signals from various switches provided in the switch section 5, and according to this form, an effect algorithm and The combination algorithm is read out to create one program, and this program is transferred to the DSP 4.

The DSP 4 executes a predetermined operation program put together into one, and is output from an electronic musical instrument (or an audio reproducing device) or the like, and is output from an A / D converter (AD).
C) Add a plurality of acoustic effects to the musical tone signal (or audio reproduction signal, etc., which will be referred to as musical tone signal hereinafter) digitized by 6 and 7. In this case, DS
P4 has a function as an effect adding means and performs an effect adding process based on a program transferred from the CPU 1.

The A / D converter 6 A / D-converts the L-channel signal and the R-channel signal of the tone signals and supplies them to the input terminal IN1 of the DSP 4, and the A / D converter 7 outputs the E-channel signal and the T-channel signal. The channel signal is A / D converted and supplied to the input terminal IN2 of the DSP4.

Digital tone signals to which a plurality of effects have been added in this way are D / A converters (DACs) 8 and 9.
After being converted into an analog signal by, the sound is emitted from a beaker (neither is shown) via an amplifier.

The D / A converter 8 is an output terminal OU of the DSP 4.
D / A conversion of the digital tone signal output from T1, especially the L channel signal and the R channel signal,
The converter 9 D / A-converts the digital tone signal output from the output terminal OUT2 of the DSP 4, particularly the 1-channel signal and 2-channel signal.

Next, FIG. 2 is a diagram showing the internal structure of the DSP 4. In FIG. 2, a program memory 101 is a memory for storing a predetermined microprogram, and outputs a predetermined operation program to the control circuit 102 in accordance with an instruction of one program transferred from the CPU 1 of FIG. At this time, an address counter (not shown) is connected to the program memory 101. Then, the program memory 101 sequentially controls the program contents in accordance with the address instruction from the address counter.
Supply to 2.

The control circuit 102 is a program memory 101.
Based on the output contents of each register, various signals for controlling data transfer and operation between memories and memories, opening / closing control of each gate and latch, and a counter value SC incremented at each sample timing are output to output a desired signal. Perform processing operations.

The coefficient memory (P) 103 is shown in FIG.
1 is a register for storing various coefficients, and these coefficients are read from the RAM 3 of FIG. 1 under the control of the CPU 1 and stored in the coefficient memory (P) 103.

The work memory (W) 104 is shown in FIG.
As shown in FIG. 5, it is a working memory for temporarily saving the waveform signal and the like created in the DSP 4.

The input register (PI1) 121 is A in FIG.
A digital tone signal (L channel signal and R signal) inputted from the D / D converter 6 into the DSP 4 through the input terminal IN1.
Channel signal) and supplies the signal to each unit via the internal bus 123.

Similarly, the input register (PI2) 122 is connected to the input terminal IN2 in the DSP 4 from the A / D converter 7 in FIG.
The digital tone signals (E channel signal and T channel signal) input via the above are stored, and the signals are supplied to each section via the internal bus 123.

Output of the above-mentioned coefficient memory (P) 103, work memory (W) 104, and input register (PI1) 12
1 and the output of the input register (PI2) 122 together with the output from each register described later, the gates 131 to 13
4 is input to the gate terminal, and outputs from the gates 131 to 134 are registers (M0) 141, (M1) 142,
It is input to (A0) 143 and (A1) 144.

Registers (M0) 141, (M1) 142
Stores the data in the middle of calculation supplied to the multiplier 145, and the registers (A0) 143 and (A1) 144 store the data in the middle of calculation supplied to the adder / subtractor 146.

The output of the register (M1) 142 and the output of the register (SR) 153, which will be described later, are applied to the gate 1
The output of the register register (A0) 143 and the output of the register (MR) 150, which will be described later, are input to the adder / subtractor 146 via the gate 148 and further to the register (A1). 14
4 and the output of the register (AR) 151 described later are input to the adder / subtractor 146 via the gate 149.

The adder / subtractor 146 performs addition and subtraction based on an instruction from the control circuit 102, and also performs a process of simply passing data (so-called through process) as necessary.

The multiplication result of the multiplier 145 is stored in the register (M
R) 150, and the output of the register (MR) 150 is supplied to the gate 132 and the gate 148. Further, the calculation result of the adder / subtractor 146 is the register (AR) 15
1 and the output of the register (AR) 151 is supplied to the gate 149 and the register (SR) 153 via the clipper circuit 152.

The clipper circuit 152 is for preventing overflow (digit overflow). Register (S
The output of the R) 153 is supplied to the gate 147, and the internal bus 123 is output as the calculation result of the processing for one sound.
Is stored in the work memory (W) 104 via.

The above calculation result is the work memory (W) 10
4 and the series of processing is completed, the data stored in the memory is transferred to the output register (OR1) 154 and the output register (OR2) 155, and the D / A converter 8 of FIG. 9 are output respectively.

The output register (OR1) 154 stores the L channel signal and the R channel signal, and outputs the same signal to the D channel.
Output to the D / A converter 8 via the output terminal OUT1 in SP4. The output register (OR2) 155 stores the 1-channel signal and the 2-channel signal, and outputs the signal to the D / A converter 9 via the output terminal OUT2 in the DSP 4.

Next, the operation principle of the multi-effect addition of the present invention will be described using this embodiment. FIG. 3 shows the CPU 1.
6 is a flowchart showing a program routine of a multi-effect adding operation executed by In FIG. 3, first, in step S101, the switch section 5 is scanned to determine whether or not the switch section 5 has been operated by an external player (for example, a player of an electronic musical instrument) to add a multi-effect. Captures external information for. Next, in step S102, it is determined whether or not the scanning condition of the switch portion 5 has changed, that is, whether or not the switch portion 5 has been operated by an external player to add a multi-effect. If YES, step S103 The state of the switch unit 5 is indicated by a register (R) in the CPU 1 (not shown).
Store at. On the other hand, if there is no change in the scanning situation (that is, if the switch unit 5 is not operated), the process returns to step S101 and waits.

Next, in step S104, it is determined from the state of the switch section 5 stored in the register (R) whether or not the content of the register (R) is equal to the value A corresponding to the effect addition process (A). The effect adding process (A) shows an example in which a plurality of (two in the present embodiment) effect processes (1) and (2) are combined in a predetermined form with respect to a plurality of channel signals. ..

If YES in step S104, it is determined that execution of the effect addition process (A) is requested from the operating state of the switch section 5, and in step S105, C
Mix processing (1A) from PU1 to DSP4
The programs of (3A), effect processing (1), and (2) are transferred, and the contents of the coefficient memory (A) are transferred.

As a result, the DSP 4 executes a process for performing one effect addition process (A) of a plurality of combinations on the signals of a plurality of channels.

On the other hand, when the contents of the register (R) are not equal to the value A corresponding to the effect addition process (A) from the state of the switch section 5 stored in the register (R) (NO).
When it is), it is determined that execution of other effects is requested, and in step S106, the DSP 4 performs the mix processing (1B) to (3B) and the effect processing (1) and (2). The program is transferred, and the contents of the coefficient memory (B) are transferred as coefficients necessary for the arithmetic processing.

As a result, the processing for adding another one effect form of the plurality of combinations is performed by the DSP.
4 is executed.

Here, each algorithm (effect algorithm) for executing the effect processes (1) and (2)
Is a ROM whose description is long and which can be controlled by the CPU 1 in advance.
Stored in 2. Also, mix processing (1A)
(3A) and mix processing (1B) to (3B) are effect processing (1) for a plurality of channel signals,
This is an algorithm (combining algorithm) for determining how to combine the algorithm of (2) and is also stored in the ROM 2, but the description thereof is relatively short.

Then, for example, when performing the processing of step S105, the algorithm of the effect processing (1) and (2) and the algorithm for determining how to combine these with respect to a plurality of channel signals are used. Certain mix processing (1A) to (3A) is 1 in CPU1
Created in one program and transferred to the DSP 4.

As described above, in the present invention, in order to execute a plurality of effects on a plurality of channel signals (four in this example), each effect processing algorithm (corresponding to an effect algorithm) and this algorithm are An algorithm for combining in various forms (corresponding to a combination algorithm) is stored in advance, and when a selection operation for adding one form of a plurality of effects is performed from the outside, the selection operation is performed. A corresponding program for effect processing and an algorithm for combining the algorithms in various forms are selected to create one program, and the created program is a DSP.
4 is transferred. Then, the DSP 4 executes a process for adding one effect form of a plurality of combination forms.

In this case, all combinations of effect forms are stored in advance in a memory (ROM 2) in the form of a program.
Stored in, and have as many algorithms as possible to change the combination of each effect processing, DSP4
There is no need to change the program to be transferred to the computer (which causes the disadvantage of increasing the storage capacity), and the target to be stored in advance is each effect processing algorithm and the algorithm for combining this algorithm in various forms. Good.

After that, when an external selection operation is performed, an effect processing algorithm and an algorithm for combining the algorithms in various forms are selected, created into one program, and transferred. Good.

Therefore, since it is not necessary to pre-store all combinations of effect forms in the form of programs, the storage capacity can be significantly reduced.
In particular, since each effect processing algorithm has a long description, it is not necessary to store this algorithm in a form that can deal with any combination of effect forms, which is the most important factor for reducing the storage capacity.

Since a plurality of effectors are not connected by hardware, even if a plurality of effects are added, a troublesome operation of changing the connection method for a plurality of effectors during performance. There is no need to do this, and the performance of adding multi-effects can be fully exerted with an extremely simple switch operation.

Further, it is not necessary to perform a process of switching the connection of the effector with a changeover switch or the like during a performance, and there is no drawback that wiring for that is complicated.

As described above, according to the present invention, it is possible to change the combination of effects applied to the input audio signal without changing the connection wiring or requiring a large capacity memory.

FIGS. 4 and 5 are diagrams showing an example of a form of the multi-effect addition processing in the DSP 4 in a pseudo hardware circuit. DS used in the figure
P4 coefficient memory (P) 103 and work memory (W
Each content of E) 104 is shown in FIGS.

First, FIG. 4 shows a first mode in which an effect addition process (A) is added as a multi-effect to four input acoustic signals, that is, an L channel signal, an E channel signal, a T channel signal and an R channel signal. Shows.

In FIG. 4, the E channel signal is divided into two systems by the mix (MIX) processing (1A) 201 and is input to the effect (1) processing 202. The effect (1) process 202 is to add a sound effect such as reverb. Effect (1) processing 20
2, the reverb is added to the E channel signal that has passed through the mix processing (1A) 201, and the mix processing (2
A) It is output to 203.

The contents of the effect (1) processing 202 for adding reverb are well known, and detailed hardware circuits are omitted.

In the mixing process (2A) 203, the T-channel signals are mixed at a predetermined ratio with respect to the two channels of E-channel signals to which reverb is added,
It is output to the effect (2) processing 204. That is,
The E-channel signal of one system to which the reverb is added is guided to the multiplier 205, and the effector (1) shown in FIG.
It is multiplied by the output multiplication coefficient P (EF1) and sent to the adder 206.

The E-channel signal of the other system to which the reverb is added is guided to the multiplier 207, is also multiplied by the effector (1) output multiplication coefficient P (EF1), and is sent to the adder 208.

On the other hand, the T-channel signal is guided to the multiplier 209, multiplied by the T-channel multiplication coefficient P (T), and sent to the adders 206 and 208. In the adder 206, the multiplier 205 outputs the effector (1) output multiplication coefficient P
The E-channel signal of the one system to which the reverb is added adjusted to the ratio determined by (EF1), and the multiplier 20.
9 and the T-channel signal adjusted to the ratio determined by the T-channel multiplication coefficient P (T) are added and output to the effect (2) processing 204.

Further, in the adder 208, the E channel signal of the other system to which the reverb is added adjusted to the ratio determined by the output multiplier coefficient P (EF1) of the effector (1) by the multiplier 207, and the multiplier 209 and the T-channel signal adjusted to the rate determined by the T-channel multiplication coefficient P (T) are added and output to the effect (2) processing 204.

Therefore, 2 with the reverb effect added
The E channel signal and the T channel signal of the system are mixed at a predetermined ratio.

The effect (2) processing 204 is for adding a sound effect such as chorus. In the effect (2) process 204, the chorus effect is added to the two-channel signals that have been subjected to the mix process (2A) 203 and output to the mix process (3A) 210.

The contents of the effect (2) processing 204 for adding the chorus effect are already well known, and detailed hardware circuits are omitted.

In the mixing process (3A) 210, the L-channel signal and the R-channel signal are mixed at a predetermined ratio with respect to the two-channel signals to which the chorus effect is added, and the 1-channel signal, the L-channel signal and the R-channel signal are mixed. Channel signal and 4 of 2 channel signals
It is divided into two and output to the outside of the DSP 4.

That is, the output signal of one system of the effect (2) processing 204 to which the chorus effect is added is guided to the multiplier 211, and the effector (2) output multiplication coefficient P
(FL) is multiplied and sent to the adder 212. Also,
Effect (2) processing 204 with chorus effect added
The output signal of the other system of 1 is guided to the multiplier 213, is also multiplied by the output multiplication coefficient P (FR) of the effector (2), and is sent to the adder 214.

On the other hand, the L channel signal is guided to the multiplier 215 in the mix processing (3A) 210, multiplied by the L channel multiplication coefficient P (PL1), and sent to the adder 212. At the same time, the L channel signal is multiplied by the multiplier 216.
Is output to the outside of the DSP 4 as a 1-channel signal by being multiplied by the L-channel multiplication coefficient P (L1).

In the adder 212, the respective outputs of the multiplier 211 and the multiplier 215 are added, that is, the chorus effect adjusted by the multiplier 211 to the ratio determined by the effector (2) output multiplication coefficient P (FL). The output signal of one system of the added effect (2) processing 204 and the L channel signal adjusted to the ratio determined by the L channel multiplication coefficient P (PL1) by the multiplier 215 are added, and the L channel signal is added. Is output to the outside of the DSP 4.

Similarly, the R channel signal is guided to the multiplier 217 in the mix processing (3A) 210, is multiplied by the R channel multiplication coefficient P (RP1), and is sent to the adder 214. At the same time, the R channel signal is multiplied by the multiplier 218.
Is output to the outside of the DSP 4 as a 2 channel signal.

In the adder 214, the respective outputs of the multiplier 213 and the multiplier 217 are added, that is, the chorus effect adjusted by the multiplier 213 is adjusted to the ratio determined by the effector (2) output multiplication coefficient P (FR). The output signal of the other system of the added effect (2) processing 204 and the R channel signal adjusted to the ratio determined by the R channel multiplication coefficient P (RR1) by the multiplier 217 are added, and the R channel signal is added. Is output to the outside of the DSP 4.

By the above processing, the reverb effect is added to the E channel signal, the signal is mixed with the T channel signal, the chorus effect is added to the mixed signal, and then the L channel signal and the R channel signal are added. It is mixed with the signal and output, and finally again 4 lines (L
(Channel signal, R channel signal, 1 channel signal, and 2 channel signal).

Next, FIG. 5 shows an effect addition process as a multi-effect for the four input acoustic signals, that is, the L channel signal, the E channel signal, the T channel signal and the R channel signal, which is different from the effect addition process (A). The 2nd form which adds (B) is shown.

In FIG. 5, the L channel signal and R channel
Two channels of channel signals are mixed (MIX) processed (1
B) It is mixed by 301 (this is not a mixture but a form in which each system is collected), and both are input to the same effect (1) processing 202 as in FIG. In the effect (1) process 202, a reverb effect is added to the L channel signal and the R channel signal that have been subjected to the mix process (1B) 301, and the mix process (3B) 303 is performed.
Is output to.

The other two systems of the E channel signal and the T channel signal are mixed (MIX) processed (2
B) is mixed by 304 (also in the form of collecting each system instead of mixing) and both are input to the effect (2) processing 204 similar to FIG. In the effect (2) processing 204, a chorus effect is added to the E channel signal and the T channel signal that have been subjected to the mix processing (2B) 304, and the mix processing (3B) 303 is performed.
Is output to.

In the mix processing (3B) 303, the L channel signal of two systems and the R channel to which the reverb effect is added are added.
The original L-channel signal and R-channel signal to which the reverb effect has not been added are mixed at a predetermined ratio with respect to the channel signal, and are mixed and output again to the outside of the DSP 4 as an L-channel signal and an R-channel signal.

The original E-channel signal and the T-channel signal to which the chorus effect has not been added are mixed at a predetermined ratio with respect to the two channels of the E-channel signal and the T-channel signal to which the chorus effect has been added. It is again output to the outside of the DSP 4 as an E channel signal and a T channel signal.

That is, the L channel signal to which the reverb effect has been added is guided to the multiplier 305, multiplied by the effector (1) output multiplication coefficient P (EL) shown in FIG. 16, and sent to the adder 306. The R channel signal to which the reverb effect has been added is guided to the multiplier 307, is also multiplied by the effector (1) output multiplication coefficient P (ER), and is then sent to the adder 308.

On the other hand, the L channel signal is directly fed to the multiplier 3
09, and is multiplied by the L channel multiplication coefficient P (LL2) and sent to the adder 306. In the adder 306,
The multiplier 305 outputs the effector (1) output multiplication coefficient P
The L-channel signal with reverb adjusted to the rate determined by (EL) and the L-channel signal adjusted by the rate determined by the L-channel multiplication coefficient P (LL2) by the multiplier 309 are added. And is again output as an L channel signal to the outside of the DSP 4.

The R channel signal is directly fed to the multiplier 3
It is led to 10, multiplied by the R channel multiplication coefficient P (RR2), and sent to the adder 308. In the adder 308,
Effector (1) output multiplication coefficient P by multiplier 307
The R-channel signal with reverb adjusted to the rate determined by (ER) and the R-channel signal adjusted by the rate determined by the R-channel multiplication coefficient P (RR2) are added by the multiplier 310. And is again output as an R channel signal to the outside of the DSP 4.

Therefore, 2 with the reverb effect added
Original L without reverb effect added to the L channel signal and R channel signal of the system at a predetermined ratio
The channel signal and the R channel signal are respectively mixed and output again as the L channel signal and the R channel signal to the outside of the DSP 4.

Similarly, the E-channel signal to which the chorus effect has been added is guided to the multiplier 311, multiplied by the effector (2) output multiplication coefficient P (F1) shown in FIG. 16, and sent to the adder 312. Further, the T-channel signal to which the chorus effect has been added is guided to the multiplier 313, similarly multiplied by the output multiplication coefficient P (F2) of the effector (2), and sent to the adder 314.

On the other hand, the E channel signal is directly fed to the multiplier 3
It is led to 15, multiplied by the E channel multiplication coefficient P (E1), and sent to the adder 312. In the adder 312, the multiplier 311 outputs the effector (2) output multiplication coefficient P
The E-channel signal with the reverb adjusted to the rate determined by (F1) and the E-channel signal adjusted by the rate determined by the E-channel multiplication coefficient P (E1) by the multiplier 315 are added. Is output to the outside of the DSP 4 as a 1-channel signal.

Further, the T-channel signal is directly fed to the multiplier 3
16 and is multiplied by the T-channel multiplication coefficient P (T2) and sent to the adder 314. In the adder 314, the multiplier 313 outputs the effector (2) output multiplication coefficient P
The T-channel signal with reverb adjusted to the rate determined by (F2) and the T-channel signal adjusted by the rate determined by the T-channel multiplication coefficient P (T2) by the multiplier 316 are added. And is output to the outside of the DSP 4 as a 2-channel signal.

Therefore, the chorus effect added 2
The original E without the reverb effect added to the E channel signal and T channel signal of the system at a predetermined ratio.
The channel signal and the T channel signal are respectively mixed and output again as the E channel signal and the T channel signal to the outside of the DSP 4. After the reverb effect is added to the L-channel signal and the R-channel signal by the above processing, the original L-channel signal and the R-channel signal themselves to which the reverb effect is not added are mixed again and output, Similarly, after the chorus effect is added to the E-channel signal and the T-channel signal in the same manner, the original E-channel signal and the T-channel signal, which are not added with the chorus effect, are mixed again and output. Are again divided into 4 systems (L channel signal, R channel signal, 1 channel signal and 2 channel signal) and output.

Next, the DSP 1 having the configuration shown in FIGS.
The specific operation of No. 2 will be described based on the operation flowcharts of FIGS.

Note that these operations are transferred to the DSP 4 after the effect processing algorithm and the algorithm for combining the algorithms in the form of FIGS. 4 and 5 are selected by the CPU 1 to create one program. In this case, the DSP 4 stores the transfer program in the program memory 101, sequentially fetches it as a micro program, and executes it.

Addresses, names and contents on the memory of coefficients (constants) or variables stored in the coefficient memory (P) 103 or data temporarily stored in the work memory (W) 104. Are shown in FIGS.
As shown in FIG.

FIG. 6 is a main flow of the multi-effect processing, and this flow implements each of these modes in order to explain both the effect addition processing (A) and the effect addition processing (B) described above. It shows with a simple flow.

In FIG. 6, first, in step S201, an input process for taking a tone signal into the DSP 4 is performed.
By this input processing, four input musical tone signals are divided into each channel and taken into the DSP 4.

Next, in step S202, the mix process (1) is performed. This mix processing (1) shows how four multiple channel signals are mixed to add an effect. Specifically, the mix processing (1)
A) 201 or mix processing (1B) 301 is performed.

Next, in step S203, effect processing (1) is performed. By this effect processing (1), the addition of the reverb effect is executed corresponding to the mixing mode of the four plural channel signals.

Next, in step S204, the mix process (2) is performed. This mix process (2) shows how to mix four multiple channel signals to add an effect. Specifically, the mix process (2)
A) 203 or mix processing (2B) 304 is performed.

Next, in step S205, effect processing (2) is performed. By this effect processing (1), the addition of the chorus effect is executed corresponding to the mixing mode of the four plural channel signals.

Next, in step S206, a mix process (3) is performed. Specifically, the mix processing (3A) 21
0 or mix processing (3B) 303 is performed.

Finally, in step S207, output processing for taking out the musical tone signal subjected to the multi-effect processing from the DSP 4 to the outside is performed. By this output processing,
The four output tone signals that have undergone the multi-effect processing are divided into respective channels and taken out from the DSP 4. Details of each processing described above are shown in each drawing after FIG. 7, and detailed processing contents will be described next.

FIG. 7 shows details of the input process (step S201). In FIG. 7, first, step S3
The tone signal taken into the input register (PI1) 121 at 01 is stored in the work memory (W) 104 as L channel input data W (INL). Next, in step S302, the musical tone signal taken into the input register (PI2) 122 is stored in the work memory (W) 104 as the R channel input data W (INR).

Similarly, the musical tone signal taken in the input register (PI1) 121 in step S303 is used as the T channel input data W (INT) in the work memory (W) 1.
04, and the input register (PI
2) The tone signal taken in by 122 is stored in the work memory (W) 104 as E channel input data W (INE). In this way, the input data of each channel is stored in the corresponding address of the work memory (W) 104.

8 to 10 show the mix processing (1A),
It shows the details of (2A) and (3A), of which FIG. 8 shows the mix processing (1A).

In FIG. 8, first, in step S401, the E channel input data W is read from the work memory (W) 104.
(INE) is stored in the read register (A0) 143. Next, in step S402, the register (A0) 14
The input data W (INE) stored in No. 3 is sequentially passed through the gate 148 and the adder / subtractor 146 to the register (AR) 15
Move to 1.

Then, in step S402, the register (A
The input data W (INE) transferred to the R) 151 is stored in the register (SR) 153 through the clipper circuit 152, and the input data W (INE) stored in the register (A0) 143 is further stored in the gate 148 and the adder / subtractor 146. Are sequentially transferred again to the register (AR) 151.

Then, in step S403, the register (A
R) Another input data W (INE) transferred to 151
Through the clipper circuit 152 to the register (SR) 153
To the previous data SR stored in the register (SR) 153 (that is, the first input data W (IN
E)) is stored as the effector (1) input channel data W (EI1) at the corresponding address of the work memory (W) 104 via the internal bus 123.

Similarly, in the same step S403, the (other) input data W (INE) after being transferred to the register (AR) 151 is stored in the register (SR) 153 through the clipper circuit 152. Then, step S404
Data SR after stored in register (SR) 153 at
(That is, the subsequent input data W (INE)) is stored as the effector (1) input channel data W (EI1) in the corresponding address of the work memory (W) 104 via the internal bus 123.

As a result, the mix processing of FIG. 4 (1A)
A function equivalent to 201 is realized. FIG. 9 shows details of the mix processing (2A). In FIG. 9, first, in step S501, the effector (1) output multiplication coefficient P (EF1) is read from the coefficient memory (P) 103 and stored in the register (M0) 141, and the effector (1) is read from the work memory (W) 104. The output channel data W (EO1) is read and stored in the register (M1) 142.

Then, in step S502, the register (M
0) The effector (1) output multiplication coefficient P (EF1) set to 141 is supplied to the multiplier 145, and the effector (1) output channel data W (EO1) set to the register (M1) 142 is supplied via the gate 147. And supplies it to the multiplier 145. Then, both are multiplied by the multiplier 145.
In the register (MR) 15
Store in 0. As a result, processing equivalent to the function of the multiplier 205 in FIG. 4 is realized.

At the same step S502, the T-channel multiplication coefficient P (T) is read from the coefficient memory (P) 103 and stored in the register (M0) 141, and the T-channel input data W from the work memory (W) 104 is read.
(INT) is read and stored in the register (M1) 142.

Then, in step S503, the register (M
The calculation result of the multiplier 145 stored in the R) 150 is sequentially passed through the gate 148 and the adder / subtractor 146 to be transferred to the register (AR) 151, and the previous step S502.
The T-channel multiplication coefficient P (T) set in the register (M0) 141 is supplied to the multiplier 145, and the T-channel input data W (INT) set in the register (M1) 142 is supplied via the gate 147. 145
Supply to. Then, the both are multiplied by the multiplier 145, and the calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 209 in FIG. 4 is realized.

In step S504, the register (AR)
The operation result of the multiplier 145 transferred to 151 is transferred to the gate 149.
Is supplied to one input terminal of the adder / subtractor 146 via the
503 calculation result (that is, T channel multiplication coefficient P
(T) and the calculation result of the T channel input data W (INT)) are supplied to the other input terminal of the adder / subtractor 146 via the gate 148, both are added by the adder / subtractor 146, and the result is registered (AR). It is stored in 151. As a result, processing equivalent to the function of the adder 206 shown in FIG. 4 is realized.

In the same step S504, the same process as part of step S503 is performed again, that is, the T-channel multiplication coefficient P set in the register (M0) 141.
(T) is supplied to the multiplier 145, and T channel input data W set in the register (M1) 142
After (INT) is supplied to the multiplier 145 via the gate 147, both are multiplied by the multiplier 145 and the calculation result is stored in the register (MR) 150.

Further, in the same step S504, the effector (1) output multiplication coefficient P is output from the coefficient memory (P) 103.
(EF1) is read out and stored in the register (M0) 141, and at the same time, the effector (1) output channel data W (EO2) is read out from the work memory (W) 104 and stored in the register (M1) 142.

Then, in step S505, the register (A
The calculation result of the adder / subtractor 146 stored in R) 151 is stored in the register (SR) 153 through the clipper circuit 152, and the calculation result of step S504 stored in the register (MR) 150 (that is, T channel multiplication coefficient P (T ) And the T channel input data W (INT) calculation result) are sequentially passed through the gate 148 and the adder / subtractor 146 and transferred to the register (AR) 151.

Further, the effector (1) output multiplication coefficient P (EF1) set in the register (M0) 141 in the previous step S504 is supplied to the multiplier 145, and
Effector (1) set in register (M1) 142
The output channel data W (EO2) is supplied to the multiplier 145 via the gate 147. Then, multiply both by the multiplier 1
Multiply by 45 and register the operation result in the register (MR)
Store in 150. As a result, processing equivalent to the function of the multiplier 207 in FIG. 4 is realized.

Then, in step S506, the register (S
R) 153 stores the data stored in the effector (2) input channel data (1) W (EI) via the internal bus 123.
As 1), it is stored in the corresponding address of the work memory (W) 104.

Further, the calculation result of step S505 stored in the register (MR) 150 at the same step S506 (that is, effector (1) output multiplication coefficient P (EF)
1) and effector (1) output channel data W (EO
The calculation result of 2)) is added via the gate 148 to the adder / subtractor 14
6 to one input terminal of the register (A
R) 151, the calculation result of the multiplier 145 (that is, the calculation result of the T channel multiplication coefficient P (T) and the T channel input data W (INT)) is input to the other input terminal of the adder / subtractor 146 via the gate 149. To the adder / subtractor 146 and add the result to the register (AR) 1
It stores in 51. As a result, processing equivalent to the function of the adder 208 in FIG. 4 is realized.

Subsequently, in step S507, the register (A
The calculation result of the adder / subtractor 146 stored in R) 151 is stored in the register (SR) 153 through the clipper circuit 152, and the register (SR) 1 is stored in step S508.
The data stored in 53 is stored in the corresponding address of the work memory (W) 104 as the effector (2) input channel data (2) W (FI2) via the internal bus 123.

As a result, the mix processing of FIG. 4 (2A)
A function equivalent to 203 is realized. FIG. 10 shows details of the mix processing (3A). In FIG.
First, in step S601, the coefficient memory (P) 103 to L
The channel multiplication coefficient P (PL1) is read out and stored in the register (M0) 141, and at the same time, the L channel input data W (INL) from the work memory (W) 104 is read.
Is stored in the register (M1) 142.

Then, in step S602, the register (M
0) 141 L multiplication coefficient P (PL
1) is supplied to the multiplier 145 and the register (M
1) L channel input data W (I
NL) is supplied to the multiplier 145 via the gate 147. Then, the both are multiplied by the multiplier 145, and the calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 216 in FIG. 4 is realized.

Further, in the same step S602, the L channel multiplication coefficient P (PLL1) is output from the coefficient memory (P) 103.
Is read and stored in the register (M0) 141.

Then, in step S603, the register (M
The calculation result of the multiplier 145 stored in the R) 150 is sequentially passed through the gate 148 and the adder / subtractor 146 and transferred to the register (AR) 151.

Similarly, in step S603, the register (M
0) 141 L multiplication coefficient P (PL
L1) is supplied to the multiplier 145, and L channel input data W set in the register (M1) 142 is supplied.
(INL) is supplied to the multiplier 145 via the gate 147. Then, the both are multiplied by the multiplier 145, and the calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 215 in FIG. 4 is realized.

In the same step S603, the coefficient memory (P) 103 outputs the effector (2) output multiplication coefficient P (F
L) is read out and stored in the register (M0) 141, and the effector (1) output channel data (1) W (FO1) is read out from the work memory (W) 104 and stored in the register (M1) 142.

In step S604, the register (AR)
The calculation result of the multiplier 145 stored in 151 is stored in the register (SR) 153 through the clipper circuit 152.
The data stored in the register (SR) 153 will be stored in the corresponding address of the work memory (W) 104 as the 1-channel output data W (OT1) via the internal bus 123 in the next step S605. After that, the data stored in the work memory (W) 104 is taken out by the output processing described later. As a result, a process equivalent to the function of extracting the output from the multiplier 216 of FIG. 4 is realized.

Similarly, in step S604, the calculation result of the multiplier 145 stored in the register (MR) 150 (that is, the multiplication result of the L channel multiplication coefficient P (PLL1) and the L channel input data W (INL)) is applied to the gate 1.
48 and the adder / subtractor 146 are sequentially passed through and transferred to the register (AR) 151.

Further, the multiplier 1 sets the output multiplication coefficient P (FL) of the effector (2) set in the register (M0) 141.
45, and the effector (1) output channel data (1) set in the register (M1) 142.
W (FO1) is supplied to the multiplier 145 via the gate 147. Then, both are multiplied by the multiplier 145,
The calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 211 in FIG. 4 is realized.

Further, in the same step S604, the R channel multiplication coefficient P (R1) is read from the coefficient memory (P) 103 and stored in the register (M0) 141, and the R channel input data W (from the work memory (W) 104 is read. Read out INR and register (M1) 142
To store.

Then, the process proceeds to step S605, and the data stored in the register (SR) 153 as described above is transferred to the 1-channel output data W via the internal bus 123.
(OT1) is stored in the corresponding address of the work memory (W) 104.

After that, the calculation result of step S604 stored in the register (MR) 150 (that is, the calculation result of the effector (2) output multiplication coefficient P (FL) and the effector (1) output channel data (1) W (FO1). ) Is supplied to one input terminal of the adder / subtractor 146 via the gate 148, and is transferred to the register (AR) 151 by the operation result of the multiplier 145 (that is, the L channel multiplication coefficient P (PLL1) and the L channel input data). W (IN
The calculation result of (L) is added via the gate 149 to the adder / subtractor 14
It is supplied to the other input terminal of 6, and both are added by the adder / subtractor 146, and the result is stored in the register (AR) 151. As a result, processing equivalent to the function of the adder 212 in FIG. 4 is realized.

The R channel multiplication coefficient P (R1) set in the register (M0) 141 is supplied to the multiplier 145, and the R channel input data W (INR) set in the register (M1) 142 is supplied to the gate 147. It is supplied to the multiplier 145 via Then, both are multiplied by the multiplier 145, and the calculation result is registered in the register (M
R) 150. As a result, the multiplier 21 of FIG.
A process equivalent to the function of 8 is realized.

Further, in the same step S605, the R channel multiplication coefficient P (RR1) is calculated from the coefficient memory (P) 103.
Is read and stored in the register (M0) 141.

In step S606, the register (AR)
The calculation result of the multiplier 145 stored in 151 is stored in the register (SR) 153 through the clipper circuit 152.
This data stored in the register (SR) 153 will be stored in the corresponding address of the work memory (W) 104 as the L channel output data W (OTL) via the internal bus 123 in the next step S607. After that, the data stored in the work memory (W) 104 is taken out by the output processing described later. As a result, a process equivalent to the function of extracting the output from the multiplier 212 of FIG. 4 is realized.

Similarly, in step S606, the calculation result of the multiplier 145 stored in the register (MR) 150 (that is, the multiplication result of the R channel multiplication coefficient P (R1) and the R channel input data W (INR)) is output to the gate 148.
And the adder / subtractor 146 are sequentially passed through to register (A
R) Move to 151.

The R channel multiplication coefficient P (RR1) set in the register (M0) 141 is supplied to the multiplier 145, and the R channel input data W (INR) set in the register (M1) 142 is supplied to the gate 147.
To the multiplier 145. Then, both are multiplied by the multiplier 145, and the calculation result is registered in the register (M
R) 150. As a result, the multiplier 21 of FIG.
Processing equivalent to the function of 7 is realized.

Further, in the same step S606, the coefficient memory (P) 103 outputs the effector (2) output multiplication coefficient P (F
R) is read out and stored in the register (M0) 141, and the effector (2) output channel data (2) W (FO2) is read out from the work memory (W) 104 and stored in the register (M1) 142.

Then, the process proceeds to step S607, and the data stored in the register (SR) 153 as described above is first transferred to the L channel output data W via the internal bus 123.
(OTL) is stored in the corresponding address of the work memory (W) 104.

After that, the calculation result of the multiplier 145 stored in the register (AR) 151 is stored in the register (SR) 153 through the clipper circuit 152. The data stored in the register (SR) 153 is transferred to the work memory (W) 10 as the 2 channel output data W (OT2) via the internal bus 123 in the next step S608.
4 will be stored in the corresponding address, and thereafter, the data stored in the work memory (W) 104 will be taken out by the output processing described later. As a result, processing equivalent to the function of extracting the output from the multiplier 218 of FIG. 4 is realized.

Similarly, in step S607, the gate 14 receives the calculation result of the multiplier 145 stored in the register (MR) 150 (that is, the multiplication result of the R channel multiplication coefficient P (RR1) and the R channel input data W (INR)).
8 and the adder / subtractor 146 are sequentially passed through to register (A
R) Move to 151.

Further, the multiplier 1 outputs the output multiplication coefficient P (FR) of the effector (2) set in the register (M0) 141.
45, and the effector (2) output channel data (2) set in the register (M1) 142.
W (FO2) is supplied to the multiplier 145 via the gate 147. Then, both are multiplied by the multiplier 145,
The calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 213 in FIG. 4 is realized.

Then, the process proceeds to step S608, in which the data stored in the register (SR) 153 as described above is transferred to the 2-channel output data W via the internal bus 123.
(OT2) is stored in the corresponding address of the work memory (W) 104.

Subsequently, the calculation result of step S607 stored in the register (MR) 150 (that is, calculation of the effector (2) output multiplication coefficient P (FR) and the effector (2) output channel data (2) W (FO2)). The result is supplied to one input terminal of the adder / subtractor 146 via the gate 148, and the operation result of the multiplier 145 transferred to the register (AR) 151 (that is, the R channel multiplication coefficient P (RR1) and the R channel input). Data W (INR)
Is supplied to the other input terminal of the adder / subtractor 146 via the gate 149, both are added by the adder / subtractor 146, and the result is stored in the register (AR) 151. As a result, processing equivalent to the function of the adder 214 in FIG. 4 is realized.

Then, in step S609, the register (A
The calculation result of the multiplier 145 stored in the R) 151 is stored in the register (SR) 153 through the clipper circuit 152. Next, in step S610, the register (SR) 15
The data stored in No. 3 as work channel (W) as R channel output data W (OTR) via the internal bus 123.
It is stored in the corresponding address of 104.

The data stored in the work memory (W) 104 is taken out by the output processing described later. As a result, processing equivalent to the function of extracting the output from the multiplier 214 in FIG. 4 is realized. With the above processing, a function equivalent to the mix processing (3A) 210 of FIG. 4 is realized.

Next, FIGS. 11 to 13 show the mix processing (1
B), mix processing (2B) and mix processing (3
FIG. 11 shows the details of B), of which FIG. 11 shows the mix processing (1B).

In FIG. 11, first, in step S701, the L channel input data W (INL) from the work memory (W) 104 is stored in the read register (A0) 143. Next, in step S702, the register (A0) 1
The input data W (INL) stored in 43 is transferred to the gate 148.
And the register (AR) 1 via the adder / subtractor 146 sequentially
Move to 51.

Further, in the same step S702, the R channel input data W (IN
R) is stored in the read register (A0) 143.

Then, in step S703, the register (A
R) input data W (IN
L) through the clipper circuit 152 to the register (SR) 1
53, and further register (A0) 14
The R channel input data W (INR) stored in No. 3 is sequentially transferred to the register (AR) 151 via the gate 148 and the adder / subtractor 146.

Then, in step S704, the register (S
R) the previous data SR stored in 153 (that is, the first L channel input data W (INL)) is transferred to the internal bus 1
The data is stored in the work memory (W) 104 at a corresponding address as the effector (1) input channel data (1) W (EI1) via 23.

Similarly, the R channel input data W after being transferred to the register (AR) 151 in the previous step S703.
(INR) through the clipper circuit 152 to the register (S
R) 153.

Then, in step S705, the register (S
R) data SR stored in 153 (that is, R channel input data W (INR)) via the internal bus 123 to the effector (1) input channel data (2) W.
(EI2) is stored in the corresponding address of the work memory (W) 104.

As a result, the mix processing of FIG. 5 (1B)
A function equivalent to 301 is realized. FIG. 12 shows details of the mix processing (2B). In FIG.
First, in step S801, the E channel input data W (INE) is read from the work memory (W) 104 and stored in the register (A0) 143. Then, step S80
Input data W stored in register (A0) 143 in 2
(INE) is sequentially transferred to the register (AR) 151 through the gate 148 and the adder / subtractor 146.

In the same step S702, the T channel input data W (IN
T) is stored in the read register (A0) 143.

Then, in step S703, the register (A
R) E channel input data W (IN
E) through the clipper circuit 152 to register (SR) 1
53, and further register (A0) 14
The T channel input data W (INT) stored in No. 3 is sequentially transferred to the register (AR) 151 via the gate 148 and the adder / subtractor 146.

Then, in step S804, the register (S
R) the previous data SR stored in 153 (that is, the first E-channel input data W (INE)) is transferred to the internal bus 1
The data is stored as the effector (2) input channel data (1) W (FI 1) at a corresponding address of the work memory (W) 104 via 23.

Similarly, the T channel input data W after being transferred to the register (AR) 151 in the previous step S803.
(INT) through the clipper circuit 152 to the register (S
R) 153.

Then, in step S805, the register (S
R) 153 after storing the data SR (that is, T channel input data W (INT)) via the internal bus 123 into the effector (2) input channel data (2) W.
(FI2) is stored in the corresponding address of the work memory (W) 104.

As a result, the mix processing of FIG. 5 (2B)
A function equivalent to 304 is realized. FIG. 13 shows details of the mix processing (3B). In FIG.
First, in step S901, the coefficient memory (P) 103 to L
The channel multiplication coefficient P (LL2) is read out and stored in the register (M0) 141, and the L channel input data W (INL) from the work memory (W) 104 is read.
Is stored in the register (M1) 142.

Then, in step S902, the register (M
0) L channel multiplication coefficient P (LL set to 141)
2) is supplied to the multiplier 145 and the register (M
1) L channel input data W (I
NL) is supplied to the multiplier 145 via the gate 147. Then, the both are multiplied by the multiplier 145, and the calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 309 in FIG. 5 is realized.

Further, in the same step S902, the effector (1) output multiplication coefficient P (E) is output from the coefficient memory (P) 103.
L) is read out and stored in the register (M0) 141, and at the same time, the effector (1) output channel data (1) W (EO1) is read out from the work memory (W) 104 and stored in the register (M1) 142.

Then, in step S903, the register (M
The calculation result of the multiplier 145 stored in the R) 150 is sequentially passed through the gate 148 and the adder / subtractor 146 and transferred to the register (AR) 151.

Similarly, in step S903, the register (M
0) The effector (1) output multiplication coefficient P (EL) set to 141 is supplied to the multiplier 145, and the effector (1) output channel data (1) W (EO1) set to the register (M1) 142 is gated. It is supplied to the multiplier 145 via 147. Then, multiply both by the multiplier 1
Multiply by 45 and register the operation result in the register (MR)
Store in 150. As a result, processing equivalent to the function of the multiplier 305 in FIG. 5 is realized.

In the same step S903, the R channel multiplication coefficient P (RR2) is read from the coefficient memory (P) 103 and stored in the register (M0) 141, and the R channel input data W (from the work memory (W) 104 is read. Read out INR and register (M1) 142
To store.

Next, in step S904, the data (that is, the multiplication result of the L channel multiplication coefficient P (LL2) and the L channel input data W (INL)) first moved to the register (AR) 151 is passed through the gate 148. The calculation result of the multiplier 145 stored in the register (MR) 150 (that is, the effector (1) output multiplication coefficient P (E) is supplied to one input terminal of the adder / subtractor 146).
L) and effector (1) output channel data (1) W
(Operation result of (EO1)) is supplied to the other input terminal of the adder / subtractor 146 via the gate 149, and both are added / subtractor 1
The value is added at 46 and the result is stored in the register (AR) 151. As a result, processing equivalent to the function of the adder 306 in FIG. 5 is realized.

Similarly, in step S904, the register (M
0) R channel multiplication coefficient P (RR set to 141)
2) is supplied to the multiplier 145 and the register (M
1) R channel input data W (I
NR) is supplied to the multiplier 145 via the gate 147. Then, the both are multiplied by the multiplier 145, and the calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 310 in FIG. 5 is realized.

Further, in the same step S904, the effector (1) output multiplication coefficient P (E) is output from the coefficient memory (P) 103.
R) is read out and stored in the register (M0) 141, and the effector (1) output channel data (2) W (EO2) is read out from the work memory (W) 104 and stored in the register (M1) 142.

Then, the process proceeds to step S905, and first, the data stored in the register (AR) 151 (that is, the effector (1) output multiplication coefficient P (EL) and the effector (1) output channel data (1) W (EO1) The addition result) is passed through the clipper circuit 152 to the register (SR)
153.

The data stored in the register (SR) 153 is the L channel output data W (OTL) via the internal bus 123 in step S906 described later.
Will be stored in the corresponding address of the work memory (W) 104, and thereafter, the data stored in the work memory (W) 104 will be taken out by the output processing described later. As a result, FIG.
A process equivalent to the function of taking out the output from the multiplier 306 is realized.

Similarly, in step S905, the calculation result of the multiplier 145 (that is, the multiplication result of the R channel multiplication coefficient P (RR2) and the R channel input data W (INR)) stored in the register (MR) 150 is stored in the gate 14.
8 and the adder / subtractor 146 are sequentially passed through to register (A
R) Move to 151.

The multiplier (1) outputs the output multiplication coefficient P (ER) set in the register (M0) 141.
Effector (1) output channel data (2) set in register (M1) 142 while being supplied to
W (EO2) is supplied to the multiplier 145 via the gate 147. Then, both are multiplied by the multiplier 145,
The calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 307 in FIG. 5 is realized.

Further, in the same step S905, the E-channel multiplication coefficient P (E1) is read from the coefficient memory (P) 103 and stored in the register (M0) 141, and the E-channel input data W (from the work memory (W) 104 is read. INE) is read and the register (M1) 142 is read.
To store.

Then, the process proceeds to step S906, and the data stored in the register (SR) 153 as described above is first output through the internal bus 123 to the 1-channel output data W.
(OTL) is stored in the corresponding address of the work memory (W) 104.

Thereafter, the calculation result of step S905 stored in the register (MR) 150 (ie, the calculation result of the effector (1) output multiplication coefficient P (ER) and the effector (1) output channel data (2) W (EO2)). ) Is supplied to one input terminal of the adder / subtractor 146 via the gate 148, and is transferred to the register (AR) 151 by the operation result of the multiplier 145 (that is, R channel multiplication coefficient P (RR2) and R channel input data). W (INR)
(Multiplication result of) is supplied to the other input terminal of the adder / subtractor 146 via the gate 149, both are added by the adder / subtractor 146, and the result is stored in the register (AR) 151. As a result, processing equivalent to the function of the adder 308 in FIG. 5 is realized.

Further, in the same step S906, the coefficient memory (P) 103 outputs the effector (2) output multiplication coefficient P (F
1) is read out and stored in the register (M0) 141, and the effector (2) output channel data (1) W (FO1) is read out from the work memory (W) 104 and stored in the register (M1) 142.

In step S907, the register (AR)
The calculation result of the multiplier 145 stored in 151 is stored in the register (SR) 153 through the clipper circuit 152.
The data stored in the register (SR) 153 will be stored in the corresponding address of the work memory (W) 104 as the R channel output data W (OTR) via the internal bus 123 in the next step S908. After that, the data stored in the work memory (W) 104 is taken out by the output processing described later. As a result, a process equivalent to the function of extracting the output from the multiplier 308 of FIG. 5 is realized.

Similarly, in step S907, the gate 148 stores the calculation result of the multiplier 145 stored in the register (MR) 150 (that is, the multiplication result of the E channel multiplication coefficient P (E1) and the E channel input data W (INE)).
And the adder / subtractor 146 are sequentially passed through to register (A
R) Move to 151.

Further, the multiplier 1 outputs the effector (2) output multiplication coefficient P (F1) set in the register (M0) 141.
45, and the output channel data (1) of the effector (2) set in the register (M1) 142.
W (FO1) is supplied to the multiplier 145 via the gate 147. Then, both are multiplied by the multiplier 145,
The calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 311 in FIG. 5 is realized.

Further, in the same step S907, the T-channel multiplication coefficient P (T2) is read from the coefficient memory (P) 103 and stored in the register (M0) 141, and the T-channel input data W (from the work memory (W) 104 is read. INT) is read and the register (M1) 142 is read.
To store.

Then, the flow shifts to step S908, where the data stored in the register (SR) 153 as described above is transferred to the R channel output data W via the internal bus 123.
(OTR) is stored in the corresponding address of the work memory (W) 104.

Thereafter, the calculation result of step S907 stored in the register (MR) 150 (that is, the calculation result of the effector (2) output multiplication coefficient P (F1) and the effector (2) output channel data (1) W (FO1). ) Is supplied to one input terminal of the adder / subtractor 146 via the gate 148, and is transferred to the register (AR) 151 by the operation result of the multiplier 145 (that is, the E channel multiplication coefficient P (E1) and the E channel input data). The calculation result of W (INE) is supplied to the other input terminal of the adder / subtractor 146 via the gate 149, both are added by the adder / subtractor 146, and the result is stored in the register (AR) 151. As a result, processing equivalent to the function of the adder 312 in FIG. 5 is realized.

The T-channel multiplication coefficient P (T2) set in the register (M0) 141 is supplied to the multiplier 145, and the T-channel input data W (INT) set in the register (M1) 142 is supplied to the gate 147. It is supplied to the multiplier 145 via Then, both are multiplied by the multiplier 145, and the calculation result is registered in the register (M
R) 150. As a result, the multiplier 31 of FIG.
A process equivalent to the function of 6 is realized.

Furthermore, in the same step S908, the coefficient memory (P) 103 outputs the effector (2) output multiplication coefficient P.
(F2) is read and stored in the register (M0) 141, and at the same time, the effector (2) output channel data (2) W (FO2) is read from the work memory (W) 104 and stored in the register (M1) 142.

In step S909, the register (AR)
The calculation result of the multiplier 145 stored in 151 is stored in the register (SR) 153 through the clipper circuit 152.
This data stored in the register (SR) 153 will be stored in the corresponding address of the work memory (W) 104 as the 1-channel output data W (OT1) via the internal bus 123 in the next step S910. After that, the data stored in the work memory (W) 104 is taken out by the output processing described later. As a result, a process equivalent to the function of extracting the output from the multiplier 312 of FIG. 5 is realized.

Similarly, in step S909, the gate 148 stores the calculation result of the multiplier 145 stored in the register (MR) 150 (that is, the multiplication result of the T channel multiplication coefficient P (T2) and the T channel input data W (INT)).
And the adder / subtractor 146 are sequentially passed through to register (A
R) Move to 151.

Further, the multiplier 1 outputs the output multiplication coefficient P (F2) of the effector (2) set in the register (M0) 141.
45, and the effector (2) output channel data (2) set in the register (M1) 142.
W (FO2) is supplied to the multiplier 145 via the gate 147. Then, both are multiplied by the multiplier 145,
The calculation result is stored in the register (MR) 150. As a result, processing equivalent to the function of the multiplier 313 in FIG. 5 is realized.

Then, the process proceeds to step S910, and the data stored in the register (SR) 153 as described above is first output through the internal bus 123 to the 1-channel output data W.
(OT1) is stored in the corresponding address of the work memory (W) 104.

After that, the calculation result of step S909 stored in the register (MR) 150 (that is, the calculation result of the effector (2) output multiplication coefficient P (F2) and the effector (2) output channel data (2) W (FO2)). ) Is supplied to one input terminal of the adder / subtractor 146 via the gate 148 and is transferred to the register (AR) 151 by the operation result of the multiplier 145 (that is, T channel multiplication coefficient P (T2) and T channel input data). The multiplication result of W (INT) is supplied to the other input terminal of the adder / subtractor 146 via the gate 149, both are added by the adder / subtractor 146, and the result is stored in the register (AR) 151. As a result, processing equivalent to the function of the adder 314 in FIG. 5 is realized.

Then, in step S911, the register (A
R) 151, the addition result of the adder / subtractor 146 is stored in the register (SR) 153 through the clipper circuit 152, and the data stored in the register (SR) 153 in step S912 is transferred to the 2-channel output data W via the internal bus 123. (OT2) is stored in the corresponding address of the work memory (W) 104.

The data stored in the work memory (W) 104 is taken out to the outside by the output processing described later. As a result, processing equivalent to the function of extracting the output from the adder 314 of FIG. 5 is realized. With the above processing, a function equivalent to the mix processing (3B) 303 in FIG. 5 is realized.

FIG. 14 shows the details of the output process (step S206). In FIG. 14, first, in step S1001, the L channel output data W (OTL) is read from the work memory (W) 104 and stored in the output register (OR1) 154, and this data is read from the register to the D / A converter of FIG. Output to 8. As a result, FIG.
A process equivalent to the function of extracting the output from the multiplier 214 of FIG. 5 and the multiplier 312 of FIG. 5 is realized.

Then, in step S1002, the R channel output data W (OT
R) is read and stored in the output register (OR2) 155, and this data is read from this register in the D / A converter 9 of FIG.
Output to. As a result, a process equivalent to the function of extracting the output from the adder 214 of FIG. 4 and the adder 308 of FIG. 5 is realized.

Next, in step S1003, the 1-channel output data W (OT
1) is read and stored in the output register (OR1) 154, and this data is read from the same register by the D / A converter 8 of FIG.
Output to. As a result, processing equivalent to the function of extracting the output from the multiplier 216 of FIG. 4 and the adder 312 of FIG. 5 is realized.

Next, in step S1004, 2 channel output data W (OT
2) is read and stored in the output register (OR2) 155, and this data is read from the same register by the D / A converter 9 of FIG.
Output to. As a result, processing equivalent to the function of extracting the output from the multiplier 210 of FIG. 4 and the adder 314 of FIG. 5 is realized.

In the present embodiment, since a DSP that digitally processes a signal is used for effect addition processing, if such a DSP is combined with another digital signal processing device, it can be used in the field of electronic musical instruments. However, it is possible to add a sound effect to various musical sounds other than the musical tone signals as described above.

The above embodiment is an example in which the present invention is applied to an electronic musical instrument that generates a musical tone signal, but the present invention is not limited to this, and an acoustic device other than the electronic musical instrument (for example, a karaoke device). ) Is also widely applicable.

[0191]

According to the present invention, it is not necessary to pre-store all combinations of effect forms in the form of a program, and the storage capacity is remarkably reduced and the storage capacity for storing the program is reduced. be able to.

In addition, it is not necessary to change the connection of the effector with the changeover switch during the performance, and it is possible to change the combination of effects to be added to the input sound signal without changing the connection wiring or the large-capacity memory. Will be possible.

Furthermore, since a plurality of effectors are not connected by hardware, even if a plurality of effects are added, a troublesome operation of changing the connection method for a plurality of effectors during performance. There is no need to do this, and the performance of adding multi-effects can be fully exerted with an extremely simple switch operation.

In addition, it is not necessary to perform a process of switching the connection of the effector with a change-over switch or the like during a performance, and it is possible to eliminate the disadvantage that the wiring for that is complicated.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of an effect adding device of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a DSP of the embodiment.

FIG. 3 is an operation flowchart of the CPU of the embodiment.

FIG. 4 is a circuit diagram showing a hardware circuit that executes one form of multi-effect addition processing of the embodiment.

FIG. 5 is another one of the multi-effect addition processing of the same embodiment.
FIG. 6 is a circuit diagram showing a hard circuit that executes one of the forms.

FIG. 6 is an operation flowchart of an entire process for adding a multi-effect according to the embodiment.

FIG. 7 is an operation flowchart showing details of input processing of the embodiment.

FIG. 8 is an operation flowchart showing details of a mix process (1A) of the same embodiment.

FIG. 9 is an operation flowchart showing details of the mix processing (2A) of the same embodiment.

FIG. 10 is an operation flowchart showing details of the mix processing (3A) of the same embodiment.

FIG. 11 is an operation flowchart showing details of a mix process (1B) of the same embodiment.

FIG. 12 is an operation flowchart showing details of the mix processing (2B) of the same embodiment.

FIG. 13 is an operation flowchart showing details of a mix process (3B) of the same embodiment.

FIG. 14 is an operation flowchart showing details of output processing of the embodiment.

FIG. 15 is a diagram showing data used in the example.

FIG. 16 is a diagram showing coefficients used in the same example.

[Explanation of symbols]

1 CPU (program creation means) 2 ROM (effect algorithm storage means, combination algorithm storage means) 3 RAM 4 DSP (effect addition means) 5 switch section 6 and 7 A / D converter (ADC) 8 and 9 D / A conversion Device (DAC) 101 Program memory 102 Control circuit 103 Coefficient memory (P) 104 Work memory (W) 121 Input register (PI1) 122 Input register (PI2) 123 Internal bus 131-134, 147-149 Gate 141 Register (M0) 142 register (M1) 143 register (A0) 144 register (A1) 145 multiplier 146 adder-subtractor 150 register (MR) 151 register (AR) 152 clipper circuit 153 register (SR) 154 output register (OR1) 155 output register ( R2)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G10K 15/08 15/04 302 E 7227-5H (72) Inventor Kozo Hanzawa Taro Nishitama, Tokyo 3-2-1 Sakaemachi, Hamura-cho, Gunma Casio Computer Co., Ltd., Hamura Technology Center (72) Inventor Hiroyuki Sasaki 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Center Hamura Technology Center (( 72) Inventor Jun Yoshino 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd. Hamura Technical Center

Claims (1)

[Claims] 1. An effect algorithm storage unit for storing each effect algorithm for adding a plurality of sound effects to an input sound signal for each algorithm in association with each sound effect, and to the input sound signal. On the other hand, a combination algorithm storage means for storing a combination algorithm for combining a plurality of sound effects in various forms, and an effect algorithm from the effect algorithm storage means according to a combination form of a plurality of sound effects for an input sound signal. And a program creating means for creating a program by reading the combination algorithm from the combination algorithm storage means and transferring the program, and an acoustic signal input based on the program created by the program creating means. Multiple sound effects An effect adding device comprising: an effect adding means for adding.