JPH0552087B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a parallel negative feedback type high frequency amplifier using field effect transistors.

<Conventional technology> One of the field effect transistors (FET)
GaAsMESFET (metal semiconductor field effect transistor) is a Si bipolar transistor or
Compared to SiMOS transistors, SiMOS transistors have superior low noise characteristics and can obtain a high cutoff frequency, so they are put into practical use as high-frequency transistors and are widely used in amplifiers and the like. Furthermore, this
GaAs MESFETs have the advantage of being able to use GaAs to form a semi-insulating substrate, which reduces parasitic capacitance during fabrication, and it is especially easier to fabricate monolithic microwave integrated circuits (ICs) that operate in high frequency bands than Si. Therefore, it is applied to wideband high-frequency monolithic amplifiers.

Among the broadband high-frequency monolithic amplifiers mentioned above, amplifiers with a parallel negative feedback circuit have excellent broadband performance and input/output matching, so they are suitable for radio wave receivers in satellite broadcasting, satellite communications, car phones, CATV, high-speed information processing equipment, etc. They are typically configured in multiple stages to obtain the desired high power gain.

<Problems to be Solved by the Invention> However, in the conventional multi-stage parallel negative feedback amplifier described above, the input level becomes higher toward the later stages, which distorts the power gain and impairs the linearity of the input-output characteristics. There is a problem. In addition, one way to improve such input-output characteristics is to increase the gate width of the FET in the subsequent stage, but even if the input level in the first stage is low, a large drain current flows in the subsequent stage, reducing the power consumption of the entire amplifier. There is a problem of increased power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multistage amplifier that can improve the linearity of input-output characteristics when the input level is high and reduce power consumption when the input level is low.

<Means for Solving the Problems> In order to achieve the above object, the present invention includes three or more field effect transistors formed on the same semiconductor substrate and having substantially the same gate threshold voltage, and The signal amplified by the field effect transistor is applied to the gate of the next stage field effect transistor via a coupling capacitor, and a feedback resistor is connected between the gate and drain of each field effect transistor to form a parallel negative feedback amplification stage. In a multi-stage amplifier configured as follows, the gate width of the subsequent field-effect transistors is made the same or smaller than that of the first-stage field-effect transistor, and a bias resistor is independently connected to the gate terminal of each field-effect transistor. Connect one end to the other end of the bias resistor to shift the gate bias of the subsequent stage to the side that increases the power gain when the input level of the first stage is high, and to shift the gate bias of the subsequent stage to the side that increases the power gain when the input level of the first stage is low. The device is characterized in that a gate bias voltage application terminal is provided to maintain the same as the gate bias of the first stage or to shift the power gain to the side where the power gain is lowered.

<Operation> Through the gate bias voltage application terminal connected to the gate terminal of each FET via the bias resistor,
A gate bias is applied to each FET independently. When the input level of the first stage is high, the power gain of the latter stage FET is increased by shifting the gate bias of the latter stage FET to the side that increases the power gain (in the case of an N-channel FET, in the positive direction).
Improve input-output characteristics. On the other hand, when the input level of the first stage is low, by shifting the gate bias of the subsequent FET to the same as the gate bias of the first stage FET or to the side that lowers the power gain (in the case of N-channel FETs, decrease it). Reduce power consumption.

Furthermore, since the gate width of the FET in the subsequent stage is the same as or smaller than the gate width of the FET in the previous stage, when the input level in the previous stage is low, the drain current in the latter stage becomes relatively small.

<Examples> The present invention will be described in detail below with reference to illustrated examples.

Figure 1 shows an equivalent circuit of a three-stage amplifier formed on the same semiconductor substrate, where 1 is the first amplification stage, 2
is the second amplification stage, 3 is the third amplification stage, 5
6 is a coupling capacitor that couples the first amplification stage 1 and the second amplification stage 2, and 6 is a coupling capacitor that couples the second amplification stage 2 and the third amplification stage 3.

Each of the above amplification stages 1, 2, and 3 has FET7,
The sources 71, 81, 91 of these FETs 7, 8, 9 are grounded 10, 10, 10.
is connected to. In addition, the drains 72, 82, and 92 of the FETs 7, 8, and 9 are connected to the FETs 72, 82, and 92, respectively.
Feedback resistors 11, 21, 31 and feedback capacitors 12, 22, 3 are connected to the gates 73, 83, 93 of 7, 8, 9.
It is connected via 2. The drain 72, 8
2 and 92 each have a 0.2KΩ bias resistor 1
3, 23, and 33 are connected, and the above gate 7
3, 83, and 93 are connected to bias resistors 14, 24, and 34 of 0.3 KΩ, respectively.

The above coupling capacitors 5, 6 and feedback capacitor 1
2, 22, 32 are capacitors composed of metal/insulator/metal, and the bias resistors 13, 2
3, 33 and 14, 24, 34 are resistance layers formed by an ion implantation method in which Si ions are directly implanted into semi-insulating GaAs. Also, above
Channels of FET7, 8, 9 and feedback resistor 11,
21 and 31 are formed by the ion implantation method similarly to the bias resistor described above. The gate threshold voltage of each of the above FETs and the resistance value of each of the above resistances can be controlled by the dose and acceleration energy during ion implantation, and the gate threshold voltage of each of the above FETs is -0.3V.
It is controlled to be between -0.4V and -0.4V.
Furthermore, the gate lengths of the FETs 7, 8, and 9 are shortened to 0.8 μm to increase the cutoff frequency, thereby increasing the power gain and reducing noise. On the other hand, the above
Gate width of FET7, 8, 9 is 1mm and 0.5 respectively
mm, 0.5mm. Note that Au-Ge/Ni is used for the source and drain of the FET, and Ti/Au is used for the gate and wiring.

The multistage amplifier 101 having the above configuration is mounted on a 6-pin TO-5 package 100 as shown in FIG. A drain terminal 102, an input terminal 103 that applies a signal to the first amplification stage 1, an output terminal 104 that takes out the output signal from the third amplification stage 3, and a bias voltage applied to each amplification stage 1, 2, and 3 independently. A first stage gate bias voltage application terminal 105, a second stage gate bias voltage application terminal 106, and a third stage gate bias voltage application terminal 107 are provided.

The characteristics of the multistage amplifier 101 at a frequency of 1 GHz were a noise figure of 2.5 dB, a power gain of 25 dB, an input standing wave ratio of 2.0, and an output standing wave ratio of 1.5 when the drain voltage was 7.5 V and the circuit current was 40 mA. In addition, the frequency is 1 GHz, the drain voltage is 7.5 V, and the circuit current is 40 mA, and the gate voltages Vg ₁ , Vg ₂ , and Vg ₃ of each amplifier stage are −
The input-output characteristics when set to 0.5V are as shown by the solid line in Figure 3. The linearity of this input-output characteristic drops by 1 dB when the output is 5 dBm.
That is, if the output at which the linearity of the input-output characteristic decreases by 1 dB is defined as saturated output power, then the saturated output power in this case is 5 dBm. Keeping the above drain voltage at 7.5V, the gate voltage of each amplification stage is Vg ₁ ,
When Vg ₂ and Vg ₃ were set to −0.5V, −0.5V, and −0.1V, respectively, the input-output characteristics were as shown by the dashed line in FIG. 3, and the saturated output power was improved to 10 dBm.
The circuit current at this time was 50 mA, and no deterioration in noise characteristics was observed.

In this way, the gate bias resistors of each amplifier stage 1, 2, and 3 are connected independently and the gate bias is applied separately, so if the input level of the first stage is high, the gate bias of the FET of the subsequent stage is By shifting the FET in the positive direction,
It is possible to increase the power gain and improve the input-output characteristics. In addition, the gate width of FETs 8 and 9 in the subsequent stage is set to be less than or equal to the gate width of FET 7 in the first stage, so when the input level of the first stage is low, the gate bias voltage of FETs 8 and 9 in the latter stage is changed to the gate width of FET 7 in the first stage. Power consumption can be reduced by making it equal to or lower than the gate bias voltage.

The multi-stage amplifier of the above embodiment can perform automatic gain control (AGC) by controlling the gate voltage of each amplification stage, and can also reduce the input/output VSWR and noise figure depending on the design of the radio wave receiving equipment. power gain can be adjusted without

<Effects of the Invention> As is clear from the above, the multi-stage amplifier of the present invention makes the gate width of the subsequent field-effect transistors the same or smaller than that of the first-stage field-effect transistor, and One end of a bias resistor is connected to the gate terminal of each effect transistor independently, and one end of the bias resistor is connected to the other end of the bias resistor. When the input level is low, a gate bias voltage application terminal is provided to keep the gate bias of the subsequent stage the same as the gate bias of the first stage or to shift it to the side that lowers the power gain, so the input level of the first stage is high. It is possible to improve the linearity of the input-output characteristic in the case where the input level is low, and it is also possible to reduce the power consumption when the input level of the first stage is low.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an equivalent circuit of an embodiment of the present invention, and FIG. 2 is a diagram showing the multistage amplifier of the above embodiment as a TO-5.
Diagram showing the state mounted in the package cage, 3rd
The figure is a diagram showing the input-output characteristics in the above embodiment. 1, 2, 3...Amplification stage, 5, 6...Coupling capacitor, 7, 8, 9...Field effect transistor, 1
0...Earth, 11,21,31...Feedback resistance,
12, 22, 32...Feedback capacitance, 13, 23, 3
3, 14, 24, 34...bias resistance, 71,
81, 91...source, 72,82,92...drain, 73,83,93...gate.

Claims (1)

[Claims] 1. Three or more field effect transistors having substantially the same gate threshold voltage formed on the same semiconductor substrate, and a signal amplified by the previous field effect transistor is connected via a coupling capacitor. In a multi-stage amplifier in which the voltage is applied to the gate of the field-effect transistor in the next stage, and a feedback resistor is connected between the gate and drain of each field-effect transistor to form a parallel negative feedback amplifier stage, the gate of the field-effect transistor in the first stage is applied. The gate width of the subsequent field effect transistors is made the same or smaller than the width, one end of a bias resistor is independently connected to the gate terminal of each field effect transistor, and the other end of the bias resistor is connected to the first stage. When the input level of the first stage is high, the gate bias of the second stage is shifted to the side that increases the power gain, while when the input level of the first stage is low, the gate bias of the second stage is kept the same as the gate bias of the first stage, or the power gain is increased. A multi-stage amplifier characterized by being provided with a gate bias voltage application terminal for shifting to the lowering side.