JPH05508978A - Control method of digital switching matrix memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Control method of digital switching matrix memory The present invention relates to a method for controlling a digital switching matrix memory. this Switching matrix memory allows connections between subscribers of communication equipment to be switched in space and time. It can be formed according to an exchange method.

This form of switching matrix memory can be used, for example, with digital signal path through-connections. Used in switching matrices of functional communication devices. This communication device The subscriber is connected to the switching matrix of the subscriber equipment via input and output lines. is connected to the The input and output lines are operated in a time division multiplexed manner. Each country Each one time slot of the input line is switched when connected to the input line. This time slot is assigned as an input channel of the programming matrix memory. The subscriber can transmit on the assigned as the output channel of the switching matrix memory. this times On the lot the subscriber can receive. Switching matrix memory is Usually contains one memory location for each input channel. This memory location For example, in the case of PCM encoded audio transmission, 8 bits are transmitted. Can be done.

The allocation between input channels and switching matrix memory locations is For switching matrix memory, input channels and switching matrix Configured by simultaneous addressing of memory locations. switching tomatoes Input channel Allows for “through-connection” of any connection path between a module and one or more output channels. Ru.

Due to its configuration, the switching matrix memory connected in this way has the so-called “Point-to-point” connections, i.e. connecting two subscribers to each other. and make it possible. However, these communication devices can be used not only for voice communication but also for data communication. In addition to the connection type in question, the so-called multipoint Connection is highly required.

Multipoint connections from voice communications to conference connections are known. This conference connection Multiple subscribers can participate. This audio conference connection is switched This is accomplished by an external special conference circuit outside the matrix. This conference circuit In addition to the pure signal superposition of a number of speaking subscribers, a logarithmically encoded PCM signal is also added. Linearization must also be performed in order to superimpose the signal without distortion.

Multipoint connections (also known as data conferencing connections) for data communications are similar. This is accomplished by an external conference circuit as described above. This conference circuit has no linearization element But it works. Traditionally used data conferencing circuits Is the subscriber data combination such that all subscribers actually transmit at the same time? It is configured to run as follows. i.e. for the data conferencing circuit , the same conditions were assumed as in the audio conferencing circuit.

The two types of conference circuits have substantially common input signals from a plurality of transmitting subscribers. They are the same in that the signals are formed. This common signal is used by all participants in the conference connection. can be received by subscribers. The disadvantage of this form of conference connection is that external conference circuits must be installed, and depending on the number of conference circuits installed, The number of possible conference connections is limited and the number of inputs on this conference circuit allows you to join a conference. The number of subscribers that can be subscribed to is limited.

The problem of the invention is to provide an unrestricted method for data conferencing connections. .

This problem is solved according to the invention by the method according to claim 1.

For each input channel of the switching matrix memory, the switching matrix A selective allocation to risk memory locations is made. This will cause the data A conference connection can be formed as follows.

That is, multiple transmit-eligible subscribers participating in a data conference connection can A switching matrix can be formed by being allocated to a memory location. I can do it. The maximum number of subscribers to a data conference is proportional to the number of input channels present. do. The maximum number of simultaneous data conferences depends on the switching matrix used. Corresponds to the number of moly locations.

The known switching matrix memory, which operates according to the space-time switching scheme, This characteristic means that data cannot be combined with data already in memory. Until now, the above-mentioned type of allocation has been prevented. knowledge that in addition to the physical connections between subscribers, data transmission protocols are also used. It uses This protocol specifically specifies when and which subscribers can connect to a data conference. Configure whether to continue sending.

During the regular data transmission phase, the transmitting eligible subscribers participate in the data conference connection. Since only one of the subscribers transmits, this transmitting subscriber is not treated specially. of subscribers' data can be written to the common switching matrix memory . By treating sending subscribers differently than sending eligible subscribers, The above characteristics of the switching matrix memory do not work. This is because the data This is because there is no need for matching.

For the method of the present invention, voice communication between two subscribers is 3) or data connection is a special case of a data conference connection. In such a connection, Usually one switching matrix memory location is used for each transmission device. each subscriber transmits to this location; other subscribers transmit to this location. only from applications.

This means that from the point of view of the present invention there is one data conference connection for each transmission device. However, since there are no more participating subscribers in this data conference connection, one subscriber Switching matrix memory location with only one input channel in common It only means that it is assigned to .

Therefore, the method of the present invention uses a switching matrix that operates in a space-time switching manner. does not depend on whether or not the subscriber participates in a data conference, can be used.

In a first embodiment of the method of the invention, the transmitted data differs from the dormant state. The conference connection subscriber is treated as a sending subscriber.

This dormant state exists in all data transmission methods and is used to distinguish between It is possible to do so. The determination of whether a subscriber is actually able to transmit depends on the It is left to the known transmission protocol to be used.

In another embodiment of the invention, a subscriber with different transmitted data from a dormant state initially is treated as a sending subscriber, and this subscriber whose sent data will be suspended again. remain with the sending subscriber until the situation is met.

This form of development ensures that only the subscriber's transmitted data differs from the dormant state. Only the transmitting subscriber's data is shared during a collision resolution transmission protocol that cannot guarantee itself. will be written to the same switching matrix memory location.

Advantageously, the sending subscriber writes to the switching matrix memory location. determined by the write control unit that controls the This write control section Sends a write control signal to the switching matrix memory when an intruder is identified. do.

This write control contains the method steps necessary to detect the sending subscriber. being admired. The relationship between input channels and switching matrix memory locations One common switching matrix memory location with no direct control of connections required The transmitted data of all subscribers assigned to a section are always transferred to the switching matrix. Through-connections can be made to memory locations.

Only by means of a write control signal can the data of the respective sending subscriber be transferred to the switch. processing matrix memory location.

In another development of the method according to the invention, the write control is configured to suspend the subscriber's input channel. The write control signal is switched to a switching master when different data content is identified from the standstill state. Send to trix memory.

In this form of identification, all subscribers whose transmitted data differs from the dormant is treated as a sending subscriber. This subscriber supports e.g. conflict resolution protocols. can be restricted as follows. That is, a common switching matrix when the memory location is not occupied by another subscriber, i.e. input data is written to a common switching matrix memory location. When not, the write control unit sends a write control signal to It can be done. Therefore, the subscriber's data is stored in the switching matrix memory by the subscriber. occupy the application as the first subscriber, or may be written to the switching matrix memory location.

Bringing the memory contents of a switching matrix memory location to a hibernating state In an advantageous embodiment of the invention, upon identifying the transition of the transmitting subscriber to the dormant state, Also, a write control signal is sent from the write control section.

This prevents the sending subscriber's last data content from remaining as memory content. be done. The dormant state in the switching matrix memory location is without additional measures not controlled by the transmission itself, e.g. without frame synchronization reset can be achieved with

Identification of transition to dormancy can be simplified as follows: The criteria representing the It is simplified as follows:

This criterion representing the sending subscriber can be formed by the write control. evaluation In the event of a comparison of the input channel individual memory contents with the instantaneous identifiers of other subscribers may be performed based on whether there is a transition to hibernation.

The identification of the occupancy of the switching matrix memory location by the sending subscriber is as follows: It can be simplified as follows. That is, the switching matrix memory location The criteria representing the occupancy by the transmitting subscriber of the switching matrix memory location It is filed in the individual memory of the computer and evaluated by the write control unit.

This reference can also be formed by the write control section. During evaluation, switch Ching Matrix Memory Location Individual memory contents and instantaneous identification of the sending subscriber A comparison with Besshi shows that the subscriber in question occupies switching matrix memory locations. This can be done based on whether or not it is allowed to have.

The assignment of the input channels to the switching memory locations is preferably This is done through the contents of a common connection memory addressable by the channel. this The connection memory addresses the switching matrix memory.

This connection memory makes it easy to connect any number of subscribers in a data conference connection to a common switch. A switching matrix memory location can be assigned to any number of memory locations at the same time. There may be data conferences. This is because subscribers can access which connections for each human-powered channel. The switching matrix memory file stored in the connection memory This is because it is determined by the application address.

The present invention will be explained in detail below based on the drawings.

FIG. 1 is a block circuit diagram of a switching matrix according to the prior art; FIG. 2 is a block circuit diagram of a switching matrix according to a first embodiment of the present invention. , FIG. 3 shows the first embodiment of the write control section, and FIG. 4 shows the switching matrix of FIG. The switching matrix memory location by the write control section of Figure 3 in the FIG. 5 shows a time diagram for the course of the switch occupancy according to the second embodiment of the invention. Chingmatrix block circuit diagram, FIG. 6 is a circuit diagram of the write control section of FIG. 5.

Figure 1 shows a block circuit diagram of a switching matrix of a communication device according to the prior art. It is shown. ■7 is a direct line from the input line IO to which subscribers are connected in a time division multiplexing system. It is connected to a column-to-parallel converter and multiplexer (S/P) 10. this strange The converter converts the serial data on all input lines IO to I7 into 8-bit wide parallel data. Convert to data. This parallel data is passed through input data lines DiO-Di7. The signal is supplied to a switching matrix memory (SM) 12. This switching machine The matrix memory 12 is one switching matrix memory for each input channel. Contains location. This switching matrix memory 12 switch The programming matrix memory locations are serial-to-parallel converter and multiplexer 1. Addressing is performed at address ADi by the cyclic counter (CTR) of Ml in common with o. be logged.

In synchronization with each address change, this cyclic counter 14 writes via the control line WR. Sends a control signal.

This write control signal causes the data Di on the input data lines DiO to Di7 to Switching matrix addressed by respective address ADi written to a memory location. Series-parallel converter and multiplexer 1 4 and the switching matrix memory locations. , a fixed mapping relationship between input channels and switching matrix memory locations. You can get someone in charge.

The switching matrix memory location connects the output data lines DoO to Do7. It can be read out via fi column serializer and demultiplexer (P /5) With 16 these data are transferred to the output line 00 which again operates in a time division multiplexed manner. ~03 will be distributed. Subscribers connected from these output lines will not be able to receive again. I can do it. This parallel/serial converter and demultiplexer 16 is a cycle of j[2 It is addressed by the counter (CTR) 18 at address ADo. This ad The response ADo is simultaneously supplied to the connection memory (CM) 20. This connection memory output The switching matrix memory 12 is activated for reading by the force data ADm. Dressed. This connection memory 20 has a memory location for each output channel. This memory location contains a switching matrix memory location. can remember the address of the application. This data content of the connection memory 20 The switching matrix memory location and hence the input channels and output A selective assignment with force channels is achieved.

The cyclic counter 18 switches the read control signal RD in synchronization with each address change. data is sent to the processing matrix memory 12. This switching matrix memory The address ADm applied is inherited. Synchronization, clock generation and connections The circuit part of the switching matrix used for memory adjustment is shown in detail in the block diagram. This is because these configurations are known and are not necessary for the description of the present invention. This is because it is not necessary.

FIG. 2 shows a block diagram of a switching matrix according to a jl12 embodiment of the invention. Circuit parts already present in Figure 1 for which the circuit diagram is shown are given the same reference numerals. ing.

Address ADi from first cyclic counter 14 to switching matrix memory A second connection memory (CM) 22 is additionally inserted into the connection path. this connection The memory includes one memory location for each human channel. this connection The switching matrix memory 12 performs an address according to the output data ADn of the memory 22. Being raced. The contents of this connection memory are the switches assigned to the input channels. ching matrix memory location address. This address is not shown. It can be written for control of communication devices via a clear connection.

Since the contents of the connected memory locations can be arbitrary, a common switch Assigning matrix memory locations to multiple subscribers or input channels Having the same switching matrix memory in multiple connected memory locations This is possible by recording the relocation address.

This switching matrix memory location is determined by the control section of the communication device. If the connection memory 20 for the subscriber's output channel is also recorded, the switch The data recorded in the Matrix memory location can also be read again by the subscriber. Can be received.

For special handling of transmitting subscribers, additional input data lines DiO to Di7 are provided. A write control section (STC) 24 is connected thereto. This write control unit also has a cyclic counter. Control jJij&WR connection from the printer 14 to the switching matrix memory 12 connection. This write control section allows the subscriber who is eligible to send and the subscriber who is sending A distinction will be made from those entering the country. The write control unit 24, which will be further explained later, is a switching In the matrix memory 12, the control unit changes from the hibernation state or enters the hibernation state. When detecting a transition, a write control signal is sent out via the control line WRi. this holiday In order to easily detect a change to the stopped state, the write control unit 24 additionally connects a signal line. It is connected to the connection memory 22 via the lines STI and STO. These two beliefs A reference for instructing a change from the rest state is connected from the write control unit 24 via the road. It is then sent to the subsequent memory 22 and read out again for evaluation at a later point in time. this is Separate storage for each input channel in an additional storage location for each connected memory location It's for a reason.

The functions of the write control section 24 will be explained in detail below based on FIG. 3.

In the NAND gate 30, the data contents of the input data lines DiO to D17 are in a dormant state. It is used as a comparison device to identify changes from

The dormant state in this embodiment assumes a logic "1" for all input data lines. . This is expressed in hexadecimal notation as "FFH"i: correspondingly t6. ．． :(7) NAND game 30 (7) The output side DAT is connected to the input data lines DiO to Di7 (all of which are one). Whenever it assumes a state different from this dormant state, it becomes logic "1". The output side DAT is It is connected to the signal line STO, and its state is used as a reference to indicate a change from the rest state. and is supplied to the connection memory 22 for storage for each input channel.

At a relatively later point in time, the memory contents individual to the input channels in the connection memory 22 are Again, an inquiry is made from the write control unit via the signal line STI. OR gate 32, the state of the signal line STI is the instantaneous state of the output DAT of the NANp gate 30. is combined with The output of this OR gate 32 is "1" in the following cases, i.e. , the instantaneous state of the input data line DiO=Di7 changes from the rest state, i.e. When the output DAT of the NAND gate 30 is 1'' or at a previous point in time, For each addressed input channel, when changing from the dormant state, i.e. When the state of the signal line STI is logic "1", the output of the OR gate is "l" , the output side of the OR gate 32 is connected to the input side of the AND gate 34. this A second input of the AND gate is connected to a control line WR. This AND game When one of the two conditions of the OR gate 32 is satisfied, , a write control signal synchronized with the address change is sent to the control line WRi.

In this way all subscribers whose data content does not change from the dormant state sent be treated as an eligible subscriber. The subscriber's data is input to the input data line DiO ~Di7 to the switching matrix memory. However, writing is required The control signal is not formed on the control line WRi, and the data content differs from that in the dormant state. is treated as a transmitting subscriber and its data is sent to the write control signal on control line WRi. is written to the switching matrix memory by the signal.

FIG. 4 shows the switching matrix of FIG. 2 having the write control section of FIG. 3. Time chart for the course of switching matrix memory location occupancy It is shown.

Addresses ADi, ADn, ADm, ADo and input/output data Di and DO arrangement Switching matrix memory addressed by ADn or ADm The data content of the location is expressed in hexadecimal notation. The horizontal axis shows time division multiplexing. A sequence of frames n is plotted. cyclic count within this sequence Ta 14.18 is the maximum count from O! Switching motor until aIFFH Addressing the trix memory 12. The time chart contains data for simplicity. Only the status for the two input channels or the two subscribers participating in the data conference is shown. has been done.

In the connection memory 22 (FIG. 2) 2 with addresses ADi-020H and 050H Switching matrix memory location address for one input channel ADn÷045H is recorded. The two input channels are therefore connected to one common switch. allocated to a matrix memory location. In the first frame n These two input channels as well as the switching matrix memory location D4 The contents of the data Di of No. 5 correspond to the dormant state 11"FFH". Output DAT (NA The ND gate 30 (Fig. 3) and the signal line STO of the write control section 24 (Fig. 3) are inactive. is active '0'', because the data content Di remains unchanged from the dormant state. .

As indicated by the logic “0” state on signal line STI, the preceding time division multiplexed frame There was also no change from the resting state.

Therefore, no write control signal is formed on the signal line WRi. 2 input channels The switch addressed by the original address A D n -045H The contents of the matrix memory location D45 remain unchanged and are in the dormant state “FFH”. It remains as it is.

For the output side of the switching matrix memory, address ADo-021H Similarly for the two output channels with 051H and 051H, the switching mat Risk memory location address ADm-045H is connected memory 20 (Figure 2) recorded in

Special table 15-508978 (6) As output data DO, in this time division multiplex frame, there is a pause every two output channels. The state "FFH" is read out by the read control signal on the control line RD.

In the subsequent time division multiplexed frame n+1, the subscriber controlled by the transmission protocol data transmission begins. Therefore the input with address ADi=020H The input data Di of the channel takes the value "09H".

Depending on the data content changing from this idle state, the output DAT and write control section The control line STO becomes logic “1”, thus synchronizing with the address change. A write control signal is formed on the control line WR4, and the data is transferred to the switching matrix. Written to memory space D45. At the same time, it instructs a change from the idle state. The reference on the signal line STO that is The contents of the switching matrix memory D45 are divided into two output channels. can be output to.

The subsequent time division multiplexed frame n+2 has address ADi=020H. The input data of the input channel changes to the value "034H". This data switch The data is transferred to the processing matrix memory space D45.

The state of the signal line STI is determined by the address ADi in the preceding time division multiplex frame n+1. = 020H when the data of the input channel changes from the idle state. and give instructions.

This information is used in the subsequent time division multiplexed frame n+3. Address ADi= The data content Di of the input channel with 020H changes to the idle state and the data The data transmission ends T. Output DAT and signal line S of write control unit 24 (FIG. 3) TO is no longer "1" during this data content of the input channel. write The control section further sends a write control signal to the control line WR based on the state of the signal line STI. Send to i. This is because there is a change to the idle state. this book The idle state of the input data is switched to the switching matrix memo by the input control signal. It is written to the respace D45. At the same time, the state of the signal line STI is determined by the connected memory. is recorded in an additional memory location.

In time division multiplex frame n+4, the idle corresponding to time division multiplex frame n is returned again. reach the state.

FIG. 5 shows a block circuit of a switching matrix according to a second embodiment of the present invention. A diagram is shown. This embodiment additionally includes a switching matrix memory Pace occupancy is evaluated by subscribers.

For this purpose, the write control unit 50, which is different from that in FIG. 2 with additional signal lines MSO and MSI. These signal lines The criteria that direct the switching matrix memory space occupancy through the control 50 to this storage location and read out again. This standard applies to each switch. The matrix is stored in an additional storage location in the memory space.

The functions of the write control section 50 will be explained based on the truth table shown in FIG.

The idle state also assumes a logic "1" for all input data lines in this embodiment. Ru. This corresponds to "FFH" for Di when expressed in hexadecimal notation.

In the M1 column a, the input data line D1 is in the idle state "FFH". Write-in system The control section 50 signal line STI has a logic "0" state. This state is indicates that the data did not change from the idle state in the preceding time-division multiplex frame. do. Similarly, logic "O" is output to the signal line MSI. This is just an ad The switching matrix memory space (ADn, Figure 5) being Indicates that it is not occupied by an input channel. Therefore, in this column, the data The transmission is idle, the connected input channel is also idle, and the Switching matrix memory space is not occupied by input channels, Based on this state of the input line, the write control unit 50 controls the signal lines ST○ and MSO. It also sends the logic "On" to the control line WRi.

In the second column, the input data line Di continues to be in the idle state "FFH". writing The signal line STI of the integrated control unit 50 has a logic state ll″O″, which means that when the preceding Indicates that the input data has not changed from the idle state in the split multiplex frame. Ru. On the other hand, logic "1" is applied to the signal line MSI. This is just Addressed switching matrix memory space (ADn , FIG. 5) is occupied by the input channel. In this column, enter The power channel data is idle and is stored in the switching matrix memory space. The space is used for data transmission from the other input channel, ie, it is occupied.

Based on this state of the input line, the write control unit 50 aligns the signal lines STO and MSO. Logic "0" is sent to the control line WRi.

In the third column C, the input data line Di changes from the idle state (≠FFH). The signal line ST) of the write control unit 50 has the logic state "0". This is the input data indicates that the data did not change from the idle state in the preceding time division multiplexed frame. Show. On the other hand, a logic "1" is applied to the signal line MSI. This is it Addressed switching matrix memory space (ADn, 5) is occupied by the input channel. In this column, input Channels attempt to occupy switching matrix memory space, i.e. That is, an attempt is made to start data transmission. The signal line MSI is logic “1”, and this Based on the fact that the signal line STI is at logic “O”, the write control unit The switching matrix memory space is occupied, but this occupation is Identify that it is not caused by a force channel. Because this input channel This is because the state did not change from the idle state in the preceding time division multiplexed frame.

This way other input channels share a common switching matrix memory space. Therefore, the write control unit 50 uses the signal lines STO and MSO as well as the control line. It sends a logic "0" to the path WR4.

In the fourth column d, the input data line Di changes from the idle state (≠FFH), the write The signal line STI of the write control unit 50 has a logic state “O#”. The force data did not change from the idle state in the preceding time division multiplexed frame. instruct. The signal line MSI is also at logic "0". This is just an address The switching matrix memory space (ADn, Figure 5) being Indicates that it is not occupied by a force channel. In this column, the input channel tries to occupy switching matrix memory space, i.e. data Attempt to start transmission.

Due to the fact that the signal line MSI is logic ``0'', the write control section Identify that trix memory space is not occupied. Other input channels writes without occupying common switching matrix memory space The control unit 50 sends a logic “l” to the signal lines STo and MSO, and A corresponding write control signal is sent to the control line WR. Data transmission starts be able to.

In the fifth column e, the input data line Di changes from the idle state (≠FFH). The signal line STI of the write control unit 50 has a logic state "l", which indicates that the input Indicates that data has changed from an idle state in the preceding time division multiplexed frame. Ru. Similarly, logic "1" is applied to the signal line MSI. This is just an address The switching matrix memory space (ADn, Figure 5) being indicates that it is occupied by a force channel. In this column, the input channels are Continues to occupy switching matrix memory space, i.e. data transmission continue. Write control based on the fact that signal lines MSI and STI are logic “1” The switching matrix memory space is occupied, and this occupation is The input channel is connected to the input channel.

Based on this, the write control unit 50 sends a logic "l" to the signal lines STO and MSO. output, and a write control signal corresponding to the control line WR is sent to the control line WR1. j[6 In column f, the input data line Di has the idle state "FFH".Write The signal line STI of the control unit 50 has the logic state "1". This condition indicates that the input indicates that the data has changed from the idle state in the preceding time division multiplexed frame. . Similarly, logic “1” is applied to the signal line MSI, which is just the address. The switching matrix memory space (ADn, Figure 5) being Indicate what is being done. In this column, the input channels are connected to switching matrices. end the occupation of the memory space, i.e. end the data transmission. signal line Based on the fact that MSI and STI are logic "1", the write control unit 50 Matrix memory space is occupied and this occupation is just connected identify that the input was made by the specified input channel. switching tomatoes To create an idle state in the risk memory space, the write controller 50 sends a signal Send logic "0" to the lines STO and MSO, and send the logic "0" to the control line WRi to the control line WR. A corresponding write control signal is sent out. In this way, idle state data is scanned each time. The switching matrix is loaded into the memory space and can be accessed via the MSI. Indicates that the matrix memory space is occupied (%).

Eiq, 2 Figj Negative 9J Summary book Control method of digital switching matrix memory The present invention forms connections between subscribers of communication devices using a space-time exchange method. The present invention relates to a method for controlling a digital switching matrix memory that allows for the control of digital switching matrix memory. Swish Switching matrix for all input channels of switching matrix memory for selective allocation of memory space and forming data conferencing connections. Input channels for multiple transmit-eligible subscribers to participate in the data conference connection in order to are allocated to one common switching matrix memory space, and each Write the transmitting subscriber's data into the switching matrix memory space.

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Claims (12)

[Claims] 1. It is possible to form connections between subscribers of communication equipment using the space-time exchange method. In the control method of digital switching matrix memory, switching One switching matrix for all input channels of matrix memory Freely allocate memory space, For a data conferencing connection, multiple sending eligible subscribers participating in the data conferencing connection. Allocate one common switching matrix memory space to the input channels of hand, The data of each subscriber to be transmitted is stored in the corresponding switching matrix memory space. A method of controlling a digital switching matrix memory characterized by writing to Law. 2. A subscriber whose transmitted data changes from an idle state is taken as a transmitting subscriber. A control method according to claim 1. 3. A subscriber sending only those subscribers whose sending data changes from the idle state for the first time and the subscriber in question will not be able to send its data until it becomes idle again. The control method according to claim 1, wherein the control method remains at the subscriber. 4. The sending subscriber controls writes to the switching matrix memory space The writing control unit identifies the sending subscriber. Sends a write control signal to the switching matrix memory space when A control method according to any one of claims 1 to 3. 5. The write control unit is configured to change the data content of the subscriber's input channel from the idle state to Matrix memory that switches the write control signal when it identifies that it has changed. 5. The control method according to claim 4, wherein the control method is to send out to a space. 6. The write control section uses a common switching matrix memory space to Claim 5: Sending a write control signal when not occupied by a user Control method described in section. 7. The write control unit also writes when the sending subscriber transitions to an idle state. Claim 4: Sending control signals to the switching matrix memory space. The control method according to any one of paragraphs 1 to 6. 8. Criteria representing other transmitting subscribers are stored in a memory separate to the input channel. The control method according to any one of the ranges 1 to 7. 9. Criteria representing the occupation of switching matrix memory space by a sending subscriber , the switching matrix memory space is stored in a separate memory. The control method according to any one of items 1 to 8. 10. The allocation of input channels to the switching matrix memory space is This is done using the contents of the connection memory that can be commonly addressed by the input channels. The output of the memory is a request for addressing the switching matrix memory space. 9. The control method according to any one of the requirements ranges 1 to 9. 11. The criteria representing the sending subscriber is an additional memory space in each memory space of the connection memory. 9. The control method according to claim 8, wherein the control method is stored in a location. 12. The standard for expressing switching matrix memory occupancy is for each switching matrix. 9. The control according to claim 9, which is stored in an additional storage location of the memory space. Method.