JPH0550833U - Frequency synthesizer tuner - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a frequency synthesizer tuner which searches a receiving station at high speed and reduces the mute period after the receiving station is searched. A time constant circuit 2 having a small time constant is connected in parallel to a time constant circuit 3 having a large time constant during reception of a receiving station, and the time constant circuit 3 is connected to the time constant circuit 2 during search of the receiving station. In a frequency synthesizer tuner equipped with a PLL circuit having a loop filter configured to be separated from the above, the potential of the capacitor C ₁ of the time constant circuit ₂ is applied to the capacitor C ₂ of the time constant circuit 3 during the search of the receiving station. Buffer amplifiers 6 and 7 and switches 8 ₁ and 8 ₂ are provided to make the potential difference between both capacitors equal.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a frequency synthesizer tuner having a PLL circuit equipped with a loop filter that achieves both a response speed and S / N.

[0002]

[Prior Art]

In the conventional frequency synthesizer tuner, as shown in FIG. 3, the loop filter of the frequency synthesizer tuner includes a resistor R ₁ and a capacitor C _{1 in} a feedback circuit of an amplifier 1 which forms a loop filter together with time constant circuits 2 and 3 described later. A time constant circuit 2 having a small time constant connected to a series circuit is connected, and a time constant circuit 3 having a large time constant composed of a resistor R ₂ and a capacitor C ₂ is selectively connected to the time constant circuit 2 via a switch 4. It is configured to be connected in parallel.

In the above loop filter, only the time constant circuit 2 is connected at the time of tuning, and a receiving station search is performed at high speed as a loop filter having a high cutoff frequency, and when tuning to the target station, the switch 4 is turned on. Under the control, the time constant circuit 2 is connected in parallel to the time constant circuit 2 so that the time constant circuit 3 acts as a loop filter having a low cutoff frequency to improve the S / N and perform reception.

In the above-described conventional frequency synthesizer tuner, the time constant circuit 2 is switched to a small time constant in order to change the reception frequency at the time point a as shown in FIG. The receiving station is searched for, the switch 4 is controlled to the ON state at the time point b, the time constant circuit 3 is connected, and the time constant increases.

[0005]

[Problems to be solved by the device]

However, when searching for a receiving station at high speed, the time constant circuit 3 having a large time constant is simply disconnected, and the electric charge before searching for the receiving station is charged in the capacitor C ₂ , and the receiving station is searched. After the search, when the loop filter has an output voltage different from that before the search for the receiving station, that is, the tuning voltage Vt (time point b), if the time constant circuit 3 is connected as it is, charging / discharging is performed due to the difference in the tuning voltage Vt. Therefore, the PLL circuit is momentarily unlocked, the tuning voltage Vt fluctuates during the period T as shown in FIG. 4, and it is necessary to mute to prevent shock noise during that period. Even when searching for a station, there was a problem that it was necessary to lengthen the mute time.

An object of the present invention is to provide a frequency synthesizer tuner that searches a receiving station at high speed and reduces the mute period after searching the receiving station.

[0007]

[Means for Solving the Problems]

 In the frequency synthesizer tuner of the present invention, a first time constant circuit having a small time constant and a second time constant circuit having a large time constant are connected in parallel during reception of a receiving station, and during search of the receiving station. In a frequency synthesizer tuner including a PLL circuit having a loop filter configured so that the second time constant circuit is separated from the first time constant circuit, the capacitor of the second time constant circuit is searched during the search of the receiving station. Is provided with a charging means for charging to a potential difference equivalent to that of the capacitor of the first time constant circuit.

[0008]

[Action]

 According to the frequency synthesizer tuner of the present invention, during the search of the receiving station, the capacitor of the time constant circuit with a large time constant is charged by the charging means to a potential difference equivalent to that of the capacitor of the time constant circuit with a small time constant. When the search at the receiving station is completed, the output voltage of the loop filter does not change when the first and second time constant circuits are connected in parallel, and the PLL circuit does not enter the unlocked state. And the mute period can be shortened.

[0009]

【Example】

 Hereinafter, the present invention will be described with reference to examples. FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention, showing a loop filter of a PLL circuit in a frequency synthesizer tuner. In this embodiment, the same components as those in FIG. 3 are designated by the same reference numerals.

The loop filter of the present embodiment receives the phase comparison output from a phase comparator (not shown) as an input and supplies the output as a control voltage to a voltage controlled oscillator (not shown) that oscillates at a frequency related to the local oscillation frequency. In addition, the amplifier 1 for applying the tuning voltage Vt to the variable capacitance diode of the RF amplification stage (not shown) and the time constant circuit 2 connected to the feedback circuit of the amplifier 1 are provided.

The loop filter of the present embodiment further includes a time constant circuit 3, a buffer amplifier 6 including a voltage follower having an input voltage of the amplifier 1 as an input, and a voltage follower having an output voltage of the amplifier 1 as an input. Buffer amplifier 7 and switch 8 which is interlocked to selectively connect the time constant circuit 3 between the input and output ends of the amplifier 1 or between the output ends of the buffer amplifiers 6 and 7. ₁ Otobi 8 _2, in conjunction with the switch _81, and the time constant circuit 3 is provided with a switch 8 ₃ for short-circuiting between the resistor R ₂ connected between the output terminal of the buffer amplifier 6 and 7.

According to the loop filter configured as described above, the switches 8 ₁ and 8 ₂ are switched to the input end side and the output end side of the amplifier 1 in order to improve the S / N during normal reception. The time constant circuits 2 and 3 are controlled so that they are connected in parallel. Further, the switch 8 ₃ is controlled in the off state.

Therefore, in this case, the feedback circuit of the amplifier 1 is connected to the parallel circuit of the time constant circuit 2 and the time constant circuit 3, and the potential difference between the both ends of the capacitor C ₁ and the capacitor C ₂ are connected. The potential difference between both ends is equal, and the time constant of the feedback circuit is dominated by the time constant of the time constant circuit 3, but the time constant of the feedback circuit is large and good S / N is received.

Here, when a high speed search of the receiving station is performed at the time point a in FIG. 2, the switches 8 ₁ and 8 ₂ are switched and the time constant circuit 3 is connected between the output terminals of the buffer amplifiers 6 and 7. , The time constant circuit 3 is substantially disconnected, the switch 8 ₃ is controlled in the ON state, and the resistor R ₂ is short-circuited. Therefore, the potential difference between both ends of the capacitor C ₂ is forcibly charged to the potential difference between the input end of the amplifier 1 and the output end of the amplifier 1 via the buffer amplifiers 6 and 7. In this case, the resistor R ₂ is short-circuited, so that charging is performed rapidly.

Here, after the PLL circuit is locked by the time constant of the time constant circuit 2, that is, at the time point b in FIG. 2, the switches 8 ₁ and 8 ₂ are switched, and the input end of the amplifier 1 and the output end of the amplifier 1 are switched. The time constant circuits 2 and 3 are controlled to be connected to each other, and the switch 8 ₃ is controlled to the off state.

At this point in time b, the potential difference across the capacitor C ₂ has already been charged to the same potential as the potential difference across the capacitor C ₁ by the buffer amplifiers 6 and 7, so the time constant circuit 3 switches the switch 8 ₁ And 8 ₂ connected between the input end of the amplifier 1 and the output end of the amplifier 1 do not change the potentials of the input end of the amplifier 1 and the output end of the amplifier 1.

Therefore, since the tuning voltage Vt is not changed by connecting the time constant circuit 3 and the PLL circuit is not in the unlocked state, there is no need to mute thereafter, and the time constant circuit 2 does not need to be muted. It will be improved in the period corresponding to the lock-up time, and after the mute is released, the time constant circuit 3 is already connected, so that reception can be performed in a good S / N state.

[0018]

[Effect of the device]

 As described above, according to the present invention, during the search of the receiving station, the capacitor of the time constant circuit with a large time constant is configured to be charged by the charging means to a potential difference equivalent to that of the capacitor of the time constant circuit with a small time constant. Therefore, when the search of the receiving station is completed, the output voltage of the loop filter does not change when the first and second time constant circuits are connected in parallel, the PLL circuit does not enter the unlocked state, and the high speed It is possible to search and reduce the mute period.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a tuning voltage characteristic diagram for explaining the operation of one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional example.

FIG. 4 is a tuning voltage characteristic diagram for explaining the operation of the conventional example.

[Explanation of symbols]

1 Amplifier 2 and 3 Time constant circuit with small time constant and time constant circuit with large time constant 6 and 7 Buffer amplifier 8 ₁ , 8 ₂ and 8 ₃ switch

Claims (1)

[Scope of utility model registration request] 1. A first time constant circuit having a small time constant and a second time constant circuit having a large time constant are connected in parallel during reception of a receiving station, and a second time constant circuit during search of the receiving station. In a frequency synthesizer tuner comprising a PLL circuit having a loop filter configured such that the constant circuit is decoupled from the first time constant circuit, a capacitor of the second time constant circuit is connected to the first time constant circuit during search of the receiving station. A frequency synthesizer tuner comprising a charging means for charging to a potential difference equivalent to that of a capacitor of a constant circuit.