JPH05502315A - Methods for transferring data between data storage subsystems and host data processing systems - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] data storage subsystem and Transferring data to and from host systems [Technical field] The present invention provides a data storage subsystem and a connected host data processing system. Concerning the field of data transfer to and from.

[Background technology] Data storage subsystems used within data processing systems typically store customer data. a device controller connected to one or more storage devices holding data. child An important requirement for subsystems such as It should be accessible at high speed by a host data processing system. remember Efforts continue to develop subsystems that can transfer data at increasingly faster speeds. I'm being kicked.

Connect the host to the device controller, and the controller to the device. interface has been developed.

One such interface has been standardized by the American National Standards Institute (ANSI). Small computer system interface (SC3) adopted as a standard I). A data storage subsystem that connects the controller to the device using the SC3I bus. The stem is known.

Several techniques are described for transferring data from the subsystem to the host. There is. In one known technique, for each data transfer operation, data is transferred to the device. It is checked for errors before it is executed. Read each data sector from the device, held in a data buffer and sent to an attached host data processing system. Check for errors in the data buffer before This technique requires good data The advantage is that only the However, if all data is transferred There is also an inherent performance loss in the amount of time it takes to complete the process.

IBM System/370 transfers data directly from the device to the host without inspection. Another technique is used, which is direct communication.

Sending ``raw'' data in this way is more advantageous than the previous method by data-sending sectors before transmission. There is a performance benefit in that it does not need to be held in a data buffer. However, Sys This technique used in tem/370 does not allow errors in the transmitted data. There are shortcomings that become apparent when you are present. When this occurs, it is first detected by the host. large portions of the requested data must be retransmitted.

Several performance-enhancing techniques are available to speed up data transmission between the device and the host. laws have been developed. One of them is that when data is requested, the requested data is It is a split transfer that reduces the latency that occurs when it is not under the head. US patent No. 4,494,157 uses split transfer to transfer data in two bursts. It describes how to transfer to buffer. Two bursts of data are sent to the host It is received in a buffer before being sent to the system.

[Invention disclosure code] The present invention provides a data storage subsystem and a connected host data processing system. The purpose is to achieve high-speed data transfer between

Accordingly, the present invention provides a direct access storage device for storing data for communication. From a data storage subsystem with an attached device controller to an attached host provides a method for transferring data to a client data processing system. This method transfers The sequence of data blocks to be executed and the first blot of the data sequence A data transfer command that specifies the starting address in host memory to which the data will be transferred. from the system to the device controller to start data transfer, and A step that transfers a sequence of data from a subsystem to a system in response to a command. The controller has the ability to respecify the starting address in host memory. have

Therefore, the control unit starts in host memory in the range specified by the command. Addresses can be respecified.

In reality, this controller has random access to host memory. do. This is a useful feature in many ways.

In a preferred method, the control device non-sequentially controls said data sequence from the device. Request a transfer in order and use the starting address specified by the host to Modified starting address in host memory to which to send the first block of sequential data. The controller transfers the data to the host in non-sequential order and 1 block is sent to the modified starting address.

Therefore, in a split read transfer, the controller sends the second burst of data to address within the host can be respecified. In this way, the first berth The controller must wait for the second burst of data to be received before sending the burst to the host. It becomes unnecessary. This will cause you to receive "out of order" data from the device, but traditional systems that required data to be transferred to the host in the correct order. There are performance benefits in comparison.

The control unit also processes data from the devices in the same order as specified in the command. requesting a transfer, the controller transfers the first block of said data sequence to the host Send to the address specified by. This means that the data is hosted on blocks in ascending order. It is a "normal" read operation that is transferred up to .

In a preferred method, when an error is detected in a portion of the data sequence, the control request the device to retransmit said portion, as specified in the command from the host. the address in host memory to send the retry portion to. calculate.

Therefore, if an error occurs during data transfer, the control unit retransmit the minutes to the host. Perform random access to host memory , there is no need to resend the entire data specified in the original command.

In another aspect of the present invention, the controller includes a starting address in host memory to which data is to be transferred. communication to a direct access storage device, characterized in that it has the ability to specify an address; During operation, the data is controlled by the device. connected host data that is transferred through the device to memory within the data processing system. data storage for storing data accessible by a data processing system A subsystem is provided.

Preferred embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which: FIG. Carrying out the invention Not all of the features included in the description below are necessary for implementation. Please note that.

Brief explanation of the drawing] FIG. 1 shows a block diagram of the main functional units of a data storage subsystem according to the present invention. This is a diagram.

FIG. 2 is a block diagram showing the main components of the adapter of FIG. 1.

FIG. 3 is a diagram showing the structure of the adapter link chip of FIG. 2.

FIG. 4 is a block diagram showing the main components of the control device of FIG. 1.

FIG. 5 is a block diagram illustrating the structure of the controller link chip of FIG. 4.

FIG. 6 is a block diagram showing the communication between tasks defined within the control unit microprocessor. It is a lock diagram.

Figure 7 is a block showing inbound serial links and outbound serial links. It is a diagram.

Detailed explanation of the invention Suitable for connection to data processing systems and provides fast access by host systems Describes a data storage subsystem that provides large amounts of storage. Figure 1 The main functional units of this subsystem, shown in Figure 1, are: (1) host adapter; 2) a device controller; and (3) a direct access storage device (DASD). this These functional units are interconnected by a 7 point full duplex series link. 1st The figure shows the basic configuration of this subsystem. The controller 10 is connected to one control device 20 via a dedicated serial link IS, and Station 2o is connected to four DAs 30 by four series links 25 to 28. It is. Most of the following description is related to this basic configuration. However, this The subsystem architecture (detailed below) allows each adapter to Can be connected to 4 control devices, each control device can be connected to up to 4 devices. It is measured. In the preferred embodiment of this subsystem, the host adapter is , housed within the host system and connected to the housing (e.g. rack) via a serial link. connected to a drawer or freestanding unit attached to a rack. This housing is , one control unit, four DASDs, and associated power and cooling systems (not shown). ).

First, the main functions of the adapter, control unit, and DASD will be briefly described.

1. Adapter An adapter essentially connects a host system to a control unit through a serial link. This is a general-purpose multi-tub I node that follows. The adapter is IBM's Micro Channel ・Architecture (micro channels are Various existing interfaces such as Scenes Coho 1/Ishiyon registered trademark) can be designed to connect to a host system via

The main functions of the adapter are as follows.

1) The adapter is 5C3I (small computer system interface ) commands from system memory using direct memory access (DMA). and transfer these commands to the controller via a serial link.

2) The adapter manages a pool of DMA channels and reads data on demand. or allocate these channels to the control unit for transfer of write data.

3) The adapter writes packets of write data from host memory via DMA. and transmit these to the control device via a serial link.

4) The adapter receives packets of read data from the serial link and transfers them to DMA. Therefore, these are stored in the system memory.

5) The adapter assembles and presents the exit status of each command to the system. temporary can present good conditions for up to four devices.

6) The adapter provides a means to abort previous SC3I commands.

2. Control device The control unit uses the SC3I command set for the attached DASD (its elements Those related to this specification will be defined separately). The main functions are as follows. It is.

1) The controller maintains a command queue for each DASD.

2) The controller prefetches the write data from the host system and prefetches the read data. data buffer for correcting data and prefetching read data from DASD. (shared among DASDs).

3) The controller generates a 5C8I status.

3.DASD The main functions of DASD are as follows.

1) DASD seeks to specified cylinder and head.

2) The DASD receives the starting logical block address (LBA) provided by the controller. the specified number of tracks, seeking to the next track if necessary. Read or write blocks. If a defective block is found, the DASD will automatically skip them.

3) DASD generates and checks ECC bytes appended to each block. D FCC hardware is included in the ASD, and the controller uses different ECC algorithms. It is designed to support a range of DASDs, which may also have Ru.

If the DASD detects a data error, the controller informs the DASD of the error. Request to supply pattern and displacement. The controller then uses the correct the data and restart the transfer to the adapter.

4) DASD has a recording channel for both read data and write data. book The embedded data is encoded and serialized before being provided to the head. from the head The read signal is detected, deserialized, and decoded.

series link A serial link is between two nodes of this subsystem: the adapter and the controller. Provides seven point-to-point communications between controllers and between controllers and DASD.

The unit of data transfer is a packet. The format of the packet is shown below. uni, control field (CONTROL), address field (ADDR) ESS), variable length data field (DATA) and CRC field ( C: RC).

-11 lower----7-----lower-7--lower-7--col FLAGI C0NT R0L IADDRESS IDATAjCRCI CRCIFLAIL-Ichiko --- 2-- can be used to execute multiple commands related to different DASDs at the same time. .

Full-duplex data transmission supports simultaneous transfer of read and write data. Ru. In reality, each serial link consists of two links providing data transfer in two opposite directions. each with a link. This is shown in FIG. According to Figure 7, each node is , an inbound link that receives input data and messages, and an inbound link that receives input data and messages. has an outbound link for sending messages.

This link has a simple protocol. Each node has its inbound its output according to the pacing responses and acknowledgments it receives from remote nodes on the link. Packets can be sent on bound links.

Packets on serial links can be classified into two types:

A message packet originates from a software process within a node and is sent to a destination node. (The process descriptions below relate to the operation of the control unit.) section and section on adapter operation). Message packets are usually , used for commands and situations (different types sent within message packets) messages are explained in detail below).

A data packet originates from a DMA channel within one node and is transmitted within a destination node. DMA channel as the destination. Data packets are typically read data or or write data.

Each packet has an address that indicates the source and/or destination of the packet. Contains fields. For further information on the operation of serial links, see the pending UK special note application See No. 9026338.5 and No. 9026336.9.

message A message is a packet on a serial link destined for a process in the destination node. It is. The first data byte of the packet (i.e., the data of the packet - The first byte of the field (l-) identifies the message. Subsequent bytes are It is a meter.

Most messages have a TAG as a parameter. to this Therefore, it is possible to associate a message with the corresponding command sent by the adapter. I can do it.

Message from adapter to control device SC3j COMMAND (S CS I command) r----1 lower 1 lower 1 lower 1111 lower 1-----Col MESSAGE C0DE ITAG 11SC 5I EXT 1DASD ADDR, ESS 11--11--Upper 112- 2------Upper 11---Hl DMA ADDR, ESS (Host memory ) ] 1−−−−−−−−−−−−−−−−−−−−−−−−−−@ICO MMA, ND DESCRIPTOR BLOCK IL--11111---- ---------~-1111'' This sets the SC3I command descriptor block to This is a message to be forwarded to the queue at the location.

DASD ADDrl, ESS (DASD address) executes the command. Identify the target storage device you plan to run.

5C5I EXT is ANS 1 specification "Small Co@puter Sys Provide extensions or modifications beyond the functionality provided by the TEMS document set . Setting this part of the message will cause split writing to DASD or control. Split read on adapter to device link is enabled.

DMA ADDRESS (DMA AT1/S) is the data for SC8I command. is the starting address in system memory of the data area.

COMMAND DESCRIPTOR BLOCK (CDB) descriptor block) is a command descriptor block for the 5C3I command. CD B contains one of the commands of the 5C3I command set.

READY-FOR-READ (readable) r-111111111- ------Col MESSAGE C0DE I TAG I LINK AD DRESS IL-111112112-J This message is sent as DATA-READY by the adapter. function) sent to the control device in response to a message.

The TAG specifies the commands associated with a particular READYJOR-READ message. identify LINK ADDR, ESS (link address) Identify the DMA channels allocated within the adapter for operation.

ABORT (termination) r-11-11-7”-1 1MESSAGECODE1TAG11TAG21L--11--Eng.--Eng. --” , the second message is ABOR”jSC3I (SC8-double) taken out from the host. Generated by the adapter when performing an operation (abort). TA, G1 is AB Identify the mailbox containing the ORT-3C3I command operation, and TAG 2 , identify the command to abort. This message sends a command to the control device. Terminates its execution if it is running, or terminates its execution if it has not yet started. causes the command to be removed from the controller's queue.

RESET (Reset 1-) r -'---'--711MESSAGE C0DE 1TAG ITYPE 1DASD ADDR, ESS IL-11111-11-- Engineering-J This message resets selected resources in the control unit or DASD. is sent from the adapter to the control device in order to

Message from control device to adapter 1MESSAGECODE ITAG I LINKADDRESS 1) -- ------121121----1--@lDMA 5TART ADDR,E SS (in host memory) 11----------------1------ @l DMA LENGTH (byte) IL J This connects the host's DMA, 5TART ADDR, ESS (D Data by DMA LENGTH (DMA length) from MA start address) This is a message that instructs you to forward the message. , LINK ADDR, ESS is 1. Identifies the DMA channel within the control unit that is the destination of the data packet. TAG identifies commands related to data.

l　MESSAGE　C0DE　I　TAG　1)To　m-１工------ --@ lDMA, 5TART ADDRESS (in host memory) lHea--- -----------1---------11DATA LENGTI(1 J This occurs if the adapter has not yet allocated a DMA channel to this TAG. commands the adapter to do that, and the specified DMA 5TART ADDR Transfer specified DMALENGTH to host memory starting from ESS This is a message instructing people to prepare. The adapter is READY-FORR In response with an EAD message, determine which DMA channel is the destination of the data packet. Informs the control device of what will happen.

5TATUS (Situation) r-11111 lower--lower 1--ko l MESSAGE C0DE ITAG l5TATUS 1 This is TAG A message conveying the 5C3I status generated when the command identified by It is Tsage.

Next, the main components of the control device and adapter will be described.

adapter hardware The main components of the adapter hardware are shown in FIG.

The core of the adapter is a microprocessor chip (MPC) 110. , which handles messages and data between the attached control unit and the host system. Contains a high-performance controller that controls the transfer of data. Also, if two identical adapters There are 120 link chips (ALC), each of which can hold two microchannel novels. Serial link and interface to 16 DMA channels (not shown) provide. Each serial link is connected to the commands, data, and It has four 128-byte packet buffers for data and status. MPC and The interface between the ALCs is an input/output bus 115.

The main components of the ALC are shown in FIG.

data RAM Data RAM 121 includes the following areas.

1) Eight 128-byte packet buffers (four for each serial link, two for each serial link) (one for outbound, two for inbound) 2) 16 8-byte DMA registers: one DMA register for each DMA channel. A register is provided. These registers are used during DMA data transfer.

3) 32-byte message buffer for outbound serial link messages. F: This buffer is used by a high-performance microprocessor to read the control device light. Used to create Y-FORREAD messages. appropriate hardware By setting, this buffer can then be sent to the control device.

4) Host interface register: Pass mailbox to adapter Three internal registers are involved in the process. Mailbox and adapter behavior The details of the work will be described later.

Mailbox pointer register: System can read and write 4-byte register. This points to the first mailbox in the chain. initialized by the stem. The current tag register is equal to the last tag register. The system clears this register at any time, or immediately after resetting the adapter. Only reading is allowed.

Current Tag Register: This is a 1-byte register that the system can read and write. It is a register. This allows the system to see the progress of the adapter. I'm going to growl. This register is cleared by an adapter reset and the host Also cleared immediately after writing the last tag register.

The adapter tags each mailbox after it completes processing the mailbox. Store in current tag register.

Final tag register: A 1-byte register that can be read and written by the system. Ta. This register allows the system to add some mailboxes to the queue. sometimes written by the system. This register is the last mailbox Indicates the tags included in. This allows the adapter to know when it has reached the end of the list. Ru. When this register is written, an interrupt is generated to the adapter. .

5) 32-byte DMA parameter to retrieve all mailboxes from host. 5CSI COMMAND, ABORT for controller/buffer controller and RESET messages are sent directly from the DMA buffer (READ Y FOR-READ messages are created in the message buffer and output (sent to the control unit via the bound link). DMA buffer is DMA Can be used to read and write host memory under your control.

Data RAM can be serial links, microprocessor or link-to-link transfers, and Time multiplexed between high performance microprocessors.

Situation RAM Each packet buffer requires its own packet status register (PSR) Ru. These registers are held in status RAM 122 and are 16 bits wide. . The packet buffer and associated packet status registers are shown in FIG.

Each register includes two fields:

DESTINATION - For outbound data packets If the contents of the corresponding packet buffer are Contains the value that is copied to the address field of the output packet when it is transmitted.

This value is used by the hardware when removing packets from the packet buffer in preparation for transmission. can be automatically loaded by software. Inbound packet)・ , this field is extracted from the address field of the input packet. Contains the address.

This value is written to the PSR by the inbound link's FSM (finite state machine). and its value is used to determine subsequent routing of this packet. .

BYTE C0UNT (byte count) - of outbound packets , this field contains the bytes located in the corresponding packet buffer. Contains a value that indicates a number. When the link sends out a packet, it uses this value as a data byte. A byte counter that is decremented each time a byte is sent (link hardware must be copied in part). The value in the PSR may change due to an error during transmission. packets must be retransmitted. Inbound - For packets, this field contains the data packet received within the input packet. Contains a value indicating the number of items.

Microchannel interface The Micro Channel interfaces with the host memory and has the devices defined above. data RAM host interface registers.

DMA channel Each ALC has 16 DMAs, channels numbered 0 to 15 (not shown). ). These channels are connected to the host I...memory and DMA packet buffers. It is used for DM and A transfer of data between servers.

Control device hardware FIG. 4 shows the main functional components of the control device. The core of the control device is the MP C chip 210, which has a high performance controller (RPC) and a data buffer. 220.

DMA bus 225 connects the DMA controller to two controller link chips 230. Connecting.

Data buffer 220: All data between the adapter and DASD is stored in this Pass through the data buffer. Also, this buffer is requested by the system It is also used to store read-ahead data in case the (Please refer to the relevant section). link packet buffer and data buffer 16 DMA channels (numbered 0 to IS) to transfer data between is provided.

Device (DA) There are two channels per link, SA (Serial Adapter) link There are four channels for each.

The data buffer consists of an array of DRAM modules. in this buffer Data is stored with the FCC to ensure data integrity. data bus Buffers are allocated in seven 32-byte segments per DASD. 1 unit When multiple tasks are executed on a DASD, each task has a different segment. will be allocated.

The high performance controller is a set of external registers implemented within the controller link chip. via the control interface to the control device. The input/output bus 226 used by the microprocessor to access these registers.

Static RAM 240 is used to execute programs.

EPROM250 stores microcode used in the operation of high-performance control equipment. Remember. The structure and operation of the microcode is discussed in detail below.

Control unit link chip (CLC) The main functional areas contained within the CLC are shown in FIG. These are as follows: Ru.

1) Two DASD series interfaces (DAO and DAl) 2) One Adapter Serial Interface (SA) 3) Link Packet Back 240 and associated packet status I register 242 Packet buffers are used to hold input and output data. Communicating To perform continuous link transfers, an A/B buffer implementation is used. by this , while link uses buffer A, DM A, logic circuit uses buffer B. It can be filled (or emptied) and vice versa. this link is full duplex, which means that the inbound and outbound links means that both require their own set of packet buffers. system The controller link chip contains three serial interfaces, so this A total of 12 packet buffers are required to service the column link. means. Microcode can create output messages within it, Additional packet buffers are also implemented (F per link). Using this , a high-performance microprocessor performs DMA transfer of one of the A/B packet buffers. without withdrawing from the service and thus negatively impacting ongoing data transfers. You will be able to create messages without having to

Each of the three links in the CLC can be one-bound, inbound, or Equipped with 5 packet buffers classified as packets. Outbound: Each link has two links serviced by DMA hardware. Provides an A/B outbound packet buffer. These buffers data buffer, DASD (DA link or adapter (SA link)) filled with data sent to the link).

Inbound: Each link also supports two A/B inbound packet packets. Equipped with fa. Incoming packets (from adapters or DASD) are DM buffer, depending on the contents of the address field of the input packet. A. Receive hardware or Spinica service.

Message: Each link interface also has a message packet Equipped with buffer. This is what the microprocessor sends to the adapter or DASD. used to create outbound messages.

4) DMA interface logic circuit: This is under the supervision of the DMA controller, A circuit that transfers data from the packet buffer to the controller data buffer. Ru.

DMA operation Data is transferred between the adapter and the controller buffer, and between the device and the controller buffer. The information is transferred by DMA between the two. The control device microprocessor A DMA controller that coordinates transfers between the link chip and the shared data buffer. include.

The controller link chip contains packet buffers in the CLC and controller data. - Built-in DMA interface for transferring data between buffers ing. DMA interface is contained within the microprocessor chip Monitored by the DMA controller. Microprocessor chips require DMA Contains a logic circuit that arbitrates between requests.

There is an arbitration phase before a DMA transfer, during which the CLC chip can generate a signal indicating a request for a DMA channel that requires service. Wear. The DMA controller issues a grant to one of these requests and then The CLC can initiate the transfer. Each controller link chip has eight DMA channels. can be used to service data transfer. These DMA channels The files are allocated as follows:

Channel 0.1 + DA link No. O (Figure 5 (7) DA O) Channel 2.3 : DA link No. 1 (DAI in Figure 5) Channels 4 to 7: Adapter link (5A in Figure 5) (The second CLC uses channels 8-15 in the same order as above. use ) Using this arrangement, up to two DMA channels can service each DASD. The adapter link can now service up to four DMA channels. You will be able to do it.

Use these channels simultaneously to take advantage of the packet multiplexing capabilities of serial links. can be done. Device links are given higher priority than adapter links. Ru. Using a DMA bus, data transfer speeds of up to 40 MB/s are possible become.

A 32 byte (DA) transfer from the packet buffer to the data buffer takes approximately It takes 1.2 microseconds. 3°6 microseconds for 128 byte (SA) transfer It takes.

During arbitration, each CLC issues a request on the DMA bus as follows: .

Storage (writing to buffer): Address of inbound link packet. If the field indicates that the data is destined for a DMA channel, then the packet A DMA request is issued upon receipt of a request.

(reading from a buffer): reading the link parameters associated with a certain DMA channel. If one or both packet buffers are empty, the A DMA request is issued.

DMA store operation: A DMA store operation empties the inbound packet buffer. used to make

DMA retrieval operation: A DMA retrieval operation is performed using the outbound packet buffer. used to meet the requirements. Each transfer typically uses one packet buffer. This is for the whole area.

command descriptor queue CDB (also including ABORT and RESET) the first time it is received. At the time of ivy, SA RECEIVE MESSAGE (SA receive message) command descriptor queue entries (CDQEs) under the control of the process.

Free queue: Initially, all CDQEs are free.

A free queue is one where one element points to the next It is a queue only in that it allows CDQE to be discovered. item The order of is meaningless.

New command queue: When a new command arrives, the SA task copy the command to the CDQE at the head of the free queue. This CDQE is empty Removed from queue and added to new command queue. Termination message is also placed in the CDQE and added to the new command queue.

Device command queue: There are four device command queues, one for each device. be. Each queue is run by its own COMMAND process. service.

The QUEUE MANAGER process waits for new commands. When a new command is found in the CDQE matrix, the device to which it is directed and forwards this CDQE to the corresponding device command queue.

Message queue: When the processing of a command is completed, the associated SC8: [Status message is loaded by the COMMAND process that CDQE is removed from the device command queue. The message queue is Therefore, SA TRANSM T MESSAGE (SA transmission message ) is a queue of requests for a process.

The same queue is used for commands received over different adapter links be done.

Queue linkage: Free queue, new command queue and message queue The column start and end pointers are located in the message control block (MCB). field.

The head and tail pointers of the device command queue are set to the corresponding device control It is in the block (DCB). The start pointer is the address of the first element in the queue. hold. The tail pointer holds the address of the last element.

Each CDQE includes a "next" pointer. CDQE is not included in any of the multiple queues. A CDQE may not be included in more than one queue at the same time. .

Next, the operation of the adapter and control device will be described.

adapter motion A task defined within a high speed microprocessor controls the operation of the adapter.

A task is started by an interrupt, which is caused by a hardware event. However, it may also be via a software interrupt from another task. software An interrupt is the ability for one task to set an interrupt for another task. It is a means of Communication between different tasks is shown in FIG.

task Status: The status task is responsible for managing the status to be presented to the host I... system. bear. Status is passed to this task from one of the other tasks and is It may also be presented directly by writing to the hardware.

Links; one link task to handle four serial links to the control unit There is a problem. This task interprets all messages received from the control device. , shall be responsible for taking appropriate measures.

Mailbox: The second task is to retrieve the mailbox from the host system. Manage interfaces. This task deletes each mailbox from the system. be responsible for receiving.

The mailbox is the 5END-SC5I (SCS I send) command. If so, it passes the command to the link task and sends it to the appropriate controller.

(There are other tasks defined, but they are not directly related to this explanation, so I will explain them here.) do not) When commanded by the host processor, the attacker extracts frames from host memory. commands and immediately transfers them to the appropriate control device for execution. command The mechanism for retrieving the code depends on the host system architecture and It changes depending on. Herein, the following mechanism is used on microchannels.

The host system uses mailboxes created in memory. Start subsystem operation. Each mailbox identifies a specific command Contains a unique tag that For example, a host performs certain behavior within a subsystem. When it wishes to start, the host will start its operation in the next available mailbox. and writes it to the final tag register.

Writing to the final tag register causes the mailbox in the adapter microprocessor to The box task is interrupted. The mailbox task uses host memory 3 of the designated one of the adapter link chips (mask chip) from 2-by I-D M A, the adapter to DMA transfer the mailbox to the buffer. commands to the adapter hardware. All messages from the host are sent to one or two It is intended for school chips.

Once in the DMA buffer, the mailbox task decrypt the mailbox to determine the type of behavior defined by the contents of that mailbox. and if it turns out to be a 5END-5C3I command, the mailbox message into a SO3jcOMMAND message for sending to the appropriate control device. be done. The SC5jc OMMAND message is the data of the message packet. - Sent over the link from a 32-byte DMA buffer in the field. this The address field of the packet contains the address of the destination. In this case, the destination is the control unit microprocessor. The command is to service the mask chip. If the command is directed to a control unit that has not been Copied to a DMA buffer in the ALC and sent over the serial link.

The host defines many different operations as well as 5END and 5C3I commands. However, many of them are performed by adapters and do not need to be sent to the controller.

However, two operations namely ABORT-3C5I COMMAND and RESE T is a suitable control device in the form of ABORT and RESET messages. passed to. For details on the format of these messages, please refer to the adapter/controller mentioned above. It is in the control device message list I.

ABORT-5CSI COMMAND and RESET operations depend on the adapter. It is basically processed in the same way as 5END 5C3I COMMAND. Mail The mailbox task decrypts the mailbox and sends it to A, BORT message or or RESET message from the DMA buffer to the appropriate controller. this place If so, the message is sent to the second ALC, depending on which control device it is addressed to. It may also be necessary to copy to a DMA buffer.

The adapter starts a timer every time it issues a command.

This allows commands to be executed without burdening the host system with numerous timers. Useful for detecting dislodgements and control equipment interruptions. Adapter idle tasks periodically Update the timer and check if the operation has timed out.

Control device motion The operation of the control unit is performed within the microcode contained in the Spinica microprocessor. This is done using tasks defined in .

Eight tasks are defined within this processor. For that, the following There is.

Four device (DA) tasks manage the interface with each device.

One SA task to manage adapters and interfaces with hosts.

Command control tasks are tasks related to overall control. The new 5csr command is , passed from the SA task to this task. This task waits for these commands. It is then queued, decoded, and sends the instruction to the SA task and the appropriate device task. SA Tas The task and DA task perform data transfer.

The controller uses the above tasks, but the SA task and the command control task are Expanded through the concept of Butask.

The controller can perform multiple tasks that are implemented as independent tasks or as subtasks within one task. process. Subtasks run under the control of a subtask scheduler be done.

FIG. 6 is a block diagram showing communication between different processes.

The control block is used during this communication as follows.

One process puts information in a control block and notifies another process. the latter A process accesses information within its control blocks. The control block is professional Bused between sessions.

control device process SA RECEIVE MESSAGE RXMSG) This process handles all messages sent from the adapter to the controller. 5C3I COMMAND, ABORT, RESET and and READY-FOR-READ (the format of these messages ). The message packet from the adapter is C Received in the LC's inbound packet buffer. Input packet address The contents of the field identify the packet as a message and Service performance control equipment. That message is a new COMMAND, If ABORT or RESET, 5ARECEIVE MESS The AGE process waits for a free command descriptor queue entry (CDQE). Copy to the beginning of the matrix. This CDQE is then used by the QUEUE MANAGER program. queued to the process. That message is READY-FORREAD In some cases, the message is sent to the appropriate SA XFER (SA forwarding) process. (i.e. the process associated with the device containing the data to be read) .

QUEUE MANAGER This process is a command SA RECEIVE MESSAGE process is a subtask of the SA RECEIVE MESSAGE process. Handle interrupts from Usually, the message is 5C3I COMMAND message. ABORT or RESET (7): is also available. SA　R ECEIVE MESSAGE process copies the message to CDQE. , after moving that CDQE from the free queue to the "new command queue". process, which then waits in the ``new command'' queue. to a device-specific queue and notify the appropriate command process. Ru. The QUEUE MANAGER process is connected to which COMMAND process. Perform some limited processing of the message to determine if it should be known.

COMMAND (command) The command process (one of the four subtasks of the command control task) , processes SC3I commands on the device command queue. command process has four running in parallel (one for each of the four supported devices) There is an instance of Typically, each process is addressed to its device. Process commands.

Each command process picks up one command from its queue and Process each individual command, making sure it is valid to run at this point. calls a routine that handles Validate that command and SA 2 commands, Pause until SA and DA are completed, Return SC3I status Normally, the SA TR, ANSMIT MESSAGE process is notified and the SC 8 Send the work status to the adapter.

Repeat this step for each command in the device queue until the device queue is empty. , then this procedure goes into a suspended state and the QUEUE MANAGER process restarts when it adds a new command to the queue.

DEVICE There is one process per device (implemented as a separate task). DA process The process handles the following requests from the COMMAND process.

1) Read The COMMAND process requests (reads) the command by calling the appropriate routine. process the command. This routine sets the 5EEK (seek) secondary finger to the appropriate ASD. issue a command, perform initial DMA settings, that is, allocate a DMA channel, and make it available for use. Calculate the available buffer size and, if there is space available, Prepare a command, issue it to the DASD, and the DASD Begins data transfer to the data buffer in the control unit. DMA At I Nos , passed to DASD in the READ subcommand and assigns it to the address of the input data packet. used within a field to identify the destination of the data.

2) Write At this time, the following requests and other special commands, such as the process format, may still be issued. If the command has not been executed, a 5EEK subcommand is issued.

3) Extension of current operation 4) Event stop The COMMAND process responds by notifying one of three events: and communicates with the DEVICE process.

NEWREQ Informs the device process that a new request has started.

EXTREQ This event is used to extend a request.

5TOP Instruct the device process to stop all work currently in progress .

Upon receiving a request from the COMMAND process, the DEVICE process: By sending the appropriate ASD subcommands on the serial link, you can Start appropriate measures.

DASD subcommands are low-level read/write subcommands generated by the controller. . The following subcommands are provided to enable the control device to read and write data. ing. Each of the subdirectives defined below is Sent to DASD via serial link. All "subdirective" packets are executed Microphones within the DASD for distribution to other components within the DASD destination processor.

10RDERC0DE ICYLINDERIHEAD IL-11--2-- 11th work 1-” This tells DASD to stop reading ahead (if active) and start reading the specified serial number. This is a subcommand that instructs the data and head to seek. Also, write command If a single seek subcommand is used, the controller immediately decodes the command Now you can start seeking without waiting for write data to be received from the adapter. I'm going to growl. Before the DASD completes a read subcommand or extended read subcommand (condition status packet is not returned), 5TOP (stop) subcommand is issued , DASD immediately aborts its read operation and 5TOP AND 5EEK R that started a seek to the cylinder and head specified by the subcommand and was aborted. , EAD (read) returns the status packet of the subcommand.

In the case of 5TOP subcommand, no status packet is sent.

Also, this subcommand is the ABORT-5I”:SI command from the adapter. When you receive the sage, it will be sent to DASD. In this case, the seek operation is It doesn't start.

READ sub-command Low -r'--Lower 1111--Lower 11 Lower 11-Co10RDERC0DE 1ADDRESS ICYLINDERIHEAD ILBAI COUNT 1 This is the DASD searches for a specific logical block address (LBA) and returns the specified number of blocks. This is a subcommand that instructs to read the block. The parameters are as follows.

Physical cylinder (CYLINDER) and physical head (HEAD) for seek inspection , the logical block address (LBA), and the number of blocks to read. Count (COUNT). Furthermore, the address field (A, DDRESS ) is the address of the entire data packet returned as a result of this subdirective. Contains the bytes placed in the field.

The DASD sends the requested data to the control unit and the FC at the end of each block. Examine the C byte. DASD encounters a block marked as defective If so, those blocks will be automatically skipped. Finally, the DASD Returns a status indicating whether or not the

C0NDTTIONAL R’EAD (conditional read) subcommand This subcommand is , has the same format as the READ subcommand, and has the selected cylinder and head - Call a seek operation to the address. Corresponds to the LBA included in this sub-directive The sector location is specified and the number of I/codes specified in the count field is , read from disk. The at1/s field is the result of this sub-command. Bytes placed in the address field of every data packet returned by Including.

CoNDI DIN10NA, JREAD subcommand is issued by the control device when: Only when the amount of read data requested by the host is greater than the selected amount Please note that. If the amount of data requested is small, C0NDITTON Use of AL READ is not guaranteed.

Use of this M command enables a divided reading operation, which will be described in detail below.

WRITE subcommand This searches for a specific LBA in DA, SD, and creates a specified number of blocks. This is a subcommand that instructs to write. The parameters are the READ subcommand (see above). (see), except that the control device supplies the data to be written. difference Additionally, there is no address field.

C0NDITIONAI, WRITE (conditional @ write mi) subcommand conditional write The read subcommand has the same format as the WRITE subcommand.

EXTEND subcommand r　””r-Ichige Ichi-ko 1ORDERCODEILBA1COUNTIL---11 工--- 工---" This is the previous READ subcommand, C0NDITIONAL-READ subcommand, WR Extends the operation of the ITE subcommand or C0NDITIONAL WRITE subcommand. This is a subcommand. "Count J (COUNT) is read after the current subcommand is completed. is a parameter that specifies the number of individual sectors that need to be read or written. .

LBA is a file that defines the address of the first block to be read or written. field. This value is used for previous sub-seconds if sequential reads or writes are required. than the LBA of the last block read or written by the command The value becomes one larger. The LBA field is the last LBA after the last LBA of the previous subdirective. If it is not the first block, blocks between these LBAs are skipped. and no reads or writes are performed.

For the EXTEND subcommand to take effect, the DASD must complete the previous subcommand. The EXTEND subcommand must be received before. The control device is EXTEN Use D to perform continuous writes or continue reading ahead. These actions are This will be explained in detail below.

When the entire operation is complete, the command process is notified of the appropriate events.

SA XFER (SA transfer) This is between the read rebuffer in the host and the control unit or between the host and the control unit. A per-device process that transfers data between write buffers. COMM The AND process can issue the following commands to the 5AXFER process: .

5end Read Data (send read data) Get Write D ata (write data acquisition) Stop Current Transfer (Current transfer stopped) The parameters necessary to execute the data transfer are stored in the control block. Passed from the MMAND process to the SA XFER process.

SA TRANSMIT (SATXMSG) This is used by other programs. Message on behalf of Rocess (READY FOR-WRITE, DATA- READY order 5 TATUS) 7. READ Y FORWRITE DATA READYt! , SA The 5TATUS message is passed to this process from the COMMAND process. Passed from.

Examples of read and write operations Next, it begins with receiving commands from the host and ends with presenting completion status to the host. Examples of typical read and write operations are given below.

Example of read operation Adapter Control device DASD SC5I COMMAND (READ 4K) --> Queue command Registration decrypt command search command Convert LBA to physical aviles Prefetch stop ＜−−−−−−−−−−−−−−−−−−3TATUS hub hub allocation　 seek Initialize DASD DMA C0NDIT 0NAL READ (32K) ->・Seek complete LBA search reading <−−−−−−−−−−−−−−−−−The first data is in the DATA buffer. enter Initialize host 1-DMA Initialize SA DMA <---1~---------DATA Send the last data of PACKETS <------------5CSj STATUS Register status in queue EX TEND (4K) −−−−−−−−−−−>・Show the situation Look-ahead data - Safe data <---------1----------STA reading S 1. The adapter has a 5CSI COMMAND message that includes READ operation in the CDB. Send the message to the control device. This message is sent to the DA from which the read data is being transferred. Contains the address of the SD and the address in host memory to which the data will be sent. nothing.

2. The controller processes the command as described above and passes control to the device task. child The device task sends 5TOP-AND-5EEK subcommands to DA and SD. . This causes any currently active read-ahead operations to be aborted. , (currently active If there is no state read-ahead operation, this subcommand will not be sent.)

3. The DASD returns 5TATUS indicating the abort status of the prefetch operation to the control device, Then, seek to the specified head and cylinder is started.

4. The device task of the controller segments 32 for the read data to be transferred. allocate a data buffer for This device task also handles controller data Allocate a DMA channel to use for data transfer to the buffer.

S, in this example, the device task then determines the address of the allocated DMA channel. , the data start address and the number of blocks to be transferred. Send L-READ subcommand to DASD. As mentioned above, the requested data If the amount is small, use "COMMUNICATION" instead of C0NDITIONAI and READ subcommands. The usual J READ subcommand is sent.

6゜When receiving the C0NDITIONAL-READ subcommand, the DASD Search BA and start data transfer. Data packet address fee The field contains the address of the DMA channel.

7. The read data is transferred to the controller via the serial link and the controller data ・It is placed in a created space in the buffer.

8. Is the control device connected to the adapter? Send an EADY message and the result , used by the host to transfer read data between the control unit and host memory. Initialize the host DMA channel to be used. In the above flowchart, the first data The DATA READY message is sent after receiving the data in the buffer. , but this message is sent before the data is received in the buffer. It is normal to The purpose of this message is to initialize the host DMA. , that is, to prepare the host to receive data.

9. The adapter responds to the DATA-READY message by opening the control bag RL'. - Send R, EADY FOR, READ message. READY in host -FOR,R,EAD message identifies the initialized DMA channel and is received by the control unit's SARECErVE message process. and passed to the SA XFER process. This SAχFER process is Initialize the DMA, i.e. use it to transfer data from the data buffer. allocate a DMA channel.

10. When data is received in the data buffer from DASD, it is serially linked. transferred to host memory via the network.

When the last data is sent, the control device reads 5CSI 5TAT? JS adapter Return to. The adapter queues this status and presents it to the host.

Example of write operation Adapter Control device DASD SC3j COMMAND (WRITE) -> Register command in queue decrypt command Convert LBA to physical address Prefetch stop <−−−−−−−−−−−−−−−−−− Allocate STATUS buffer seek Initialize DASD DMA Data packet −−−−−−−−−−−−−−−−−>The first data is enter hubfa DA Initialize DMA C0NDITIONAL WRITE ----> Data packet - −−−−−−−−−−−>LBA search EXTEND −−−−−−−−−−−−−−−−−>・<−−−−−−−−− -------1 status <-------------5CSjSTATUS status Join the queue present the situation writing 1. The adapter sends the 5C5I COMMAND message that defines the write operation. Send to control device.

2. The control device processes the command (as described above), and the control Passed from D process to DEVICE process. In this example, the DEVICE Rocess sends D A S D 1 m 5 TOP 'AND 5 EEK sub-command (A read-ahead operation is currently active).

3. The DASD stops read-ahead and controls the status indicating the abort of read-ahead operation. send to D A, SD were specified by the 5TOP-AND-5EEK sub-command Begin seeking to cylinder and head.

4. The control unit's SA XFER process allocates space in the data buffer. The SA DMA channel is the destination for write data packets from the host. Initialize.

5, 5A XFER process notifies SA TRANSMIT process, This SA TRANSMIT process sends READY FOR-WR to the adapter. Send an ITE message. This message is the D This is a message that identifies the MA channel.

6. D used by the adapter's link task to transfer data to host memory Allocates an MA channel and then transfers write data packets to the controller. Start sending.

7. The device task of the controller transfers data between the data buffer and DASD. Initializes the DMA channel used for the Identify BA and amount of write data t6 C0NDITIONAL-WRITE secondary finger DASDI: Send the command. DASD starts LBA search.

8. When the write data is received in the buffer via the DMA channel, from the fiber to the DASD via a serial link on a second DMA channel.

Look ahead A read ahead is a set of READ commands that together constitute one long sequential read. This is a function provided by the control device to improve performance. This is as below Continue reading from DASD to the controller's buffer in anticipation of the next read. This is achieved by

Upon receiving a 5C3I READ command, the controller will allocate this read. Add as many sectors as required for the segment's data buffer to 32 of the control unit being installed. Instruct DASD to transfer. In this embodiment, the controller typically 32 data (i.e., even when commands from i.e., the amount of data that fills the allocated buffer space). requested by host When the data arrives from the DASD, it is transferred to the host. requested data A status is generated by the controller when the data has been transferred to the host. During , the transfer of read-ahead data continues.

READ subcommand to DASD with more data than requested by host was specified, the extra data is stored in the controller buffer.

Sent by the controller to the DASD when the host makes buffer space available. The EXTEND subcommand extends the data transfer. EX, TEND secondary finger Upon receiving the command, the D.A.S.D. data to the new end of the buffer.

As an example, a READ command sent from the adapter will contain data in 4 (8 sectors). If the controller requests 32K from the device, the requested 4K At the same time that 4 data are transferred to the host, 4 spaces are created in the buffer. system The controller sends an EXTEND secondary requesting new data to 4 to fill the buffer. Send commands to the device.

When the next READ command is received from the adapter, the controller checks the buffer. check to see if the requested data already exists (or will soon exist). ). If so, the controller transfers the data to the host. send If not, the controller instructs the DASD to do a new read; Abort if there is an active read ahead. Is the DASD commanded for new transfer again? Otherwise, read-ahead continues until the read-ahead buffer is filled.

Continuous writing Continuous (back-to-back) writing refers to sequential writing of successive blocks. This is the write command. The first block of a subsequent write is the last of the previous write. Immediately following the block of Additional support will otherwise cause the DASD to rotate during commands. However, D A and SD can now be written without rotating. Ru.

The command-specific routines for the WR and TTE commands can transfer currently active device transfers. When it reaches a point where it can be extended to include the next consecutive write, this rule Chin “looked over his shoulder” and said that his next CD, QE, would contain such writing. Inspect whether or not. If so, this routine issues an extension request to the device task. Then, the device task sends an EXTEND subcommand to DAD. D A, If SD receives the EXTEND subcommand before completing the previous write, , the DASD simply updates the current write count with the count of the EXTEND subcommand. Extend by the amount specified by the mount parameter.

If the EXTEND subcommand reaches DA, SD too late, DASD Present the situation after the first write in normal form, then indicate the "failure" situation and correct it. Rejects the EXTEND subcommand.

In that case, the controller generates a normal write. The EXTEND subcommand itself The body is a candidate for extension.

example The host sends an scsr write command for sectors ○ to 7.

The control device issues a WRITE sub-command for sectors 0-7.

The host sends an SC3 write command for sectors 8-15.

A controller detects consecutive writes in the queue.

The control device issues an EXTEND subcommand for 8 sectors.

If the EXTEND subcommand arrives before the end of WRITE, this DASD Extends its current block count by 8, returns no status after sector 7, and Instead, return status after sector IS.

If the EXTEND subcommand arrives too late, this DASD Generate the normal situation for and control that the EXTEND subcommand was received too late. to the control device. In that case, the control device will write the WRITE sub for sectors 8 to 15. Reissue the directive. Sectors 8-15 are then written during the next rotation.

In a continuous write implementation using the EXTEND subcommand, the serial link packet In other words, the control device sends write data to DA and SD. It is possible to send the EXTEND subcommand via the serial link at the same time as sending the EXTEND subcommand to Please note that you must be able to.

split read Split reading means reading from three DAs to the first sector in the range of the current READ operation. (starting from the first sector included in that range that appears under the head This is the performance improvement obtained by For example, sector 4.5.61. ,．． 1 5.16, the head happens to arrive too late to read sector 4. but if it is fast enough to read sector 6, then 6.7.811. . , It can be read in the order 15.16.4.5. Therefore, DASD is 11 sectors (i.e., 16-5) faster than otherwise. It should complete quickly.

This optimization commands the controller to read the first sector of DASI:N:,i. This is achieved by A DASD has a sector whose sectors are milliseconds), the read is aborted and the current LBA is returned to the control device. In that case, the controller must either reissue the same read or also divides the read into a "tail" read, which transfers from the current sector to the end, and a "tail" read, which transfers from the current sector to the end. Determine whether to divide the data into "start" reading, which transfers data from the data to the beginning of the end.

To support this, C0ND IT l0NA5R for DASD, EAD secondary finger can be used for all commands. This subcommand is used if there is a long delay before the first sector. If so, it will be terminated. In the above example, if the data is read in normal order (arrives at the controller buffer 11 sectors earlier than If the data sent to the host must be rearranged into the normal order, split The performance benefit of read operations is significantly reduced6 The techniques described herein eliminate the need to reorder data within the controller buffer. By doing so, the potential of "divided reading" can be brought out even more. child It defines a message interface between the control device and the adapter and This is accomplished by giving the controller the necessary control over the host DMA address. It will be done. In practice, the controller has random access to host memory. have The data is read from the controller when it is placed in the controller's data buffer. The DATA-READY message sent to the host Specifies an address in default memory. When a split read operation is in progress, the control The location is the modified starting address from the address sent in the original command from the host. Calculate the response and include this address in the DATA READY message. Send to host. In the above example, the control device is informed of the starting address of sector 4. Therefore, the first sector of the split read data (sector 6 in this case) is sent. The corrected address in the destination host can be calculated. sectors 6 to 16 If it is already in the data buffer, the controller sends a single DATA READ A Y message is issued and transfer of sectors 6 to 16 is started. sectors 6-16 The transfer is complete. When the control device obtains sectors 1 to 5 in the buffer, DATA-R An EADY message is issued to the host and sectors 1 to 5 are ready for transfer. indicates the host memory address to which sector 1 is to be sent.

raw data reading The controller can randomly access areas of host memory, i.e. The ability to control the host address also provides other performance benefits. D During a read operation where the ASD is transferring multiple sectors of data to the controller buffer Then, the DASD waits until the end of one sector (512 bytes) and checks the FCC. before sending the sector to the host. In the system described here, the DASD does not have enough buffer storage to hold one sector's worth of data. data is read serially from disk and compiled into 128-byte packets. and sent to the control device. When the sector ends, the device checks the ECC and Add 6 ECC bytes to the end of the data. All data in that sector If the data is ``good'', no error is indicated and the controller stops transmitting to the host. continue. In this system, before the device sends the final packet of data to the control device, Therefore, before the device knows that the data contains an error, the data Note that most of that sector has already been transferred from the controller to the host. I want to be. Therefore, data already in the host is "raw" data, i.e. That is, no checks are performed before forwarding to the host.

In most data transfers, raw data is also good data. In other words, that data is transferred from the device. Transferring data directly to the host without inspection , compared to traditional systems that inspect every sector before transmitting it to the host. performance benefits are brought about. This direct method allows you to host many sectors of data. The time it takes for one sector of data to move from the device to the host The amount of time saved is approximately equal to the time required for The system described herein In any high-performance system, this benefit can significantly reduce overall overhead. can be reduced.

As mentioned above, most data transfers involve sending the raw data and then sending the verified data. Provides performance benefits compared to data. The trade-off with this is This is a performance degradation when there are errors in the transferred data. In some conventional systems, If there is one error in the data, the entire data must be retransmitted. . In the present invention, the control device has random access rights to the host memory. , there is no need to retransmit all of the data.

At the end of a sector, the DASD detects that there is an error in its data. If the Get out. When the controller has finished sending the current packet data to the host, it and sends a DATA RETRY message to the host. . The controller requests retransmission of the sector containing the error. DASD is essential The requested sector is put into a 128-byte packet and retransmitted to the control device. The device stores the data in a buffer. The retransmitted block of data is If so, the controller passes the data to the host.

The controller specifies the address in host memory to which retry data is to be sent. Send a DATA RETRY message to the adapter. This DATA RETR Y messages are used by the adapter to transfer data to host memory. This message instructs to set up a new DMA channel. adapter In response to this DATA RETRY message, the data Respond with AD message. DATA RETRY message will be retried Indicates the amount of data.

If the retry data sent to the controller still contains errors, the controller Re-request the data as many times as required.

If the controller still does not receive good data after a predetermined number of attempts, the control The control device attempts to correct errors in the data held in its buffer. child For this purpose, the controller sends an "action on rECC" subcommand to the device. This secondary finger The command causes the device to calculate which bytes are in error and also Calculate corrected data. The number of bytes that can be corrected is implementation dependent. Honmei In the detailed system, that number is 2 bytes. The device sends correction information to the control device. The sending controller corrects the data held in its buffer. After that, the control The controller sends a block of data containing the corrected bytes to the host.

host FIG.1 FIG.2 FIG.3 1-IPc DASD link 7 dabuta link FIG.5 FIG.6 FIG.7 data storage subsystem and Data transfer to and from the host I...system from the data storage system to the connected host. Techniques for transferring data to a host data processing system are disclosed. this sub The system supports one or more direct access storage devices, such as disk drives. A connected device controller is provided. The system transfers data to this subsystem Issue commands to initiate data transfer between the system and the device. reading day data or write data from the device to the host I via a buffer in the control device. transferred directly. For read operations, the read command data and the starting address in host memory to which it is sent. Device The control device corrects the start address to the address to which the data is actually sent. have the ability. This provides performance benefits in case of piecemeal data transfers. It will be done. Additionally, if an error occurs during a read operation, the controller 1゜International search report DrT that allows you to specify the host address to which the report will be sent /l’! Q (H)nn+cc

Claims (7)

[Claims] 1. A device control that is communicatively connected to a direct access storage device that stores data. from a data storage subsystem with a device to an attached host data processing system. A method of transferring data to a system, the method comprising: The sequence of data blocks to be transferred and the first block of the data sequence. A data transfer command that specifies the starting address in host memory to which the block is to be transferred. sending a code from the system to the equipment controller to initiate data transfer; A system that transfers sequences of data from a subsystem to a system in response to commands. the ability for the controller to respecify the starting address in host memory. A method of transferring data that has the power. 2. A control device facilitates the transfer of said data sequence from the device in a non-sequential order. request and the control unit uses the starting address specified by the host to Modified starting address in host memory to send the first block of data to: , the controller transfers the data to the host in non-sequential order, and the first 2. The block according to claim 1, characterized in that the block is sent to a modified starting address. How to transfer your data. 3. The controller transfers data from the device in the same order specified in the command. the controller sends the first block of said data sequence to the host. The method of transferring data according to claim 1, wherein the data is sent to a specified address. 4. When an error is detected in a part of a data sequence, the controller requests the device to retransmit the address specified in the command from the host. to calculate the address in host memory to send the retransmitted portion to 4. A method for transferring data according to claim 3, characterized in that: 5. The control device determines whether said part is received in the host without error or request retransmission of said portion until a predetermined number of retransmission attempts have been made, and in the latter case If so, the controller requests correction data from the device and corrects the error in the part. the corrected part using the address specified in the command from the host. 5. The method according to claim 4, further comprising calculating an address in host memory to which the message is to be sent. How to transfer the data described. 6. comprising a device controller communicatively connected to a direct access storage device; When data is transferred from the device, through the controller, to memory in the data processing system. The data accessible by the attached host data processing system being transferred. a data storage subsystem for storing data, wherein the control device characterized by having the ability to specify the starting address in host memory of the destination data storage subsystem. 7. The controller controls the data transfer used to transfer data from the device to host memory. 7. The data storage subsystem of claim 6, including a buffer.