JPH0548902A - Image data compressor - Google Patents

Abstract

PURPOSE:To suppress the picture quality deterioration and to hold the high picture quality by erasing the number of the processing blocks at the time of the image with fine patterns and increasing the code quantity for the block to be processed. CONSTITUTION:At a first pass, an activity sum S equivalent to one screen outputted from an integrating circuit 16 is supplied to a processing block deciding circuit 28, the number of the processing blocks is decided based on this and the processing block pattern corresponding to it is selected. At this time, as the sum S is increased, the processing block pattern with the small number of the blocks is selected. The address data in correspondence to the deciding processing block pattern are sent to an image memory 13, at a second pass, the image data are read from the memory 13 based on the address data, and by a regularization factor alpha generated in accordance with activity sums S1, S2 and S3 selected by a selecting circuit 29 at the first pass and the bit distribution result, the encoding processing is executed. Thus, the picture quality deterioration can be prevented for the image with fine patterns.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an image data compression apparatus for compressing digitized image data by using an orthogonal transformation system for recording or transmitting it in a storage medium system.

[0002]

2. Description of the Related Art As is well known, in the field of image equipment, data is orthogonalized in order to convert the image signal into digitized data and record or transmit it in a storage medium system using a semiconductor memory or the like. Data compression is performed using a conversion system.

FIG. 4 shows a conventional image data compression apparatus using such an orthogonal transformation system, and the data compression processing is performed in two passes. That is, reference numeral 11 in the drawing is an input terminal to which an analog image signal is supplied. The image signal supplied to the input terminal 11 is A / D (analog /
It is supplied to the (digital) conversion circuit 12, converted into digital image data, recorded in the image memory 13, and then read out in units of 8 × 8 blocks, for example.

As the processing of the first pass, first, the digital image data read out in block units from the image memory 13 is supplied to the DC (direct current) component extraction circuit 14, and the DC component is extracted from the average value in the block. While being obtained, it is supplied to the activity calculation circuit 15 and the activity indicating the amount of change in each block is calculated. The activity calculated by the activity calculating circuit 15 is supplied to the integrating circuit 16 to obtain the activity sum S for one screen.

As a method of calculating the activity, a parameter for determining a normalization factor α and a bit allocation, which will be described later, by passing digital image data read in block units from the image memory 13 through a BPF (band pass filter). It is executed by extracting data, taking the absolute value of this parameter data, and integrating by one block. Note that standard deviation, peak-peak, or the like can be used as the means for extracting the parameter data.

Then, the quantization step size is determined. That is, the normalization coefficient table 17 that is experimentally obtained in advance is provided, and the normalization coefficient table 17 is provided.
Of the normalizing factor generating circuit 18 based on the output of 1 and the activity sum S for one screen output from the integrating circuit 16.
The quantization step is obtained by multiplying the normalization factor α generated in 1) by the multiplication circuit 19. Note that as the activity sum S increases, the normalization factor α
Is also set to be large. The processing up to this point is the one-pass processing.

Next, encoding is performed in the processing of the second pass. That is, digital image data is read again in block units from the image memory 13, and the activity sum S for one screen obtained via the activity calculation circuit 15 and the integration circuit 16 is supplied to the bit allocation circuit 20. The bit allocation circuit 20 is provided with the input activity sum S for one screen and the activity calculation circuit 1 described above.
Based on the activity of each block calculated in step 5, the number of bits given to each block is proportionally distributed.

Further, the digital image data read out from the image memory 13 in units of blocks is processed by the orthogonal transformation circuit 21.
Is supplied to the encoding circuit 23 after being quantized by the quantization circuit 22 based on the quantization step obtained in the processing of the first pass. The encoding circuit 23 is supplied with the normalization factor α generated by the normalization factor generation circuit 18 and the output obtained by quantizing the output of the DC component extraction circuit 14 by the quantization circuit 24, and The output of the bit allocation circuit 20 is the addition circuit 2
5 is supplied.

Then, the encoding circuit 23 Huffman-encodes the output data of the quantization circuit 22 so as not to exceed the number of allocated bits calculated by the bit allocation circuit 20, and outputs it via the output terminal 26.

Here, in the encoding process by the encoding circuit 23, because of the variable length encoding,
It is known that the number of bits actually used for encoding is smaller than the number of allocated bits in most blocks. Therefore, the number of allocated bits output from the adder circuit 25 and the number of bits used for encoding by the encoding circuit 23 are supplied to the subtraction circuit 27 to obtain the difference between both bit numbers, and this difference is a surplus. The bits are supplied to the adder circuit 25 and added to the allocated bit number of the next block output from the bit allocation circuit 20. Less than,
The surplus bits generated at the time of encoding are sequentially carried over to the allocated bits of the next block.

However, in the conventional image data compression apparatus as described above, although the deterioration of the image quality is suppressed to some extent by allocating the bits to each block, an image with a large change and a fine pattern is smooth and flat. There is a problem that the deterioration of an image becomes more severe than that of a normal image.

[0012]

As described above, the conventional image data compression apparatus has a problem that an image with a fine pattern is more deteriorated than an image with a flat pattern.

Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to provide an extremely good image data compression apparatus capable of maintaining high image quality even for images with fine patterns.

[0014]

An image data compression apparatus according to the present invention divides digital image data into predetermined block units, performs orthogonal transformation and quantization processing on each block, and outputs 1 activity of each block. It is intended for those that perform encoding processing according to the number of distributed bits of each block determined based on the sum of screens. And as the activity sum for one screen increases, 1
The number of processing blocks on the screen is reduced, and the bit rate for the blocks to be processed is increased.

[0015]

According to the above configuration, the fineness of the pattern is judged from the activity sum for one screen, and the number of processing blocks is deleted for the image with more activity sum, that is, the image with the smaller pattern, and the block to be processed is deleted. However, since the bit rate (code amount) is increased, it is possible to suppress the image quality deterioration and maintain the high image quality even for an image with a fine pattern.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. 1, the same parts as those in FIG. 4 are designated by the same reference numerals. That is, in the first pass, the activity sum S for one screen output from the integration circuit 16 is supplied to the processing block determination circuit 28.
The processing block determination circuit 28 determines the number of processing blocks based on the input activity sum S, and selects a processing block pattern corresponding to the number of blocks.

This processing block pattern is shown in FIG.
Three types shown in (a), (b), and (c) are prepared in advance. That is, when one screen is a horizontal H block and a vertical V block, FIG. 2A shows a processing block pattern without block deletion in which the number of processing blocks is H × V, and FIGS. 2B and 2C. Indicates a processing block pattern with block deletion in which the number of processing blocks is H × (V−n) and (H−n) × (V−n), respectively.

Then, in the processing block decision circuit 28,
As shown in FIG. 3, as the activity sum S for one screen increases, the processing block pattern with the smaller number of blocks is selected. Further, the integrator circuit 16 is provided with integrators corresponding to the above-mentioned three types of processing block patterns, and the activity sums S1, S2, and S3 corresponding to the respective patterns are respectively obtained and supplied to the selection circuit 29. . This selection circuit 29 has an activity sum S1, corresponding to the processing block pattern determined by the processing block determination circuit 28.
It is operated so as to derive S2 and S3 to the normalization factor generation circuit 18 and the bit allocation circuit 20.

From the processing block decision circuit 28,
Address data corresponding to the determined processing block pattern is sent to the image memory 13, the image data is read from the image memory 13 based on this address data in the second pass, and selected by the selection circuit 29 in the first pass. The encoding process is performed based on the normalization factor α and the bit allocation result generated according to the activity sums S1, S2, and S3.

Therefore, according to the configuration of the above embodiment, the fineness of the design is judged from the activity sum S for one screen, and the number of processing blocks is deleted for the image having the larger activity sum S, that is, the finer the design. As a result, the bit rate (code amount) can be increased for the block to be processed, and the quantization step can be reduced, so image quality deterioration is suppressed and high image quality is maintained even for images with fine patterns. can do. Further, with respect to the deleted block portion, a measure such as adding black level data at the time of reproduction may be taken. The present invention is not limited to the above-described embodiments, but can be variously modified and implemented without departing from the scope of the invention.

[0021]

As described in detail above, according to the present invention,
It is possible to provide an extremely good image data compression device that can maintain high image quality even for images with fine patterns.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image data compression device according to the present invention.

FIG. 2 is a diagram showing an example of a processing block pattern of the same embodiment.

FIG. 3 is a diagram showing a relationship between an activity sum S and a processing block pattern of the embodiment.

FIG. 4 is a block configuration diagram showing a conventional image data compression device.

[Explanation of symbols]

11 ... Input terminal, 12 ... A / D conversion circuit, 13 ... Image memory, 14 ... DC component extraction circuit, 15 ... Activity calculation circuit, 16 ... Integration circuit, 17 ... Normalization coefficient table, 18 ... Normalization factor generation circuit , 19 ... Multiplier circuit, 20
... Bit allocation circuit, 21 ... Orthogonal transformation circuit, 22 ... Quantization circuit, 23 ... Encoding circuit, 24 ... Quantization circuit, 25 ... Addition circuit, 26 ... Output terminal, 27 ... Subtraction circuit, 28 ... Processing block determination circuit , 29 ... Selection circuit.

Claims (1)

[Claims] 1. Allocation of each block determined by dividing the digital image data into a predetermined block unit, performing orthogonal transformation and quantization processing for each block, and determining the sum of the activity of each block for one screen. In an image data compression device that performs encoding processing according to the number of bits,
As the activity sum for one screen increases, 1
An image data compression apparatus, which is configured to reduce the number of processing blocks on a screen and increase a bit rate for blocks to be processed.