JPH0548664A - Delay detection circuit with soft judgement error correcting circuit - Google Patents

Abstract

PURPOSE:To provide a delay detection circuit with a soft judgement error correcting circuit for DQPSK and PI/43 shift QPSK which are appropriate to travelling object communication. CONSTITUTION:A digital orthogonal demodulating part 4 and an absolute phase detecting circuit 10 directly detect an absolute phase as against a reference signal in the absolute phase detecting circuit 11 and detected phase difference between successive reception symbols is detected by a phase difference calculating circuit 11. The quantization converting part 13 of phase difference data where the phase difference data between the reception symbols is quantized on a phase plane and a soft judgement error correcting circuit 16 directly detect the phase at every time t=kTs (k is an integer, Ts is a symbol and data time interval) of reception modulation wave and difference between the phase of reception modulation wave in time t=kTs and the phase of reception modulation wave in time t=(k-1) Ts which is one symbol time in advance is detected. Thus, transmission symbol and data information is obtained and phase difference data is quantized on the phase plane in accordance with the signal point arrangement of modulation wave so as to correct a soft judgement error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase modulation wave such as differentially coded 4-phase phase modulation (hereinafter abbreviated as DQPSK) or π / 4 shift 4-phase phase modulation (hereinafter abbreviated as π / 4 shift QPSK). The present invention relates to a differential detection circuit with a soft-decision error correction circuit, which is used in a device for receiving the.

[0002]

2. Description of the Related Art In recent years, mobile communication systems such as car telephones using differential coded phase modulation such as DQPSK and π / 4 shift QPSK and time division multiplexing have been studied in mobile communication. As the demodulation system of the differentially encoded phase modulated wave, the carrier signal of the digitally modulated wave is regenerated in the demodulator, and the differentially encoded phase modulated wave received based on the regenerated carrier signal is synchronously detected, A synchronous detection demodulation system that differentially decodes the obtained symbol data and a differential detection demodulation system that demodulates the transmitted digital modulated wave by utilizing the fact that there is transmission information in the phase change between the preceding and following symbols. Are known. In mobile communication, the radio transmission line is a fading transmission line as is well known. In a fading transmission line, generally, the carrier signal has a Rayleigh distribution in amplitude and a random uniform distribution in phase. When a differentially encoded digital phase-modulated wave is transmitted through such a fading transmission line and demodulated by a coherent detection demodulation system, it is generally difficult for the carrier reproduction system to completely follow random phase fluctuations. The demodulation characteristics are worse than in the detection demodulation system.
For this reason, a differential detection demodulation system is generally used as a demodulation system for differentially encoded phase modulation in mobile communication.

A conventional differential detection demodulation system will be described below with reference to FIG. 4 for the case of π / 4 shift QPSK modulation. In the case of DQPSK modulation, FIG.
-45 after delay element 43 and before multiplier 46 at
A delay detection demodulation system can be constructed in the same manner by adding a phase shifter of °. ("Digital Communication" McGrow Hill, 1983, John
G. FIG. 4 shows a conventional differential detection demodulation system for .pi. / 4 shift QPSK modulation, which is processed in the intermediate frequency band. In FIG. 4, 4
2 is a BPF, 43 is a delay element having a symbol rate interval Ts, 44 is a 90 ° phaser, 45 and 46 are multipliers, 4
7, 48 LPF, 49 symbol clock regenerator, 5
Reference numerals 0 and 51 are determiners, and 52 is an error correction circuit.

The operation of the differential detection demodulation system configured as described above will be described below. First, the received modulated wave input to the input terminal 41 is band-limited by the BPF 42 that suppresses wideband noise, and then delayed by one symbol rate interval time Ts by the delay element 43 having the symbol rate interval Ts. The 90 ° phase shifter 44 is phase-shifted and becomes one input of the multipliers 45 and 46, respectively. The other input of the multipliers 45 and 46 is
The output of the BPF 42 is input as it is. The outputs of the multipliers 45 and 46 are supplied to the LPF 4 for removing high frequency components.
After being low-passed by 7 and 48, they are input to decision devices 50 and 51. At this time, time t = (k-1) T
The received modulated wave at s is Vk−1 = Acos (Wct + φk
−1 + θ) + Nn−1, and the received modulated wave at time t = kTs is Vk = Acos (Wct + φk + θ) + Nn, the outputs of the LPFs 47 and 48 are A ² co respectively.
s (φk−φk−1) + Nn · Nn−1 and A ² sin
(Φk−φk−1) + Nn · Nn−1, and FIG.
Depending on the bit map corresponding to the phase shift of π / 4 shift QPSK shown in (a), the decision units 50 and 51 are
Then, determination is made for each symbol clock reproduced by the symbol clock regenerator 49. Here, φk−1, φk and Nn−1, Nn are time t = (k−1) T, respectively.
It is the phase and noise of the transmitted modulated wave at s, t = kTs. Further, θ is a fixed phase shift in the receiver, and Wc is a carrier angular frequency. Then, the judgment output is input to the error correction circuit 52 and decoded to obtain the bit output of the demodulated data. Here, in general, when a soft-decision error correction is performed by an error correction circuit by quantizing the decision output into a multi-value by an A / D converter, an error rate characteristic is improved as compared with the case where binary hard-decision error correction is performed. It is known to be possible. For example, in a channel under additive white Gaussian noise, when soft decision error correction is performed by quantization of 3 bits using a convolutional code,
The error rate characteristic is improved by about 2 dB as compared with the case of performing binary hard-decision error correction.

[0005]

However, the above-mentioned conventional structure requires a delay element having an accurate symbol rate interval in the intermediate frequency band and a 90 ° phaser in the intermediate frequency band. In addition, there is a problem that an A / D converter is required to perform soft decision error correction.

The present invention solves the above-mentioned problems of the prior art and is a soft-decision method capable of error correction, which is suitable for mobile communication, with respect to digital modulation systems such as DQPSK and π / 4 shift QPSK. An object is to provide a differential detection circuit with an error correction circuit.

[0007]

In order to achieve this object, the present invention detects the absolute phase with respect to an internal reference signal from a received phase modulated wave, detects the absolute phase of the received symbol, and the received symbol. Means for detecting a phase difference from the absolute phase detected one symbol data time interval before;
And a phase quantization conversion means for quantizing the phase difference data obtained by the differential detector on the phase plane.

[0008]

The present invention has DQPSK and π due to the above configuration.
For / 4 shift QPSK or the like, by performing quantization on the phase plane according to the signal point arrangement of the modulated wave, it is possible to realize a delay detection circuit capable of soft-decision error correction.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block connection diagram of a differential detection circuit with a soft decision error correction circuit according to an embodiment of the present invention. In FIG. 1, 1 is an input terminal, 2 is a BPF, 3 is a limiter, 4 is a digital quadrature demodulation unit, 5 is a 1/4 frequency divider,
6 and 7 are EX-OR logic, 8 and 9 are digital LP
F, 10 are absolute phase detection circuits, 11 is a phase difference calculation circuit,
12 is a symbol clock recovery circuit, 13 is a phase difference data quantization conversion unit, 14 is a phase quantization memory address determination circuit, 15 is a phase soft decision memory, 16 is a soft decision error correction circuit, 17 is a demodulation data output terminal, Reference numeral 18 is a reference signal input terminal.

A differential detection circuit with a soft-decision error correction circuit configured as above will be described with reference to FIG. 2 and FIG.
The operation will be described for the case of / 4 shift QPSK modulation. FIG. 2 is a waveform diagram of each part for explaining the operation of the differential detection circuit. FIG. 3A is a diagram showing signal point arrangement of inter-symbol phase difference of π / 4 shift QPSK modulation, FIG. 3B is a diagram showing a phase plane of the reference signal fref of the differential detection circuit, and FIG. It is a figure which shows the phase soft decision method.
First, the reception modulated wave input from the input terminal 1 in FIG.
Bandwidth is limited by BPF2 to suppress wideband noise.
After the band is limited by the BPF 2, the envelope is made constant by the limiter 3 in order to make the amplitude constant, which is input to the digital quadrature demodulation unit 4. The digital quadrature demodulation unit 4 has two
90 ° phaser and digital LPF composed of two EX-OR logics 6 and 7 and 1/4 frequency divider 5
It is composed of 8 and 9. 2 is a waveform diagram for explaining the operation of the digital quadrature demodulation unit 4, and FIG. 2 (a) is a BPF2 of FIG.
The received modulated wave having a constant amplitude after being band-limited by the limiter 3 is shown, which is a phase modulated wave with a constant amplitude. FIGS. 2B and 2C show the reference signal inside the quadrature demodulator, and FIGS. 2B and 2C have a phase difference of 90 °. 2D is an EX-OR output of the received modulated wave of FIG. 2A and the reference signal of FIG. 2B, FIG.
Is an EX-O of the received modulated wave of (a) and the reference signal of (c)
R output. The outputs of FIGS. 7D and 7E are reference signals f
It is a pulse-modulated wave having a cycle twice that of ref. Figure 2
FIG. 2F shows FIGS. 2D and 2E on the frequency axis, and the modulated wave component 21 of the baseband appears at an interval twice the reference signal. The digital quadrature demodulator 4 can extract the baseband modulated wave component 21 as the baseband outputs I and Q of FIG. 1 through the digital LPFs 8 and 9. The baseband outputs I and Q are signals whose sums of squares of the respective amplitudes are always constant, and are 1 on the phase plane of the reference signal fref as shown by the phase points 31 or 32 in FIG. 3B. It can be associated with one phase point. The absolute phase detection circuit 10 is from 0 ° to 3
The 60 ° phase is divided appropriately (128 divisions or 6
By holding the phase data in the memory, the I and Q outputs of the digital quadrature demodulator 4 are equally divided into 0 ° to 360 ° corresponding to the phase of the reference signal fref. Can be obtained as digital data φk. The phase difference calculation circuit 11
In the absolute phase detection circuit 10, the symbol data time interval T
Based on the absolute phase detected every s, time t = (k−
1) Detection phase φ (k-1) at Ts and time t = kTs
(Where k is an integer) the phase difference φd with the detected phase φk =
Calculate φk−φ (k−1). The differential detection circuit described above is disclosed in Japanese Patent No. 2-300827. Next, the phase difference φd obtained by the differential detection circuit
A method of performing soft-decision error correction by quantizing ω on the phase plane will be described. The phase difference φd is input to the phase difference data quantization conversion unit 13. The phase quantization conversion unit 13 is shown in FIG.
As shown in (c), the memory 15 has quantized data on the phase plane according to the inter-symbol phase difference arrangement of π / 4 shift QPSK, and the phase quantization memory address determination circuit 14 uses the phase Soft decision data is obtained by designating a memory address corresponding to the phase difference φd input to the quantization conversion unit 13. Then, the soft decision data is input to the soft decision error correction circuit 16 and error correction is performed to obtain demodulated data 17. Here, in FIG. 3C, the phase difference φd is quantized on the phase plane as follows. Regions i (1), i (2), q (1), q (2) are
The phase plane is equally divided according to the number of quantization bits, and a soft decision value is given to each. FIG. 3C shows a case where the number of quantization bits is 3. When the phase difference φd is in the regions i (1) and i (2), the I symbol is given a soft decision value of 0 to 7 depending on the value of the phase difference φd. Then, the Q symbol is given a soft decision value of 7 when the phase difference φd is on the region i (1) and a soft decision value of 0 when it is on the region i (2). In addition, the phase difference φd is
In the case of (1) and q (2), similarly, a soft decision value of 0 to 7 is given to the Q symbol according to the value of the phase difference φd. Then, in the I symbol, the phase difference φd has a region q
If it is above (1), a soft decision value of 7 is given, and the region q (2)
If it is above, a soft decision value of 0 is given.

As described above, according to the present embodiment, the absolute phase detecting means for directly detecting the absolute phase with respect to the reception phase modulated wave and the internal reference signal, and the continuous reception symbols detected by the absolute phase detecting means. Detect the phase difference of
The phase difference detecting means and the phase difference data quantization conversion means for quantizing the phase difference data between the received symbols detected by the phase difference detecting means are provided in the differential detection demodulation method. The decision error correction system can be applied, and a delay detection circuit with a soft decision error correction circuit suitable for a mobile communication receiver can be realized. Further, although the above embodiment has been described with respect to π / 4 shift QPSK, the same can be applied to DQPSK.

[0013]

As described above, the present invention compares the received phase-modulated wave with a constant envelope with the internal reference signal,
An absolute phase detecting means for directly detecting the absolute phase with respect to the internal reference signal; an absolute phase of the received symbol detected by the absolute phase detecting means; and an absolute phase detected one symbol data time interval before the received symbol. The phase difference detection means for detecting the difference between the phase difference data detected by the phase difference detection means and the phase difference data between the received symbols on the phase plane of the phase difference data provided by the quantization conversion means. The soft-decision error correction method can be applied to the delay-detection demodulation method, and a delay-detection circuit with a soft-decision error correction circuit suitable for a mobile communication receiver can be realized.

[Brief description of drawings]

FIG. 1 is a block connection diagram of a differential detection circuit with a soft decision error correction circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the orthogonal quadrature demodulator of the differential detection circuit in the embodiment.

FIG. 3 is a phase diagram for explaining the operation of the differential detection circuit with soft decision error correction circuit in the same embodiment.

FIG. 4 is a block connection diagram of a baseband band differential detection demodulation circuit used for demodulating a conventional π / 4 shift QPSK modulation wave.

[Explanation of symbols]

 1 Input Terminal 2 BPF 3 Limiter 4 Digital Quadrature Demodulator 5 1/4 Divider 6 EX-OR Logic Circuit 7 EX-OR Logic Circuit 8 Digital LPF 9 Digital LPF 10 Absolute Phase Detection Circuit 11 Phase Difference Calculation Circuit 12 Symbol Clock Reproduction circuit 13 Phase difference data quantization conversion unit 14 Phase quantization memory address determination circuit 15 Memory 16 Soft decision error correction circuit 17 Demodulated data output terminal 18 Reference signal input terminal

Claims (2)

[Claims] 1. A means for detecting an absolute phase of a digitally modulated received modulated wave such as differentially encoded four-phase modulation or π / 4 shift four-phase modulation, with respect to an internal reference signal.
Soft decision error comprising means for quantizing on the phase plane the phase difference between the absolute phase detected by the absolute phase detection means and the absolute phase detected one symbol data interval before the absolute phase. Delay detection circuit with correction circuit. 2. The quantization method on the phase plane according to claim 1, wherein the IQ phase plane is defined by symbol points of quadrature phase modulation and I points.
-Q is divided into 4 equal parts by the line segment connecting the origin of the phase plane,
The equally divided regions are assigned to the I and Q symbols so that the I and Q symbol regions are adjacent to each other, and the regions assigned to the I and Q symbols are quantized. The region is divided according to the number of bits, and a soft decision value is given to each of the regions divided according to the number of quantization bits. Then, when the phase data to be quantized is in the I symbol area,
A soft decision value according to the number of quantization bits is given to the I symbol, a constant soft decision value is given to the Q symbol, and when the phase data to be quantized is in the Q symbol area, The phase data is quantized on a phase plane by giving a soft decision value according to the number of quantization bits to the symbol and a constant soft decision value to the I symbol. Delay detection circuit with soft decision error correction circuit described.