JPH0548034U - Microcomputer - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the power consumption of a system by monitoring long-time operation by a loop instruction of a microcomputer and issuing a standby request to another IC. [Structure] Jump instruction detection circuit 3, standby request condition setting circuit 6, jump address generation register 7, jump destination address register 8, predicted address register 1
3, the address comparator 14 is provided, and the standby request signal 9
And the standby release signal 15 is output.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a microcomputer, and more particularly to a microcomputer equipped with a standby control function.

[0002]

[Prior Art]

 In the conventional microcomputer, when a standby request output is made to another IC (integrated circuit) having a standby function, as shown in FIG. A specific command is issued, and in a microcomputer equipped with an output port, a standby request signal is output from the port terminal by executing a predetermined program.

In the prior art shown in FIG. 3, the microcomputer 22 sets the standby control IC 25 through the address bus 23 and the data bus 24, and the standby control IC 25 uses the standby request signals 18 and 19. , IC20, 21 make a standby request.

[0004]

[Problems to be solved by the device]

 However, in this conventional standby control method, since the management of the long-term operation of the microcomputer 22 in the loop state needs to be performed by software, the presence / absence of a standby request to the external ICs 20 and 21 is determined by the microcomputer. Depends on the contents of the program that is executed in. Therefore, there is a drawback that the power consumption of the entire system is high.

The present invention has been made in view of the above problems, and it is possible to monitor long-time operation by a loop instruction of a microcomputer by itself and reduce power consumption of the system. The purpose is to provide.

[0006]

[Means for Solving the Problems]

 The microcomputer according to the present invention includes a prefetch address register for storing an address currently being executed, a detection circuit for detecting a jump instruction including a branch and a loop, and the jump instruction generated by a signal from the detection circuit. Address of jump occurrence to store address, address register of jump destination to store address of jump destination, first output terminal, and register to set condition to output standby request signal from this first output terminal to outside A condition setting circuit for determining whether or not a condition is met by comparing the jump generation address with the jump destination address, an adder circuit for sequentially adding the jump destination address, and a prediction predicted by the adder circuit Predictive address register for storing address, and second output terminal A comparator for comparing the predicted address with the value of the prefetch address register to detect an address mismatch and release a standby request from the second output terminal to the outside. ..

[0007]

[Action]

 In the present invention, when a jump instruction is detected by the jump instruction detection circuit, the address at which the jump instruction is generated is stored in the jump generation address register, and the jump destination address is stored in the jump destination address register. Then, the condition setting circuit compares the jump occurrence address with the jump destination address, and outputs a standby request signal via the first output terminal when the preset condition is met. Since the loop instruction monitoring circuit is built-in in this way, the external IC can be placed in the standby state when the microcomputer is in the loop state.

[0008]

【Example】

 Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a microcomputer 16 according to an embodiment of the present invention. The instruction code stored in the instruction decoder 2 via the internal bus 1 is input to the jump instruction detection circuit 3, and the jump instruction detection circuit 3 detects a jump-related instruction. As a result, the detection signal 4 is output from the detection circuit 3, and the address buffer 10 is controlled by this detection signal 4 to store the value of the address register 5 in the jump occurrence address register 7. The detection signal 4 is also input to a condition setting circuit 6 which determines whether or not to output a standby request to the outside, and the detection signal 4 enables the condition setting circuit 6.

In the condition setting circuit 6, conditions for outputting the standby request signal 9 are set in advance via the internal bus 1. Then, the condition of the value of the jump occurrence address register 7 and the value of the jump destination address register 8 from which the jump destination address is read from the address register 5 via the address buffer 10 like the address register 7 By inputting to the setting circuit 6, the condition setting circuit 6 outputs the standby request signal 9 in comparison with the preset condition.

The address comparison circuit 11 has a built-in address adder circuit 12 and increments the value of the jump destination address register 8 to store the address currently predicted to be executed in the predicted address register 13. At that time, if the value of the predicted address register 13 matches the value of the jump occurrence address register 7, the value of the jump destination address register 8 is stored in the predicted address register 13 next, and the increment is performed again. repeat. The value of the predicted address register 13 is always compared with the value of the address register 5 by the comparator 14, and if the value of the address register 5 does not match the value of the predicted address register 13 due to the end of a loop, etc. It outputs a standby release signal 15 for releasing the standby mode to the IC.

FIG. 2 is a schematic diagram of a system using the microcomputer 16 of the present invention. The standby request signal 9 and the standby release signal 15 are input to the standby control circuit 17 and output as standby request signals 18 and 19 such as HALT to the external ICs 20 and 21.

[0013]

[Effect of the device]

 As described above, according to the present invention, by incorporating the loop instruction monitoring circuit inside the microcomputer, it is possible to put the external IC in the standby state when the microcomputer is in the loop state. The power consumption of the entire system can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a microcomputer according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a system using the microcomputer shown in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional standby system.

[Explanation of symbols]

 1; internal bus 2; instruction decoder 3; jump instruction detection circuit 4; address buffer control signal 5; address register 6; standby request condition setting circuit 7; jump generation address register 8; jump destination address register 9; standby request Output signal 10; Address buffer 11; Address comparison circuit 12; Address addition circuit 13; Predicted address register 14; Address comparator 15; Standby release request output signal 16; Microcomputer 17; Standby control circuit 18, 19; Standby request Signals 20 and 21; External IC 22; Conventional microcomputer 23; Address bus 24; Data bus 25; Standby control IC

Claims (1)

[Scope of utility model registration request] 1. A prefetch address register for storing an address currently being executed, a detection circuit for detecting a jump instruction including a branch and a loop, and an address at which the jump instruction is generated by a signal from the detection circuit. A jump occurrence address register, a jump destination address register that stores the jump destination address,
A first output terminal and a register for setting a condition for outputting a standby request signal to the outside from the first output terminal are included, and it is determined by comparing the jump generation address and the jump destination address whether or not the condition is met. A condition setting circuit, an adder circuit for sequentially adding the jump destination addresses, a predictive address register for storing a predictive address predicted by the adder circuit, a second output terminal, a value of the predictive address and the prefetch address register. And a comparator that outputs a signal for canceling the standby request to detect an address mismatch and output the signal from the second output terminal to the outside.