JPH0548008B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a digital processing circuit, and more particularly to a low power circuit for performing digital processing.

(2) Description of the Prior Art Electronic computer systems of the type that have all major electronic functions in a single large scale integrated circuit (LSI) semiconductor chip or in a small number of chips are developed by Texas Instruments Inc. Described in the prior art or patents assigned to Detsudo.

U.S. Pat. No. 3,819,921 to Kilby et al., Compact Electronic Calculator, originally filed September 29, 1967.

U.S. Patent No. 4074351 to Boone and Cochran
No. ``Variable Function Program Calculator''.

U.S. Pat. No. 3,819,957 to Bryant, "Digital Mask Logic in Electronic Calculator Chips."

US Pat. No. 3,987,416 to Bandai Rendont, Fisher and Hartsell, ``Electronic Calculator with Display and Keyboard Scanning.''

Such conventional inventions have made it possible to reduce the price, downsize, and increase the functionality of electronic calculators. Millions of such calculators were produced. Research and development continues to reduce manufacturing costs and increase the functionality available to users. In particular, it is desirable to provide a basic chip structure that is extremely flexible and usable in many different types of calculators and similar digital processing devices. By making such a chip, one manufacturing device can be used to produce the same device in large quantities, and different devices can be produced just by changing one mask, so the cost advantage of mass production can be maintained. It is possible to make a large number of changes while maintaining the same.

Conventional MOS/LSI calculator chips, such as those referenced above, generally had registers organized such that a single instruction word operated on all digits within a given register. For even more flexibility, it is possible to create a device organized in digits that operates one digit at a time. for example,
Suppose it is desired to test or set a specific 1-bit flag. In a digit-organized device, only the required digits or bits are accessed, whereas in a register-based device, a register of all 13 digits must be addressed and masked for use. An example of such a processing chip is disclosed in U.S. Pat. No. 3,991,305 to Cordell et al., entitled "Electronic Calculator or Digital Processing Chip with Multiple Code Combination of Display and Keyboard Scanning Outputs." This patent generally discloses what is known to those skilled in the art as the TMS1000 structure for 4-bit microcomputers. Another method using this same type of architecture is disclosed in U.S. Pat. . The mechanism disclosed herein is similar to the structure of the TMS1000 used with low power circuits and the structure disclosed in the above-referenced application.

FIG. 1a shows a prior art example that attempts low power operation using a positive channel MOS field effect transistor device. This type of circuit is referred to as a precharge and conditional discharge circuit. Node 800 is in a charged state during φ3. Note that since the circuit is in P-MOS, the device is active while the timing signal is in the negative portion. During φ1, this node remains charged until it is conditionally discharged by the input line. If the input line remains at a high potential, the node will remain charged and the output will remain at -V as shown in Figure 1b. However, if the input is at a low potential, the device 801 will be activated and the node 800 will be open-circuited to φ1 as shown in the figure. The drawback of this standard charge-discharge logic is that the pre-charge period is longer than other circuits, e.g.
This is because it causes problems in RAM cell addressing, etc. If the charge/discharge logic is connected directly to the address portion of the RAM cell, all addresses will be on during the precharge period. Therefore, if charge/discharge logic is used to address the RAM, additional circuitry is required to buffer the precharge interval from the address lines of the RAM cells.

FIG. 2 shows a static inverter including a device with a depletion region 802 for supplying charge to a node connected to an output line. States inverters solved the precharge problem, but
Consumes more direct current. A static inverter also requires a significantly larger load device size for any device in the precharge discharge circuit. This is a major drawback when manufacturing circuits on small silicon chips.

The third attempt to realize low-power circuit operation
This technique is shown in Figure 3. This is a complementary type
It is a MOS converter. Clock-synchronous CMOS converters have no precharge and do not require constant DC current. However, CMOS manufacturing processes are more costly and complex than regular PMOS or NMOS manufacturing processes.

For many semiconductor display application technologies, CMOS,
Includes techniques for the use of charging/discharging circuits and static devices. One such circuit is that required for liquid crystal displays. Liquid crystal displays are required to be low power and therefore interface well with low power processing circuits. A reference to the requirements for LCDs is the International Handbook of LCDs 1975-76, 2nd edition, supplemented by Martin Tobias in 1976, published by Obham, 14 Pen Road, London, NC9RD, UK. Please refer to. Other references include 2990 West Lomita Blvd., Tolerance, Calif.
There is ``General Information on LCD Displays'' published by Epson America Inc. The third reference is "Vacuum Science and Technology Bulletin," Vol. 10, No. 5, September 1973.
There is an article by LA Gutsman titled ``Liquid Crystal Displays'' that will be published in the Monday/October issue.

In the past, LCD devices have required the use of low power circuits such as charge-discharge logic or CMOS logic. This specification discloses another technique for low power circuits suitable for low power interfacing with LCDs without the disadvantages of conventional circuits.

Also disclosed herein are low voltage RAM cells. RAM cells are included in the patents listed above. However, herein the low voltage
This shows the manufacturing technology of RAM cells.

Other patents involving similar techniques include U.S. Pat. There is a US Patent No. 4,280,271.

In conventional calculators and microcomputer chips, low power CMOS circuits or static logic have been used to manufacture oscillators in clock circuits. This specification discloses techniques for manufacturing low power oscillator and clock circuits that do not have the disadvantages of charge/discharge circuits, static converters, CMOS circuits, and the like.

This specification also includes discussion of integrated circuit on/off switches. Prior art on/off switches include mechanical on/off switches that require a separate switch dedicated to the power switch. An advantage of an integrated on/off switch is that it can be built into the keyboard and used for other functions as well. Traditional on/off switches, other than CMOS-style on/off switches, require a significant amount of constant current to flow, shortening the life of the batteries operating within the microcomputer system.
The integrated on/off switch disclosed herein is
Even if not manufactured in CMOS form, it requires only a small amount of power during the off state.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a low power circuit, especially a low power inverter circuit, which does not have the disadvantages of charge/discharge circuits, static inverters, CMOS circuits, etc.

In order to achieve the above object, the low power circuit of the present invention
(a) first and second power lines; (b) first and second power lines;
(c) first and second clock means for supplying first and second clock signals having opposite phases; A circuit, the first circuit
The circuit means includes first, second, and third transistors of one conductivity type connected in series, and a first clock signal and a third clock signal are applied to the gates of the first, second, and third transistors, respectively. 2 clock signal,
An input signal is provided, and the first circuit means further comprises:
the first clock signal in response to the second clock signal and the input signal.
and means capable of boosting a node coupling the second transistor, the second circuit means including fourth, fifth, and sixth transistors of one conductivity type connected in series; The gates of the fifth and sixth transistors are connected to the node, and the gates of the fifth and sixth transistors each receive a second clock signal,
The device is characterized in that an input signal is supplied and an output terminal is formed between the fifth and sixth transistors.

In the following, the invention will be explained in detail in connection with exemplary embodiments with reference to the figures.

DESCRIPTION OF EMBODIMENTS A basic configuration example of a low power inverter circuit according to an embodiment of the present invention is shown in FIGS. 4a to 4d.

The inverter circuit shown in FIG. 4a has first and second circuit means, the first circuit means being a MOS transistor 805 whose gate is connected to the clock signal φA, and a transistor whose gate is connected to the clock signal φB. 808, a transistor 809 that connects the input signal to the gate, and a transistor 805.
and a node 806 coupling transistor 808
and a capacitive element 807 that can supply charge to. On the other hand, the second circuit means includes a transistor 813 having its gate connected to the node 806, and a transistor 812 having its gate connected to the clock signal φB.
Transistor 810 connecting the input signal to the gate
and a transistor 810 and a transistor 8
An output section is formed between 12.

The inverter circuit shown in FIGS. 4b and 4c is a modification of the second circuit means of the inverter circuit of FIG. 4a. The inverter circuit of FIG. 4b includes transistor 812 and transistor 8.
A transistor 811 is connected in series between the transistor 10 and the transistor 811, and the gate of the transistor 811 is connected to the clock signal φB. The one shown in FIG. 4c has another output section formed thereon.

Furthermore, the inverter circuit shown in FIG.
This is a modification of the first circuit means of the inverter circuit shown in FIG. 4A, in which the first circuit means of the inverter circuit shown in FIG. It has a configuration in which these are connected.

Next, the operation of the inverter circuit according to this embodiment will be explained.

Since the operations of the inverter circuits shown in FIGS. 4a to 4d are essentially the same, the operation of the inverter circuit shown in FIG. 4c will be representatively explained here. Note that FIG. 4e is a diagram showing the inverter circuit of FIG. 4c in symbols, and FIG. 4f is a timing chart.
Referring to FIG. 4a, during the time frame φA,
Node 806 is being charged by device 805 . If the input to the PMOS circuit is at a low potential for a period of φB, node 806 is connected to input line and device 808.
and 809. However, if the input is at a high potential, timing signal φB supplies additional charge to node 806 by capacitive element 807. When charged, node 806 is connected to device 8
Similarly, φB turns on devices 811 and 8.
Turn on 12. If the device 810 does not turn on because the input is at a high potential, the lines marked “OUT1” and “OUT2” will cause
An output voltage of V is generated. Note that since node 806 receives -V or a negative voltage value plus the charge from clock phase φB passing through capacitive element 807, node 806 generates a voltage below -V. Must-have. Therefore, the voltage at node 806 is greater than -V as shown in Figure 4c. As described above, since the inverter circuit according to this embodiment does not use charge/discharge logic, there is no need to use an additional circuit that does not cause trouble to other circuits during the associated precharge period. . Further, unlike an E/D inverter circuit, a large-sized load transistor is not necessarily required in order to achieve low power consumption. Furthermore, since it is not a CMOS structure,
Its manufacture is easy.

FIG. 5 shows a block diagram of the microcomputer disclosed herein. Note that this microcomputer is similar to that disclosed in US Pat. No. 3,991,305.
This patent is incorporated herein by reference. Instructions for this microprocessor system are contained in read-only memory (ROM) addressed by a chapter register (CA), a page register (PAGE), and a program counter (PC). Both the chapter register and the page register have a chapter buffer (CB) and a page buffer (PB). Furthermore, a three-level stack is provided for subroutine calls. The output of the ROM is decoded by an instruction decoder and provides control signals for the rest of the microcomputer circuitry. Timing for the microcomputer circuit is provided by an oscillator. Input to the device is provided through ports K ₁ to K ₄ . These inputs are provided to a 4-bit arithmetic logic unit (ALU). ALU
It also receives input from random access memory RAM (a device provided for temporary data storage). The arithmetic logic unit provides outputs to the Y register and the accumulator, which also provide inputs to the arithmetic unit. The Y register also provides output for the RAM and register digit outputs (R ₀ -R ₁₂ ) from the microcomputer. The accumulator provides an output to an output program logic array (OPLA). OPLA also provides data to the display RAM. The display RAM also receives output from the Y register. Common line generator, display
RAM and segment drive circuits provide output
It drives the LCD device.

This block diagram (LCD interface omitted) was created by Texas Instruments.
A more detailed explanation is provided in the "TMS1000 Series Data Book Manual" published in December 1975. It is shown here for reference. This circuit is also described in the "Reference Manual for the TMS1000 Series MOS/LSI One-Chip Microcomputer Programmer" published by Texas Instruments, Inc., and is included here for reference.

6a, 6b, 6c, and 6d illustrate the instruction duplicate block of FIG. 5. This circuit provides control signals from microinstructions stored in ROM.

Figure 7 shows constants and keyboard bits (CKB)
Shows logic. The overall function of this logic is
It has a three-layer structure. First, constants that appear within the instruction code area are output. Second, keyboard or external input is output. Third, one of the four output lines is selected and one of the four bit digits stored in the RAM is addressed. All of these functions are controlled by instructions given from the ROM.

Figures 8a and 8b show a read only memory (ROM). It should be kept in mind that line 978 represents one of the 128 lines not shown. ROM
stores instructions that specify logical operations. In this configuration, the ROM has 2048 8-bit instruction words. 16 ROMs each
It is organized as two chapters with pages. Each page contains 6464 instruction words.
The ROM is addressed by a 1-bit chapter address and a 4-bit page address contained in registers shown in the logic of FIGS. 10a-10d. Additionally, the ROM is addressed by a 6-bit program counter (PC) as shown in Figures 9a and 9b. Each of the above program counters has a three-stage subroutine stack for designing algorithms. The program counter consists of a series of pseudo-random numbers (0, 1, 3, 7, F, ... 10, 20, 0,
1, etc.) are counted sequentially. This series of random number counting continues unless changed by execution of a branch, call, or regression instruction. In the preferred embodiment, the instruction at chapter 0, page F program counter 00 is executed first when power is applied.

Arithmetic and logic operations are performed by a 4-bit arithmetic logic unit that cooperates with the logic shown in Figures 11a and 11b. The arithmetic logic unit performs logical comparison arithmetic comparison and addition functions. Operations on two sets of inputs are performed when the two sets of 4-bit parallel inputs are added together or logically compared. The accumulator is
It has an inverted output for one of the inputs of the ALU, and the subtraction is performed by two auxiliary arithmetic circuits. This input can also be the correct output of an accumulator, RAM, instruction constant or keyboard input. Other inputs come from the Y register, RAM, instruction constants, or keyboard input. Constants are provided by instruction words stored in ROM. The results of additions and subtractions are stored either in the Y register or in the accumulator. The arithmetic function generates a carry output to the state logic. Logical comparisons produce outputs in state logic. When the compare function is used,
The status bits affect only program control and do not affect the contents of the Y register or the accumulator register. If the status bit is a logical 1, which is the normal state, then the branch or call instruction is executed next. If the instruction resets the state bits (not by carrying or comparing to make the bits equal), the state goes to the 0 state and then back to the 1 state for one instruction cycle. If the status bit is 0, branch and call instructions are not accepted and the next instruction is executed at PC+1 (the next normal program counter consecutive address).

A random access memory (RAM) is shown in FIG. The RAM provides temporary storage for data sent from the arithmetic and logic unit through the Y register. RAM is addressed by instructions passing through the Y and X registers. The X register decoding circuit is shown in FIG. This circuit is shown in Figures 14a and 14.
Connected to the X address circuit shown in Figure b.

The Y register also addresses thirteen output latches, shown as digit latches in FIG. Note that FIG. 15 actually depicts 16 output latches. However, the three top bit latches DL13, DL14, DL1
5 is dedicated for special functions and is not used for external output.

The initialization circuit is shown in FIG. This circuit provides an initialization signal to the microcomputer and, in conjunction with an input at the RO bat, provides an output indicating a test instruction when the initialization pad receives that input. Therefore, the digit latch RO has both input and output functions. The actual register output circuit is shown in FIG. This circuit receives input from the digital latch of FIG. Each output is individually set or reset by being addressed by the output of the Y register, and a SETR or RSTR instruction is executed. Each output is one of three selectable formats.
(i.e., push-pull, open-drain pull-high, or open-drain pull-low, whichever is most suitable for the user) is manufactured using a mask program. The SETR instruction turns on the pull-high device, if present. The source current from Vdd is
Turn off the pull-low device. The RSTR instruction turns on the pull-low device, if present. Current flowing to Vss turns off the pull-high device. Selecting an open-drain pull-row allows the keyboard to be scanned without the use of external components and without the confusion caused by input from multiple keys at once. The open-drain pull-high selection is used for maximum current drive capability or for interfacing with other logic that requires voltages higher than Vss. The selection of Pushyupur is
Used to interface with any CMOS logic operating at the same voltage level.

A keyboard input circuit is shown in FIG. There are four data inputs K ₁ , K ₂ , K ₃ and
_K4 exists. All inputs are inverted to be compatible with the features of the integrated on/off switch when they are received. All inputs are 4
Either the bit input is tested for a low level with the KNEZ instruction, or the 4-bit input is transferred to the accumulator through the control keyboard logic described above with the TKA instruction. The K input is kept at a high potential internally,
Regarding the "1" level input, it is set to a low state externally. The K input for a KNEZ or TKA instruction must be valid during the previous instruction cycle portion. The R output from the register output circuit (R output pulldown selection) of FIG. 17 is used to scan the matrix of keys without adding any components. If the R line is used for scanning input,
It is necessary to leave at least one instruction cycle between the RSTR instruction and the KNEX instruction. In addition to keyboard input, an integrated on/off switch is shown in FIG. The central circuit for this on/off switch is latch 820. When in the off state, power is provided from Vss through resistor 826 to gate 828 of the device. However, since the device is off, device 823 is not receiving clock signal φ3. Therefore, the line labeled OFF is not powered and the circuit does not waste any current. The on signal is received by pressing any of the four keyboards, thereby activating either device 822 or any of the four devices 830. When any of devices 822 is activated, node 827 drops to Vdd and device 828 turns off. Device 830 is Vdd and LVdd
Since Vdd powers the internal clock, device 823 is activated when φ3 occurs.
When φ3 occurs, power is applied to the gate 827 of the device.
is given and the state of the latch changes. When this latch changes state, power is applied to gate 824 which in turn applies power from LVdd to Vdd.
LVdd is the current Vdd power source that is always on. Vdd powers the microcomputer chip.

Figures 19a, 19b and 19c illustrate an output program logic array (OPLA) that decodes the output data from the accumulator for display RAM. The OPLA outputs are connected through the segment line circuit shown in FIG.

15. State latch and state latch determine whether (X) or (Y) is loaded into the display RAM. These circuits of FIG. 20 are connected to the display RAM by means of digit latches 15 which control the decoding or non-decoding functions of the accumulator lines of FIGS. 19a, 19b, and 19c.
output can be controlled.

FIG. 21 is a block diagram of a liquid crystal display output circuit. Block 414 is the display
It shows RAM and is organized into a 4-bit by 20-bit array. The figure also includes OPLA 417 which receives input from the accumulator via line 419 and status input via line 418.

OPLA 417 connects segment X via line 415
and segment Y to display RAM 414 via line 416 which also passes through the TDO control circuit. The common time generator 400 is OPLA41
line 40 to both 7 and display RAM 414.
4,407,406. Liquid crystal display devices consist of two types: common time output and selection output. In order to display one digit on one liquid crystal display, two selection outputs and four common time outputs are required. Two selection outputs are dedicated to each digit of the liquid crystal display. However, all four common time outputs are common to all digits of the liquid crystal display. The circuit shown in the figure provides output for 10 digits on a liquid crystal display. That is, two selection outputs are given for 10 digits, so a total of 20 selection outputs are given. Regarding these 20 selection outputs, 4
Two common time outputs are given. Selective outputs are required for all displays contained within display RAM 414 during each of the four common time periods. The common time generator addresses four common times for two segments each in both OPLA 417 and display RAM 414. Additionally, the common time generator is connected to the common buffer 4 via line 405.
A common time output is given to 08. Common time generator 400 also connects line 101 to resistive divider 4
A polarity signal is given to 02. Liquid crystal displays require a signal to select polarity. That is, when receiving a positive signal, negative signals of the same amount of potential must be sequentially received at appropriate inputs. Therefore,
In order to properly interface with a liquid crystal display, the outputs from the select pad and the common pad must all be of one polarity for a predetermined period of time and then the other polarity for the same period of time. This need is met by providing a polarity input to resistive divider 402 to change polarity according to common time generator 400. A resistive divider 402 provides a voltage input to a common buffer 408 .
8 provides an output to the common pad via line 410. Additionally, resistive divider 402 provides voltage to select line buffer 411 via line 409. The selection buffer 411 is connected to the display via line 413.
Selection data is also received from RAM414.
The 20 selection lines are output on line 412.

The common time generation circuit is shown in FIGS. 22a and 22b.
As shown in the figure. The circuit shown as 440 is a ring counter providing timing to gate 443. Gate 443 is gate 444
It also receives input from the TDO. If any of the three inputs at gate 443 are activated, SHIFTC is connected to common time generator 4.
Increment 00. The output of gate 443 is connected to four common time latches 431, 432, 4
It is used to shift the output of 33,434. The outputs of these latches represent a common time period. When updating the display, the TDO instruction is enabled for four instruction cycles and all four common latches 431-434 are activated. The outputs of these common latches are the common time output, line 439, and line 438 indicates that the common latches are not shifted. Furthermore, circuit 4
35 acts as a polarity generator. circuit 435
has a one-half counter that receives a timing signal from a timing circuit 442 as shown. When displaying in high-speed cycle mode
The number of instruction cycles per SHIFTC pulse must be increased to maintain the same display period. (Circuit 950 has a 1/127 counter.) In the fast period mode, gate 444
Used to provide a pulse indicating SHIFTC every 127 instruction cycles.

The resistance distribution circuit and the common buffer circuit are the 23rd
and FIG. 23b. The resistive distribution circuit receives the polarity signal from the common time generator 400 via line 101. This signal connects the first two buffers 451 and 45 which provide output to the rest of the resistive distribution circuit without pre-charging.
2 is input. These buffers are two inverter circuits connected in series similar to the inverter shown in Figure 4c. Capacitive element pair 454 receives input from circuit 459. Capacitive element 4
54 is used to provide the outputs of buffers 451 and 452 which are input into cross latches 457 and 458. Cross latch 458 has VA and
Generate VC. Cross latch 458 is VD and
Generate VB. VA and VB are used by selection lines. VC and VD are used on a common line. Capacitive element 454 and buffers 452, 451
output drives these matrix switches at a higher voltage than the negative power supply. This capability allows the circuit to use lower voltage power supplies than are normally required for PMOS or NMOS circuits. The outputs of these matrix switches 457 and 458 are connected to the distribution network 463.
and 462, providing high impedance or low impedance interfaces, respectively. Low impedance interface 4
63 is turned on during the first instruction cycle when power transfer is required. High impedance circuit 462 switches on and maintains the power signal for the remaining three instruction cycles. Line 465 connects low impedance circuit 46 during the first instruction cycle.
A pulse is given to connect 3.

The common buffer 408 is also shown in FIGS. 23a and 23b.
Shown in the figure. The buffer receives a signal from common time generator 400 on line 405. This signal is buffered by two buffer sections 182 and 183 similar to the inverter circuit of FIG. 4a. The outputs of these inverters 182, 183 drive devices 840 and 841. The outputs of inverters 182 and 183 are supplemented by capacitive elements 186 and 187 that receive charge from COU1. This additional signal is connected to devices 840 and 841.
Used for switching. Capacitive elements 187 and 186 receive additional charge from COU1 circuit 459 to provide signals to devices 840 and 841 in an amount in excess of Vss. The four common lines shown at 410 further provide outputs to individual Vc or Vd lines determined by common buffer 408 and resistive divider 402. The common buffer for common pads 2-4 is similar to the common buffer shown.

FIG. 24a is a schematic diagram showing RAM cells for display RAM 414. RAM cells are
device 960 controlled by address and
Line 1 connected from the device 961 controlled by the TDO command and from the inverter 175 (see FIG. 25b) with input from the common time generator 400
Through a device 962 controlled by 74,
It is receiving input from either SEG(X) or SEG(Y). The RAM cell is of the three-transistor type and includes a gated capacitive element shown at 207. φ2 and φ31 are I/O
Used to precharge the wire with a positive value.
At the start of the refresh cycle, φ1 and φ4 are connected to ground. Therefore, φ1 becomes -V. If node 210 indicates a negative value (storing a "0"), gated capacitive element 207 is turned on and node 210 has an amount of voltage higher than the voltage provided by the negative power supply. is connected. Gate drive on device 205 is in a state sufficient to change node 211 to -V. φ1 then goes to ground and φ4 rises to an amount higher than the voltage given by the negative power supply. Node 211 shares charge with node 210. When the voltage at node 210 drops due to leakage, the voltage level is refreshed.

If “1” is stored in the cell, the gated capacitive element 207 is not turned on and the node 210
Also do not connect with negative voltage. Device 205 is not turned on and nodes 210 and 211 remain at ground potential. Connection leakage at nodes 210 and 211 causes these nodes to remain at ground potential.
The RAM bit timing table is shown in Figure 24b. In FIG. 24c, the gated capacitive element 20
7 manufacturing process is shown. φ1 is the diffusion region 21
Please note that it is accepted by 2.
Adjacent to diffusion region 212 is a thin oxide layer 214, numbered 215 in FIG. 24c, extending across 212 and below the metal junction of node 210. A self-aligned implant is performed in the pattern 213 shown. This injection is carried out on metal plate 2
It is desirable that the area below plate 215 is not injected, but the area adjacent to plate 215 is injected.
Since 215 is made of metal, the area below 215 is not diffused in the horizontal direction, thereby achieving the desired result. Display RAM 414 and selection buffer 411 are shown in FIG. Chapter 24a
The RAM cell shown in FIGS. 24b, 24c, and 24d is shown as circuit 173 in FIGS. 25a and 25b. This RAM cell is addressed by a line 174 connecting from circuit 175. This circuit 175 receives input from the common line 406 previously described.
The RAM cells are segment X as explained earlier.
It receives inputs from line 415 and segment Y line 416 and also receives the TDO signal of device 191 shown in Figures 25a and 25b. The contents of the cell are output into a selection buffer shown as circuit 505. Output buffer 505 receives charges from capacitive elements 178 and 179,
Furthermore, these capacitive elements receive a timing signal COU2 from the circuit 177. The purpose of this additional charge is to drive the output of buffer 505 beyond the negative power supply value. As previously mentioned, this technique allows use with small power supplies. The output of the selection buffer is line 18
Line 180, shown as 0, connects directly to the liquid crystal device. Additional circuitry 176 is illustrated with signal φX occurring on line 181. φX
is the output buffer 50 from segment RAM 173.
This is a signal for transferring data to 5. line 96
5 is used to keep the display floating during test mode. Figure 24d is the second
Figure 4c shows a cross-sectional view of the portion of the RAM cell shown in Figure 4c. Substrate 217 has gap 2 that serves as a connection between diffusion region 212 and metal gate 215.
Please keep in mind that it includes 16.

FIG. 26 is a block diagram of the clock generation circuit. Block 311 starts a regenerative oscillator (ticler) which starts an oscillator 313 via line 312.
oseillator). Oscillator 313 then outputs two oscillation signals to ring counter 315. The ring counter 315 is further connected to the line 316
A timing signal for the delay buffer 317 is output to the top. Delay buffer 317 sends 15 signals to line 318 to clock buffer 319 shown in the figure.
Give on top. Nine clock signals are output on line 320. The logic diagram of the oscillation circuit and regeneration circuit is shown in the second section.
It is shown in Figure 7. Block 311 contains the logic for a regenerative oscillator including a static NAND gate 321 connected to two static converters 322 and 323. Capacitive element 324 is a static capacitor connected from the output of inverter 322.
Note that it is connected to the input of NAND gate 321. This capacitive element adds charge to the output of the device 323 and connects the device to the main oscillator 34.
It is driven by 7,348,349. This technique, previously mentioned, is called "bootstrapping" or driving with a voltage greater than the negative power supply. The purpose of the regeneration oscillator is to start the oscillator 313 as the power increases. Oscillator 313 is illustrated as a loop of two inverters connected with cross-coupled NAND gates. Capacitive elements 332 and 341 are provided in the loops of these inverters, and 344, 3
Note that we are providing additional charge to the oscillator output of 45. inverter 330,
334 and 338 are gated and closed by. Inverters 331, 337, 339
The gate is opened and closed by the OSC. Inverter 3
35 and 340 are similar to the static inverter shown in FIG. NAND gates 328 and 329 are gated and closed by signal A and signal B, respectively. 28a and 28b are circuit diagrams of the oscillator 313.

FIG. 29a shows the ring counter 315 shown previously.
FIG. Number 31,3 in a round box
2, 33, 34, 35 and 36 indicate certain points of such special nodes. These numbers are also used elsewhere in delay buffer circuit 317 (FIG. 26) to generate signals for the clock buffer. The timing table for the input from oscillator 313 into ring counter 315 is shown in FIG. ring counter 31
The timing table for the output of 5 is shown in FIG. The number assigned to the waveform is 31 in Figure 29a.
Please note that this corresponds to the specific node shown in 5. Whenever the display is updated, circuit 975 selects a fast cycle operation to further increase the speed and provide a bootstrapped voltage at the display output.
Circuit 975 (input by user)
also selects fast cycle operation when is active. Also shown is a schematic diagram 999 of regenerative oscillator 311 (FIG. 26).

A schematic diagram of delay buffer 317 is shown in FIG. 29b. Please remember that the signal input numbers and output numbers correspond to the respective timing table numbers shown in FIG. Delay buffer 317
The purpose of providing a signal that is logically the same as the output of ring counter 315 is that the output of this buffer can be "bootstrapped" below the negative supply voltage by using the gated capacitive element shown. has been done. These signals are used to drive the clock buffer of Figure 29c.

A schematic diagram of the clock buffer 319 is shown in the second section.
Fig. 9c. Such a buffer consists of a push-pull circuit, φ3 and φ4 are “bootstrapped” to a voltage lower than the negative power supply voltage by capacitive elements 976 and 977, respectively.
has been done.

FIG. 34 is a schematic diagram illustrating the various logical forms used in previous schematic diagrams. Many of these figures
It is similar to the low power inverter shown in Figures c, 4e and 4f.

As described above, we were able to provide a circuit that can be used with a low power supply and is suitable for interfacing with an LCD. According to the present invention, it is possible to interface with an LCD without using a special low-power circuit such as CMOS logic as in the prior art. Furthermore, the present invention could also provide a RAM cell that can be used with low power supply. Further, by utilizing the present invention, it is possible to provide an oscillation and clock circuit that can be used with a low power supply and avoids the drawbacks caused by using conventional precharge discharge circuits, static converters, CMOS, etc. You can also do it.

By taking advantage of these advantages, it is possible to combine devices with simple construction and low power consumption, such as microcomputers, to provide products that meet very modern needs and can be used in any application. I am confident that we will be able to obtain very good results.

The following sections are disclosed in connection with the above description.

(1) an output line; first circuit means for precharging the node; second circuit means connected to said node for discharging said node in accordance with the occurrence of a selected input; and said second circuit means; a third circuit for isolating the node from the output line during connection and precharging;
A low power circuit having circuit means and;

(2) input circuit means for receiving data to be displayed; connected to said input circuit means and further comprising first switch means, a voltage greater than the amount of voltage applied to said first switch means by the circuit power line; a segment output circuit having a first switch means for providing a first switch signal of a plurality of display segments; said segment output circuit having a first switch means for providing an output signal for a plurality of display segments; a display timing circuit connected to a display timing circuit for providing a second switch signal of a voltage amount greater than the voltage amount provided to the display timing circuit by the circuit power line, and further providing a time interval signal output; A display circuit comprising: the above display timing circuit;

(3) a gated capacitive element having a first terminal connected to the first node and a second terminal connected to the first refresh line; a first transistor having a second terminal connected to the node and the bit line, and a third terminal connected to the second refresh line; a first terminal connected to the power line and connected to the second node; a second transistor having a second terminal connected to the first node; and a third terminal connected to the first node;
a second refresh signal having a voltage amount greater than a voltage applied to the power line applied to the second refresh line.

(4) a plurality of inverter means, each inverter means including first circuit means for precharging a node; second circuit means connected to said node for discharging said node in accordance with the occurrence of a selected input signal; and; third circuit means connected to said second circuit means for isolating said node from said first and second output lines during precharge; and; a first output connected to said third circuit means. a second output line connected to said second circuit means, said inverter means being connected in a cascade connection;
The first output line of the previous stage is connected to the input of the next stage, the second output line of the final stage is connected to the input of the first stage, and the counter output is the first output line of the final stage. Digital counter with.

(5) a latch having first and second latch inputs and first and second latch outputs; connected to said first latch output and having at least one static inverter connected in cascade; a first loop having a plurality of dynamic inverters whose inverter outputs of the stages are connected to a first latch input; connected to a second latch output and having at least one static inverter connected in cascade; a second loop comprising a plurality of dynamic inverters, the output of the inverter of the last stage being connected to the second latch input; an initialization circuit connected to at least one of said loops; a first charge storage means connected between the output of the inverter and the first latch output; a second charge storage means connected between the inverter output and the second latch output in the second loop; an oscillator circuit having storage means;

(6) a latch that prevents power from being dissipated by the switch circuit during the OFF state and reduces direct current in the switch circuit during the ON state; a switch circuit comprising: first circuit means for enabling power supply and disabling said power supply during an off state; and second circuitry connected to said latching means for changing the state of said latch. .

[Brief explanation of drawings]

FIG. 1a is a schematic diagram of the charge/discharge logic, and FIG. 1b is a timing diagram of the charge/discharge logic;
Fig. 2 is a schematic diagram of a static inverter, and Fig. 3 is a schematic diagram of a CMOS inverter.
Figures 4a, 4b, 4c and 4d are schematic diagrams of low power MOS inverters, respectively;
Figure 4e is a symbolic representation of the low power MOS circuit shown in Figure 4c, and Figure 4f is a diagram symbolically representing the low power MOS circuit shown in Figure 4c.
It is a timing diagram of the low power MOS circuit of figure c,
Figure 5 is a block diagram of a microcomputer using a low power MOS circuit, and Figures 6a and 6
Figure b is a schematic diagram of the instruction decode logic arrangement;
Figures c and 6d are schematic diagrams of additional instruction decode logic, Figure 7 is a schematic diagram of constant and keyboard logic, and Figures 8a and 8b are schematic diagrams of read only memory (ROM). , 9a and 9b are schematic diagrams of the program counter, 10a to 10d are schematic diagrams of the chapter register and page register, and 11a to 10d are schematic diagrams of the chapter register and page register.
Figure 11b is a schematic diagram of the arithmetic logic unit, Y register and accumulator, Figure 12 is a schematic diagram of a random access memory (RAM), and Figure 13 is a schematic diagram of the 14A and 14B are schematic diagrams of decoding circuits;
Figure b is a schematic diagram of the X register address circuit and write logic, Figure 15 is a schematic diagram of the digit latch circuit, Figure 16 is a diagram of the initialization circuit and test latch, and Figure 17 is a diagram of the register output circuit. 18 is a schematic diagram of the keyboard input circuit and integrated on/off switch, FIGS. 19a-19c are schematic diagrams of the output of the program logic arrangement, and FIG. 20 is a schematic diagram of the segment line. FIG. 21 is a block diagram of a liquid crystal display output circuit; FIG. 22a and 22b are schematic diagrams of the circuit;
The figure is a schematic diagram of the common time generation circuit, and the 23rd
Figures a and 23b are schematic diagrams of the resistor distribution circuit and common buffer, and figure 24a is a diagram of the display.
24b is a schematic diagram of a RAM cell included in the RAM, FIG. 24b is a timing diagram of a display RAM cell, FIG. 24c is a schematic diagram of a display RAM cell structure, and FIG. 24d is a schematic diagram of a display RAM cell structure shown in FIG. 24c. RAM
25a and 25 are schematic cross-sectional views of the cell;
Figure 5b is a circuit diagram of the display RAM and segment buffer, Figure 26 is a block diagram of the oscillator and clock phase generator, Figure 27 is a logic diagram of the oscillator, and Figures 28a and 28b are the oscillator. FIG. 29a is a circuit diagram of a ring counter, regenerative oscillator, and high/low frequency circuit, and FIG. 29b is a circuit diagram of a delay buffer.
Figure 29c is a circuit diagram of a clock buffer;
FIG. 30 is a timing diagram of the oscillator output, FIG. 31 is a timing diagram of the ring counter output, FIG. 32 is a timing diagram of the delay buffer, FIG. 33 is a timing diagram of the clock buffer output, and FIG. Figure 34 is a schematic diagram of the logical form used in the previous figures. 800... Node, 802... Depletion region, 80
8,809...device, 820...latch, 827
...Gate, 400...Common time generator, 45
7...Cross latch, 408...Common buffer.

Claims (1)

[Claims] 1 (a) first and second power supply lines; (b) first and second circuit means disposed between the first and second power supply lines; (c) reverse an inverter circuit comprising first and second clock means for supplying first and second clock signals in a phase relationship, the first circuit means comprising one conductivity type clock signal connected in series; A first clock signal, a second clock signal, and an input signal are supplied to the gates of the first, second, and third transistors, respectively. The first circuit means includes means capable of boosting a node coupling the first and second transistors in response to a second clock signal and an input signal, said second circuit means comprising serially connected transistors. It includes fourth, fifth, and sixth transistors of one conductivity type, the gate of the fourth transistor is connected to the node, and the gates of the fifth and sixth transistors are connected to a second clock signal and an input signal, respectively. A low power circuit characterized in that the output terminal is formed between the fifth and sixth transistors. 2. In claim 1, a seventh transistor is provided between the fifth transistor and the sixth transistor, the gate of the seventh transistor is supplied with the second clock signal, and the fifth
and a seventh transistor, and a second output terminal is formed between the seventh and sixth transistors. 3 (a) first and second power supply lines; (b) first and second circuit means disposed between the first and second power supply lines; and (c) first and second circuit means disposed between the first and second power supply lines; an inverter circuit comprising first and second clock means for supplying first and second clock signals, the first circuit means having first and second clock means of one conductivity type connected in series; a first clock signal and an input signal are supplied to the gates of the first and second transistors, respectively;
The first circuit means includes means capable of inputting a second clock signal and boosting a node connecting the first and second transistors; The gate of the third transistor is connected to the node, and the gates of the fourth and fifth transistors are supplied with a second clock signal and an input signal, respectively. , a low power circuit characterized in that an output terminal is formed between the fourth and fifth transistors.