JPH0547937A - Manufacture of viahole - Google Patents
Manufacture of viaholeInfo
- Publication number
- JPH0547937A JPH0547937A JP22656491A JP22656491A JPH0547937A JP H0547937 A JPH0547937 A JP H0547937A JP 22656491 A JP22656491 A JP 22656491A JP 22656491 A JP22656491 A JP 22656491A JP H0547937 A JPH0547937 A JP H0547937A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- hole
- metal
- back surface
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、バイアホ−ル（Via ho
le）の製造方法に関し、特に、ＩＣ内のバイアホ−ルを
簡単な工程で容易に形成することができるバイアホ−ル
の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a via hole.
le), and more particularly, to a method for manufacturing a via hole capable of easily forming a via hole in an IC by a simple process.
【０００２】[0002]
【従来の技術】従来のバイアホ−ルの製造方法を図２に
基づいて説明する。図２は、従来技術によるバイアホ−
ルの製造法を工程順に示した図である。まず、400μｍ
厚さの半絶縁性ＧａＡｓ基板１を準備し（工程Ａ）、こ
の基板１の表面に、メタルＡ２を形成する（工程Ｂ）。
次に、上記基板１の裏面を研磨し、この基板１の厚さを
100μｍとした後（工程Ｃ）、両面目合せ機を用いて、
裏面から所望位置に穴をあけて貫通させ（工程Ｄ）、そ
の後該裏面にメタルＢ３を形成し（工程Ｅ）、基板表面
と裏面とを導通させる。2. Description of the Related Art A conventional method for manufacturing via holes will be described with reference to FIG. FIG. 2 shows a conventional via-hole.
It is the figure which showed the manufacturing method of the le in the process order. First, 400 μm
A semi-insulating GaAs substrate 1 having a thickness is prepared (step A), and a metal A2 is formed on the surface of this substrate 1 (step B).
Next, the back surface of the substrate 1 is polished to reduce the thickness of the substrate 1.
After setting to 100 μm (step C), using a double-sided aligner,
A hole is made at a desired position from the back surface to penetrate the hole (step D), and then a metal B3 is formed on the back surface (step E) to electrically connect the front surface of the substrate to the back surface.
【０００３】[0003]
【発明が解決しようとする課題】上記従来のバイアホ−
ルの製造方法では、(1) 両面目合せ機を用いて裏面から
穿穴する工程であって、複雑であり、また、(2) バイア
ホ−ル内のメタルのカバ−レッジを良くするために、裏
面のメタル層を厚く形成しなければならないという問題
点があった。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the manufacturing method of a hole, (1) it is a step of making a hole from the back side using a double-sided aligner, which is complicated, and (2) in order to improve the coverage of the metal in the via hole. However, there is a problem in that the metal layer on the back surface must be formed thick.
【０００４】本発明は、上記問題点を解消するバイアホ
−ルの製造方法を提供することを目的とし、詳細には、
簡単な工程により、容易に形成することができるバイア
ホ−ルの製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a via hole which solves the above problems, and more specifically,
It is an object of the present invention to provide a method for manufacturing a via hole which can be easily formed by a simple process.
【０００５】[0005]
【課題を解決するための手段】そして、本発明は、上記
目的を達成するための手段として、基板表面から穴開け
をし、次に、該基板の裏面を研磨して上記穴を貫通させ
ることを特徴とするバイアホ−ルの製造方法である（請
求項１）。また、本発明は、基板表面から穴開けをし、
この穴内にメタル層を形成し、次に、該基板の裏面を研
磨して上記穴を貫通させ、その後該研磨面にメタル層を
形成し、基板表面と裏面とを導通させることを特徴とす
るバイアホ−ルの製造方法である（請求項２）。As a means for achieving the above object, the present invention comprises making a hole in the front surface of a substrate and then polishing the back surface of the substrate to penetrate the hole. A method of manufacturing a via hole characterized by the above (claim 1). In addition, the present invention, by making a hole from the substrate surface,
A metal layer is formed in the hole, the back surface of the substrate is then polished to penetrate the hole, and then a metal layer is formed on the polished surface to electrically connect the front surface and the back surface of the substrate. This is a method for producing via holes (claim 2).
【０００６】従来技術では、前記したとおり、両面目合
せ機を用いて裏面から穿穴する工程であって、複雑であ
るが、本発明では、目合せは基板表面のみであり、基板
裏面は単に研磨することにより貫通穴を形成するもので
あるから、バイアホ−ルを容易に形成することができ
る。In the prior art, as described above, the step of making a hole from the back side using a double-sided aligning machine is complicated, but in the present invention, the alignment is only on the front surface of the substrate, and the back surface of the substrate is simply Since the through hole is formed by polishing, the via hole can be easily formed.
【０００７】また、従来技術では、前記したとおり、バ
イアホ−ル内のメタルのカバ−レッジを良くするため
に、裏面のメタル層を厚く形成しなければならない。こ
れに対して、本発明では、基板裏面のメタルを厚く形成
する必要がなく、薄く形成することができる。これは、
本発明では、基板表面から穴開けをし、この穴内にメタ
ル層を形成するものであり、このメタル層は、バイアホ
−ル内のカバ−レッジを良くするために、厚くしなけれ
ばならないけれども、例えばメッキ手段で所望厚さに形
成することができる。一方、基板裏面のメタルは、本発
明では、例えばスパッタにて薄く形成することができ、
ペレッタイズ時に有利である。Further, in the prior art, as described above, in order to improve the coverage of the metal in the via hole, the metal layer on the back surface must be formed thick. On the other hand, in the present invention, it is not necessary to form the metal on the back surface of the substrate thick, and the metal can be formed thin. this is,
In the present invention, a hole is drilled from the surface of the substrate, and a metal layer is formed in this hole, and this metal layer must be made thick in order to improve the coverage in the via hole. For example, it can be formed to a desired thickness by plating means. On the other hand, in the present invention, the metal on the back surface of the substrate can be formed thin by, for example, sputtering.
It is advantageous when pelletizing.
【０００８】[0008]
【実施例】次に、本発明の実施例を図１に基づいて説明
する。図１は、本発明の実施例であるバイアホ−ルの製
造法を工程順に示した図である。まず、400μｍ厚さの
半絶縁性ＧａＡｓ基板１を準備し（工程Ａ）、この基板
１の表面に100μｍの深さの穴をあける（工程Ｂ）。次
に、この穴内にメタルＡ２を形成した後（工程Ｃ）、該
基板１の裏面より研磨して基板１の厚さを100μｍとし
（工程Ｄ）、貫通穴を形成する。その後、メタルＢ３を
形成し（工程Ｅ）、表面と裏面を導通させる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a view showing a method of manufacturing a via hole according to an embodiment of the present invention in the order of steps. First, a semi-insulating GaAs substrate 1 having a thickness of 400 μm is prepared (step A), and a hole having a depth of 100 μm is formed on the surface of the substrate 1 (step B). Next, after the metal A2 is formed in this hole (step C), the back surface of the substrate 1 is polished to make the thickness of the substrate 1 100 μm (step D), and a through hole is formed. After that, a metal B3 is formed (step E), and the front surface and the back surface are electrically connected.
【０００９】上記工程Ｃにおいて、穴内にメタルＡ２を
形成する手段としては、メッキ法の採用が好ましく、具
体的には、Ａｕをメッキにて所望厚さに形成し、また、
所望のところのみミリングにて残すことができる。ま
た、上記工程Ｅにおいて、基板裏面の研磨面にメタルＢ
３を形成する手段としては、スパッタ法の採用が好まし
く、具体的には、Ａｕをスパッタにて薄く形成すること
ができる。In the step C, as a means for forming the metal A2 in the hole, it is preferable to adopt a plating method. Specifically, Au is formed by plating to a desired thickness, and
Milling can be done only where desired. Further, in the step E, the metal B is polished on the polishing surface on the back surface of the substrate.
As a means for forming 3, it is preferable to adopt a sputtering method, and specifically, Au can be thinly formed by sputtering.
【００１０】[0010]
【発明の効果】本発明は、以上説明したように、基板表
面より穴をあけ、その後基板裏面の研磨によって、その
穴を貫通させる手段を採用するものであり、これによっ
て、バイアホ−ルを容易に製造することができる効果が
生ずる。また、本発明において、目合せは基板表面のみ
であり、そして、基板裏面全面にメタルを形成するのみ
であるから、従来法のような両目合せ機を用いたことに
よる複雑さがない。また、穴内のメタル層は、バイアホ
−ル内のカバ−レッジを良くするために、厚くしなけれ
ばならないけれども、本発明では、例えばＡｕをメッキ
にて形成し、所望のところのみミリングにて残すことが
でき、一方、基板裏面の研磨面に形成するメタルは、例
えばスパッタにてＡｕを薄く形成でき、ペレッタイズ時
に有利である等の効果が生ずる。As described above, the present invention employs means for making a hole from the front surface of the substrate and then polishing the back surface of the substrate to penetrate the hole, thereby facilitating the via hole. The effect that can be manufactured occurs. Further, in the present invention, since the alignment is performed only on the front surface of the substrate and only the metal is formed on the entire back surface of the substrate, there is no complexity due to the use of the double aligning machine as in the conventional method. Further, the metal layer in the hole must be thickened in order to improve the coverage in the via hole, but in the present invention, for example, Au is formed by plating, and is left by milling only where desired. On the other hand, for the metal formed on the polished surface of the back surface of the substrate, Au can be thinly formed by, for example, sputtering, which is advantageous during pelletizing.
【図１】本発明の実施例であるバイア-ホ−ルの製造法
を工程順に示した図である。FIG. 1 is a diagram showing a method of manufacturing a via-hole according to an embodiment of the present invention in the order of steps.
【図２】従来技術によるバイア-ホ−ルの製造法を工程
順に示した図である。FIG. 2 is a diagram showing a method of manufacturing a via hole according to a conventional technique in the order of steps.
１ 半絶縁性ＧａＡｓ基板 ２ メタルＡ ３ メタルＢ 1 Semi-insulating GaAs substrate 2 Metal A 3 Metal B
Claims (3)
表面から穴開けをし、次に、該基板の裏面を研磨して上
記穴を貫通させることを特徴とするバイアホ−ルの製造
方法。1. A method for manufacturing a via hole, which comprises forming a hole in the front surface of a substrate and then polishing the back surface of the substrate to penetrate the hole.
表面から穴開けをし、この穴内にメタル層を形成し、次
に、該基板の裏面を研磨して上記穴を貫通させ、その後
該研磨面にメタル層を形成し、基板表面と裏面とを導通
させることを特徴とするバイアホ−ルの製造方法。2. A method for manufacturing a via hole, wherein a hole is drilled from the surface of a substrate, a metal layer is formed in the hole, and then the back surface of the substrate is polished to penetrate the hole, and then the polishing is performed. A method of manufacturing a via hole, characterized in that a metal layer is formed on a surface of the substrate to electrically connect the front surface and the back surface of the substrate.
成し、研磨面のメタル層は、Ａｕをスパッタにて薄く形
成する請求項２に記載のバイアホ−ルの製造方法。3. The method of manufacturing a via hole according to claim 2, wherein the metal layer in the hole is formed by plating Au, and the metal layer on the polished surface is formed thinly by sputtering Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22656491A JPH0547937A (en) | 1991-08-12 | 1991-08-12 | Manufacture of viahole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22656491A JPH0547937A (en) | 1991-08-12 | 1991-08-12 | Manufacture of viahole |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547937A true JPH0547937A (en) | 1993-02-26 |
Family
ID=16847137
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22656491A Pending JPH0547937A (en) | 1991-08-12 | 1991-08-12 | Manufacture of viahole |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547937A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462419B1 (en) | 1999-06-16 | 2002-10-08 | Nec Corporation | Semiconductor device and method for manufacturing the same |
| US6664640B2 (en) | 2001-07-30 | 2003-12-16 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device |
| US6790694B2 (en) | 2002-08-21 | 2004-09-14 | Kabushiki Kaisha Toshiba | High frequency semiconductor module, high frequency semiconductor device and manufacturing method for the same |
-
1991
- 1991-08-12 JP JP22656491A patent/JPH0547937A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462419B1 (en) | 1999-06-16 | 2002-10-08 | Nec Corporation | Semiconductor device and method for manufacturing the same |
| US6664640B2 (en) | 2001-07-30 | 2003-12-16 | Nec Compound Semiconductor Devices, Ltd. | Semiconductor device |
| US6790694B2 (en) | 2002-08-21 | 2004-09-14 | Kabushiki Kaisha Toshiba | High frequency semiconductor module, high frequency semiconductor device and manufacturing method for the same |
| US6940157B2 (en) | 2002-08-21 | 2005-09-06 | Kabushiki Kaisha Toshiba | High frequency semiconductor module, high frequency semiconductor device and manufacturing method for the same |
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