JPH0547750A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0547750A JPH0547750A JP3199168A JP19916891A JPH0547750A JP H0547750 A JPH0547750 A JP H0547750A JP 3199168 A JP3199168 A JP 3199168A JP 19916891 A JP19916891 A JP 19916891A JP H0547750 A JPH0547750 A JP H0547750A
- Authority
- JP
- Japan
- Prior art keywords
- film
- nitrogen
- passivation film
- reaction chamber
- refractive index
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Plasma Technology (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、よ
り詳しくは、ＥＰＲＯＭを有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an EPROM.
【０００２】近年の半導体装置においては、高集積化と
ともに高信頼化が要求されている。そのため半導体装置
の最終パッシベーション膜の耐湿性を向上する必要があ
る。特に、プラスチックパッケージにより素子を封止す
る場合に重要になる。Recent semiconductor devices are required to have high integration and high reliability. Therefore, it is necessary to improve the moisture resistance of the final passivation film of the semiconductor device. In particular, it becomes important when the device is sealed with a plastic package.
【０００３】[0003]
【従来の技術】ＥＰＲＯＭセルが形成された半導体チッ
プは、図３(A) に示すように、セラミック製のパッケー
ジａに封止されるのが一般的であり、半導体チップｂの
上方には窓ｃが形成され、その窓ｃはガラスｄにより覆
われている。2. Description of the Related Art A semiconductor chip having EPROM cells is generally sealed in a ceramic package a as shown in FIG. 3A, and a window is provided above the semiconductor chip b. c is formed and its window c is covered by glass d.
【０００４】半導体チップｂを覆う最終パッシベーショ
ン膜ｅの材料には、紫外線透過率の優れたＣＶＤ法によ
るＰＳＧ膜、SiO2膜が用いられており、これらの膜は他
の半導体素子に用いられるプラズマＣＶＤ法による窒化
膜に比べて耐湿性が著しく劣っているが、耐湿性に優れ
たセラミック製パッケージａによって封止されているた
めに特に不都合はない。As a material of the final passivation film e covering the semiconductor chip b, a PSG film and a SiO 2 film by a CVD method having an excellent ultraviolet transmittance are used, and these films are plasmas used for other semiconductor elements. Although the moisture resistance is remarkably inferior to the nitride film formed by the CVD method, there is no particular inconvenience because it is sealed by the ceramic package a having excellent moisture resistance.
【０００５】[0005]
【発明が解決しようとする課題】ところで、セラミック
製パッケージａは高価であり、図３(B) に示すような窓
ガラスｆを設けた樹脂製パッケージｇ、或いは透明な樹
脂製パッケージ（不図示）の使用が望まれている。By the way, the ceramic package a is expensive, and a resin package g provided with a window glass f as shown in FIG. 3 (B) or a transparent resin package (not shown). Is desired to be used.
【０００６】しかし、樹脂材は一般に吸湿性が大きく、
耐湿性の劣るSiO2膜等を半導体チップｂの最終パッシベ
ーション膜ｅに用いると、パッケージに吸収された水分
がパッシベーション膜ｅを浸透して半導体素子に到達
し、半導体素子の特性が劣化するといった問題がある。However, the resin material generally has a high hygroscopic property,
When a SiO 2 film or the like having poor moisture resistance is used as the final passivation film e of the semiconductor chip b, the moisture absorbed in the package penetrates the passivation film e and reaches the semiconductor element, which deteriorates the characteristics of the semiconductor element. There is.
【０００７】この場合、パッシベーション膜ｅとして耐
湿性の良いプラズマ窒化膜を使用することも考えられる
が、プラズマ窒化膜は紫外線透過性が悪くＥＰＲＯＭに
使用することはできない。In this case, it is conceivable to use a plasma nitride film having a high moisture resistance as the passivation film e, but the plasma nitride film has a poor ultraviolet transmittance and cannot be used for an EPROM.
【０００８】本発明はこのような問題に鑑みてなされた
ものであって、最終パッシベーション膜の耐湿性、紫外
線透過性を向上することができる半導体装置を提供する
ことを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of improving the moisture resistance and ultraviolet ray transmittance of the final passivation film.
【０００９】[0009]
【課題を解決するための手段】上記した課題は、ＥＰＲ
ＯＭを有する半導体チップの最終パッシベーション膜の
材料として、屈折率が１．４８〜１．６０、窒素含有濃
度が５×１０20〜１×１０22atms／ccである酸化シリコ
ンを用いることを特徴とする半導体装置によって達成す
る。[Means for Solving the Problems] The above-mentioned problems are caused by the EPR.
As a material of a final passivation film of a semiconductor chip having an OM, silicon oxide having a refractive index of 1.48 to 1.60 and a nitrogen content concentration of 5 × 10 20 to 1 × 10 22 atms / cc is used. This is achieved by a semiconductor device that
【００１０】[0010]
【作 用】本発明によれば、屈折率が１．４８〜１．６
０、窒素含有濃度が５×１０20〜１×１０22atms／ccで
ある酸化シリコンを半導体チップの最終パッシベーショ
ン膜として使用している。[Operation] According to the present invention, the refractive index is 1.48 to 1.6.
Silicon oxide having a nitrogen content of 5 × 10 20 to 1 × 10 22 atms / cc is used as the final passivation film of the semiconductor chip.
【００１１】この膜は、プラズマ窒化膜よりも窒素濃度
が低く、またＣＶＤ酸化シリコン膜よりも窒素濃度が高
く、蒸気加圧試験を行ったところ、４０時間を経過して
も膜の水分飽和状態にいたっておらず、耐湿性が良いこ
とがわかった。This film has a lower nitrogen concentration than the plasma nitride film and a higher nitrogen concentration than the CVD silicon oxide film. A steam pressurizing test showed that the film was saturated with water even after 40 hours. It was found that the moisture resistance was good.
【００１２】また、このような最終パッシベーション膜
に覆われたＥＰＲＯＭに紫外線を照射しても、メモリ消
去エラーは生じないことが確認されており、紫外線透過
性が良いことがわかる。Further, it has been confirmed that no memory erasing error occurs even when the EPROM covered with such a final passivation film is irradiated with ultraviolet rays, and it is understood that the ultraviolet transmittance is good.
【００１３】[0013]
【実施例】そこで、以下に本発明の実施例を図面に基づ
いて説明する。図１は、本発明に用いる成膜装置の一例
を示す構成図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing an example of a film forming apparatus used in the present invention.
【００１４】図１において符号１は、平行平板型プラズ
マＣＶＤ成膜装置で、その反応室２の中には、ＥＰＲＯ
Ｍが形成された半導体ウェハ１０を載せる導電性の基板
載置台３が取付けられ、その上方には電極４が基板載置
台３上面に対向して配置されており、基板載置台３と電
極４には高周波電源Ｒｆが接続されている。また、基板
載置台３の下面には基板加熱用のヒータ５が取付けられ
ている。In FIG. 1, reference numeral 1 is a parallel plate type plasma CVD film forming apparatus.
A conductive substrate mounting table 3 on which the semiconductor wafer 10 having M formed thereon is mounted is attached, and an electrode 4 is arranged above the substrate mounting table 3 so as to face the upper surface of the substrate mounting table 3. Is connected to a high frequency power supply Rf. A heater 5 for heating the substrate is attached to the lower surface of the substrate mounting table 3.
【００１５】なお、図中符号６は、反応室２内に反応ガ
スを供給するガス導入管、７は、反応室２内を減圧する
ための排気管を示している。次に、上記した成膜装置を
用いて、半導体ウェハ１０の上に紫外線透過性、耐湿性
の良い最終パッシベーッション膜１１を形成する条件に
ついて説明する。In the figure, reference numeral 6 is a gas introduction pipe for supplying a reaction gas into the reaction chamber 2, and reference numeral 7 is an exhaust pipe for reducing the pressure inside the reaction chamber 2. Next, the conditions for forming the final passivation film 11 having good ultraviolet transparency and moisture resistance on the semiconductor wafer 10 by using the above film forming apparatus will be described.
【００１６】まず第１の例として、電極４と基板載置台
３の間隔を２cmに設定し、高周波電源Ｒｆのパワーを３
０Ｗ、その出力周波数を２００ｋHzとする。また、反応
室２の内部圧力を１.0Torrとし、ヒータ５によるウェハ
加熱温度を３００℃とする。First, as a first example, the distance between the electrode 4 and the substrate mounting table 3 is set to 2 cm, and the power of the high frequency power source Rf is set to 3 cm.
0 W, and its output frequency is 200 kHz. Further, the internal pressure of the reaction chamber 2 is set to 1.0 Torr, and the wafer heating temperature by the heater 5 is set to 300 ° C.
【００１７】この状態で、モノシラン（SiH4）、酸化窒
素（N2O)及び窒素（N2）をそれぞれ１０cc/min、３００
cc/min、１００cc/minの流量でガス導入管６から反応室
２内に導入する。In this state, monosilane (SiH 4 ), nitric oxide (N 2 O) and nitrogen (N 2 ) were added at 10 cc / min and 300, respectively.
It is introduced into the reaction chamber 2 through the gas introduction pipe 6 at a flow rate of cc / min and 100 cc / min.
【００１８】このような条件によれば、半導体ウェハ１
０の上にSiO2膜が形成され、その屈折率は１．４８〜
１．４９、窒素の含有量は１×１０21atms／ccとなり、
このSiO2膜を最終パッシベーション膜１１として用い
る。According to such conditions, the semiconductor wafer 1
0 has a SiO 2 film formed on it, and its refractive index is 1.48-
1.49, nitrogen content is 1 × 10 21 atms / cc,
This SiO 2 film is used as the final passivation film 11.
【００１９】また、２気圧、１２０℃の温度の条件下
で、蒸気加圧試験（ＰＣＴ：PressureCooker Test) に
より評価を行ったところ、図２に示すように、○でプロ
ットした実線で示すような結果が得られ１４時間経過時
にも水分透過量が飽和していない。さらに、経過時間を
４０時間にしても、飽和状態まで達していなかった。し
かも、紫外線を照射して半導体ウェハ１０内のＥＰＲＯ
Ｍセルのメモリを消去したところ、消去エラーは生じな
かった。Further, when evaluated by a vapor pressure test (PCT: Pressure Cooker Test) under the condition of 2 atm and 120 ° C., as shown in FIG. The results were obtained, and the water permeation amount was not saturated even after 14 hours. Furthermore, even when the elapsed time was 40 hours, the saturated state was not reached. Moreover, the EPRO inside the semiconductor wafer 10 is irradiated with ultraviolet rays.
When the memory of M cells was erased, no erase error occurred.
【００２０】なお、蒸気加圧試験の際には、ベアのシリ
コンウェハ上にＰＳＧ（８wt％）を５０００Å積層し、
その上に上記したプラズマＣＶＤによりSiO2膜を 3000
Å成長し、そのSiO2膜を通してＰＳＧ膜に吸収された水
分量を測定して飽和状態を調べた。At the time of the vapor pressure test, PSG (8 wt%) was laminated on a bare silicon wafer at a rate of 5000 Å,
On top of that, a SiO 2 film is deposited on the surface by plasma CVD as described above.
Å The saturated state was investigated by measuring the amount of water absorbed by the PSG film grown through the SiO 2 film.
【００２１】次に第２の成膜例を説明する。電極４と基
板載置台３との間隔を１cmに設定し、高周波電源Ｒｆの
パワーを２５０Ｗ、その周波数を 13.56ｋHzとする。ま
た、反応室２の内部圧力を２．５Torrまで減圧するとと
もに、ヒータ５により半導体ウェハ１０を加熱し、成長
温度を３００℃とする。Next, a second film forming example will be described. The distance between the electrode 4 and the substrate mounting table 3 is set to 1 cm, the power of the high frequency power source Rf is 250 W, and the frequency thereof is 13.56 kHz. Further, the internal pressure of the reaction chamber 2 is reduced to 2.5 Torr, the semiconductor wafer 10 is heated by the heater 5, and the growth temperature is set to 300 ° C.
【００２２】また、SiH4、N2O 、N2をそれぞれ５０cc/m
in、５００cc/min、２５００cc/minの流量で反応室２内
に導入し、半導体ウェハ１０に膜を形成すると、このよ
うな条件により形成されたSiO2膜は、屈折率が１．４９
〜１．５１、窒素の含有量は１×１０21atms／ccとな
る。Further, SiH 4 , N 2 O and N 2 are each 50 cc / m 2.
When a film is formed on the semiconductor wafer 10 by introducing into the reaction chamber 2 at a flow rate of in, 500 cc / min and 2500 cc / min, the SiO 2 film formed under such conditions has a refractive index of 1.49.
˜1.51, the nitrogen content is 1 × 10 21 atms / cc.
【００２３】この膜を上記と同一条件で蒸気加圧試験を
行ったところ、図２の×のプロットで示すような結果が
得られ、１４時間経過時にも水分透過量が飽和せず、水
分の侵入を遮断していることが確かめられ、耐湿性の良
いことが分かった。４０時間についても同様である。When this membrane was subjected to a steam pressurization test under the same conditions as above, the results shown in the plot of X in FIG. 2 were obtained, and the moisture permeation amount was not saturated even after 14 hours, and It was confirmed that the invasion was blocked, and the moisture resistance was found to be good. The same applies to 40 hours.
【００２４】しかも、このSiO2膜を最終パッシベーショ
ン膜１１に適用しても、紫外線によりＥＰＲＯＭセルの
メモリが消去し、この膜は紫外線透過性に優れているこ
とが明らかになった。Moreover, even when this SiO 2 film was applied to the final passivation film 11, it was revealed that the memory of the EPROM cell was erased by ultraviolet rays, and that this film was excellent in ultraviolet transmittance.
【００２５】これに対し、一般的な条件で形成されるSi
O2膜のＰＣＴを行ったところ、図２の破線で示すよう
に、６時間経過した時点で水分飽和状態となり、吸水性
が高く半導体装置の特性を劣化させることが確認されて
いる。On the other hand, Si formed under general conditions
When the PCT of the O 2 film was performed, it was confirmed that, as shown by the broken line in FIG. 2, the water saturated state was reached after 6 hours and the water absorption was high and the characteristics of the semiconductor device were deteriorated.
【００２６】SiO2膜の一般的な成長条件を例示すると、
反応室の内部圧力を３.0Torr、ヒータによる加熱温度を
３００℃、電極３，４間距離を１cmとする。また、反応
ガスとしてSiH4、N2O 、N2をそれぞれ５０cc/min、１５
００cc/min、５００cc/minの流量で反応室２内に導入
し、また、高周波電源Ｒｆのパワーを１５０Ｗ、その周
波数を 13.56ｋHzとする。このような条件により形成さ
れた膜の屈折率は１．４５となり、また、窒素の含有量
は１×１０20atms／cc以下であって上記実施例よりも１
桁小さいことがわかる。As an example of general growth conditions for a SiO 2 film,
The internal pressure of the reaction chamber is 3.0 Torr, the heating temperature by the heater is 300 ° C., and the distance between the electrodes 3 and 4 is 1 cm. Also, SiH 4 , N 2 O, and N 2 were used as reaction gases at 50 cc / min and 15 respectively.
It is introduced into the reaction chamber 2 at a flow rate of 00 cc / min and 500 cc / min, and the high frequency power supply Rf has a power of 150 W and a frequency of 13.56 kHz. The film formed under these conditions has a refractive index of 1.45, and the nitrogen content is 1 × 10 20 atms / cc or less, which is 1 as compared with the above embodiment.
You can see that it is orders of magnitude smaller.
【００２７】さらに、一般的なプラズマＣＶＤによる窒
化膜の屈折率は２．０程度であり、窒素含有量は１×１
０23atms／cc以上である。以上のことから、SiO2膜の窒
素の含有量により耐湿性、紫外線透過性が決定されると
考えられ、ＥＰＲＯＭを有する半導体チップを覆う最終
パッシベーション膜の材料としては、窒素含有量を窒化
膜よりも少なく、一般的なSiO2膜よりも多い窒素含有
量、即ち５×１０20〜１×１０22atms／ccの範囲の量に
設定すればよい。Further, the refractive index of a general plasma CVD nitride film is about 2.0, and the nitrogen content is 1 × 1.
0 23 atms / cc or more. From the above, it is considered that the moisture resistance and the ultraviolet transmittance are determined by the nitrogen content of the SiO 2 film, and as the material of the final passivation film which covers the semiconductor chip having the EPROM, the nitrogen content is higher than that of the nitride film. However, the nitrogen content may be set higher than that of a general SiO 2 film, that is, in the range of 5 × 10 20 to 1 × 10 22 atms / cc.
【００２８】なお、上記した反応ガスのうちのN2O はソ
ースガスであって窒素含有を決定する要因になるが、こ
れらの例ではN2は希釈ガスとして作用するために、窒素
の含有量にはあまり影響を与えない。Of the above reaction gases, N 2 O is a source gas and is a factor that determines the nitrogen content. However, in these examples, since N 2 acts as a diluent gas, the content of nitrogen is Does not affect much.
【００２９】[0029]
【発明の効果】以上述べたように本発明によれば、屈折
率を１．４８〜１．６０、窒素濃度を５×１０20〜１×
１０22atms／ccとした酸化シリコンを半導体チップの最
終パッシベーション膜として使用しているので、窒素含
有量がそれよりも多いプラズマ窒化膜の性質と、窒素含
有量がそれよりも少ないＣＶＤシリコン酸化膜との両方
の性質を兼ね備えており、耐湿性と紫外線透過性が良
く、半導体素子の特性の劣化やＥＰＲＯＭのメモリ消去
エラーの発生を防止することができる。As described above, according to the present invention, the refractive index is 1.48 to 1.60 and the nitrogen concentration is 5 × 10 20 to 1 ×.
Since silicon oxide of 10 22 atms / cc is used as the final passivation film of the semiconductor chip, the properties of the plasma nitride film having a higher nitrogen content and the CVD silicon oxide film having a lower nitrogen content are used. Both of them have excellent properties such as moisture resistance and ultraviolet ray transparency, and it is possible to prevent the deterioration of the characteristics of the semiconductor device and the memory erase error of the EPROM.
【図１】本発明の半導体装置における膜の形成に使用さ
れる成膜装置の一例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of a film forming apparatus used for forming a film in a semiconductor device of the present invention.
【図２】本発明に適用する膜の試験結果を従来との比較
において示す特性図である。FIG. 2 is a characteristic diagram showing test results of a film applied to the present invention in comparison with a conventional one.
【図３】半導体装置の一例を示す断面図である。FIG. 3 is a cross-sectional view showing an example of a semiconductor device.
１ プラズマＣＶＤ成膜装置 ２ 反応室 ３ 基板載置台 ４ 電極 ５ ヒータ ６ ガス導入管 ７ 排気管 10 半導体ウェハ 11 最終パッシベーション膜 1 Plasma CVD film forming apparatus 2 Reaction chamber 3 Substrate mounting table 4 Electrode 5 Heater 6 Gas introduction pipe 7 Exhaust pipe 10 Semiconductor wafer 11 Final passivation film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０５Ｈ 1/18 9014−2Ｇ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H05H 1/18 9014-2G
Claims (1)
ッシベーション膜の材料として、屈折率が１．４８〜
１．６０、窒素含有濃度が５×１０20〜１×１０22atms
／ccである酸化シリコンを用いることを特徴とする半導
体装置。1. A material for a final passivation film of a semiconductor chip having an EPROM has a refractive index of 1.48 to.
1.60, nitrogen content concentration is 5 × 10 20 to 1 × 10 22 atms
A semiconductor device characterized by using silicon oxide / cc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3199168A JPH0547750A (en) | 1991-08-08 | 1991-08-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3199168A JPH0547750A (en) | 1991-08-08 | 1991-08-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547750A true JPH0547750A (en) | 1993-02-26 |
Family
ID=16403290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3199168A Withdrawn JPH0547750A (en) | 1991-08-08 | 1991-08-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547750A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5851602A (en) * | 1993-12-09 | 1998-12-22 | Applied Materials, Inc. | Deposition of high quality conformal silicon oxide thin films for the manufacture of thin film transistors |
| FR2788880A1 (en) * | 1998-10-29 | 2000-07-28 | Lg Philips Lcd Co Ltd | SILICON OXIDE LAYER FORMATION METHOD AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR THEREOF |
| US6121685A (en) * | 1993-06-03 | 2000-09-19 | Intel Corporation | Metal-alloy interconnections for integrated circuits |
| CN106981459A (en) * | 2016-01-15 | 2017-07-25 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacture method |
-
1991
- 1991-08-08 JP JP3199168A patent/JPH0547750A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6121685A (en) * | 1993-06-03 | 2000-09-19 | Intel Corporation | Metal-alloy interconnections for integrated circuits |
| US5851602A (en) * | 1993-12-09 | 1998-12-22 | Applied Materials, Inc. | Deposition of high quality conformal silicon oxide thin films for the manufacture of thin film transistors |
| US5861197A (en) * | 1993-12-09 | 1999-01-19 | Applied Materials, Inc. | Deposition of high quality conformal silicon oxide thin films on glass substrates |
| FR2788880A1 (en) * | 1998-10-29 | 2000-07-28 | Lg Philips Lcd Co Ltd | SILICON OXIDE LAYER FORMATION METHOD AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR THEREOF |
| US6337292B1 (en) | 1998-10-29 | 2002-01-08 | Lg. Philips Lcd Co., Ltd. | Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby |
| US6627545B2 (en) | 1998-10-29 | 2003-09-30 | Lg.Philips Lcd Co., Ltd | Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby |
| US6716752B2 (en) | 1998-10-29 | 2004-04-06 | Lg.Philips Lcd Co., Ltd. | Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby |
| US7378304B2 (en) | 1998-10-29 | 2008-05-27 | Lg.Philips Lcd Co., Ltd. | Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby |
| CN106981459A (en) * | 2016-01-15 | 2017-07-25 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacture method |
| CN106981459B (en) * | 2016-01-15 | 2020-09-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
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| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
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