JPH0547180A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To automatically equalize and precharge a signal outputted from an amplifier based on the signal inputted to an amplifier. CONSTITUTION:The amplitude levels of signals IN, INB inputting to the amplifier circuit 1 amplifying a readout signal with a minute amplitude are compared and judged in a comparing and controlling part 2, and simultaneously an equalizing/precharging signal EQ0 is generated based on the above-mentioned comparison and judgment and supplied to an equalizing and precharging circuit 4 and the output signals OUT, OUTB of the above-mentioned amplifier circuit 1 are equalized and precharged automatically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to increasing a data reading speed,
It is suitable to be used for equalizing or precharging a read signal.

[0002]

2. Description of the Related Art As is well known, in order to increase the speed of reading data, read signals are equalized or precharged. The equalization and precharge are ATD pulse (Address) generated by detecting a change in an external input signal such as an address.
Based on the transition detection), an internal control pulse whose pulse width, timing, etc. are changed is created and used.

FIG. 7 is a circuit diagram showing an example of a conventional equalizing and precharging technique. In FIG. 7, a pulse signal such as an address signal provided to the input terminal 20 is supplied to a predecoder, a redundant circuit (neither is shown) or the like through the address buffer circuit 21. Further, based on the ATD pulse generated by detecting a change in the external input signal M ₁ ... M _n such as an address, the internal signal control pulse signal S _C changes the internal signal control pulse signal S _C.
Is generated by.

The internal signal controlling pulse signal S _C is supplied to equalizing and precharging circuits 23 and 24 provided on the input side and the output side of the sense amplifier 25 (or buffer amplifier), respectively, and supplied in a complementary form. The input signals IN and INB, the output signals OUT and OUTB output from the sense amplifier 25, and the like are equalized and precharged.

[0005]

When the output signals OUT, OUTB, etc. are equalized in this way, the pulse width, timing, etc. must be set accurately. However, the pulse width, timing, etc. must be set as described above. Is difficult to optimize. For this reason, in the early stage of development, a part of the wiring is cut on the chip by using a laser cutter, a focused ion beam device (FIB) or the like, and processing such as connection is performed for tuning. Complex and labor-intensive methods are used. In addition, when using a redundant cell or performing a special operation such as a multi-bit test, it is necessary to change the pulse width, timing, etc. according to the occasion. In view of the above problems, the present invention compares and determines the amplitudes of input signals of an amplifier circuit, and automatically equalizes and precharges the output of the amplifier circuit based on the comparison and determination. The purpose is to

[0006]

A semiconductor memory device of the present invention comprises an amplifier circuit for amplifying a read signal having a minute amplitude,
A comparison control unit for judging the amplitude level of the read signal inputted to the amplifier circuit and deriving an equalize / precharge signal based on the judgment, and an output of the amplifier circuit according to the equalize / precharge signal. It is equipped with an equalize and precharge circuit for equalizing and precharging.

[0007]

According to the present invention, the amplitude levels of the signals inputted to the amplifier circuit for amplifying the read signal of the minute amplitude are compared and judged, and the equalization and precharge signals are generated based on the comparison and judgment to generate the amplifier circuit. By automatically equalizing and precharging the output signal of, the pulse width setting and timing setting required when the internal control pulse is used, and the optimization work are reduced.

[0008]

1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention. The semiconductor memory device of the present embodiment shows a case where read data is complementarily input to the amplifier circuit 1 such as a sense amplifier or buffer and further complementarily output, and the comparison control unit 2 and the equalize / precharge circuit 3, It is composed of 4 etc.

In the semiconductor memory device of this embodiment having the above structure, the equalize / precharge circuit 3 is used.
When the equalizing pulse EQ _i is inputted to the input signals IN and INB at some timing, the comparison control unit 2 detects this. Input signal IN, INB
When it is detected that is equalized, the comparison control unit 2 outputs the equalize and precharge signal EQ _O to the precharge circuit 4 so as to equalize the output line.

Then, after a while, the equalizing signal EQ _i is cut off on the input side, and the amplitudes of the input signals IN and INB widen. When the input amplitude is widened and the amplifier circuit 1 is opened to a level at which it can be driven without malfunctioning, the equalizing and precharge signal EQ _O on the output side is turned off. As described above, in the semiconductor memory device of this embodiment, since the output signal of the amplifier circuit 1 is automatically equalized based on the amplitude of the input signal thereof, it is possible to reliably prevent a malfunction due to the equalization being cut off quickly. can do.

The comparison control unit 2 operates as follows in order to check whether the input level is given as an equalize level or whether the amplitude level is a sufficient amplitude level which does not cause the amplifier circuit 1 to malfunction. It has a function. That is,
The level difference of the complementary inputs is less than a certain value (V _DIF ) or the level of one side of the complementary inputs is more than or less than a reference voltage (V _REF1 or V _REF2 ) or the level of one side of the complementary inputs. Is higher than V _REF1 and the level on the other side is lower than V _REF2 (V _REF1 > V _REF2 ).

When these conditions are satisfied, a signal EQ _O is output and controlled so as to perform equalization and precharge on the equalize and precharge circuit 4 connected to the output of the amplifier circuit 1. .. As a result, the output of the amplifier circuit 1 is automatically equalized and precharged as shown in the timing chart of FIG.

Here, as a method of comparing and judging the levels of the input signals IN and INB, the reference voltages V _REF1 and V _REF2 supplied from the outside or internally generated are compared with the input signal using a comparator.・ There is a method of judgment. Further, a method of utilizing the threshold value of the logic circuit and comparing and determining the input level by considering this as a reference voltage is possible. Also, if the inputs are not complementary and are single phase, then
When V _REF1 ≧ input level ≧ V _REF2 , equalization and precharge may be performed. The outputs may be single-phase or complementary, regardless of whether the inputs are complementary or single-phase. Although various concrete circuits of the comparison control unit 2 can be considered, simple examples for FIG. 1 are shown in FIGS. The circuits shown in FIGS. 3 and 5 both use the input threshold value of the logic circuit as the reference voltage.

In FIG. 3, the comparison control section 2 is composed of an inverter INV1, an inverter INV2, a NOR circuit NOR and the like. The equalize and precharge circuits 3 and 4 are composed of an inverter circuit 5 and a transmission gate 6. In this case, the input threshold value (V _REF2 ) of the inverters INV1 and INV2 is lower than the input equalize and precharge levels, and the input threshold value of the NOR circuit NOR is equal to the input equalizer and precharge INV1 and INV2. Higher than the output level of. Therefore, even if the level on the "H" side of the input is equalized, it is always above the input threshold value V _REF2 , so that the outputs of the inverters INV1 and INV2 are always at the "L" level. ..

On the other hand, the fact that the input is at the "L" level is equalized, and the inverters INV1 and INV are
Those having a voltage higher than the input threshold value V _{REF2 of} 2 are equalized and fall to the “L” level. When the equalization is cut off, the level goes up to "H" again. Then, the output signals of the inverters INV1 and INV2 are supplied to the NOR circuit NOR to generate the equalizing signal EQ on the output side of the amplifier circuit 1 as shown in FIG.

In FIG. 5, the comparison control unit 2 has an inverter IN.
It is composed of V1, an inverter INV2, a NAND circuit NAND, and the like. In this case, the inverter INV1,
The input threshold value (V _REF1 ) of INV2 is higher than the equalization and precharge levels of the input, and the NAND circuit NAN
The input threshold value of D is lower than the output levels of the inverters INV1 and INV2 at the time of input equalization and precharge. Therefore, in this case, even if the level on the "L" side of the input is equalized, the input threshold value V _REF1
Since it is always lower than the above, the inverter INV
The outputs of 1 and INV2 are always at "H" level.

On the other hand, the fact that the input is at "H" level is equalized and the above-mentioned inverters INV1 and INV are
Those having a voltage lower than the input threshold value V _{REF1 of} 2 are equalized and rise to the “H” level. Then, when the equalization is finished, the level goes down to "L" level again. Then, the output signals of INV1 and INV2 are supplied to the NAND circuit NAND, and the equalizing signal EQ on the output side of the amplifier circuit 1 is generated as shown in FIG.

In the semiconductor memory device of this embodiment, since the output signal of the amplifier circuit 1 is automatically equalized and precharged as described above, the internal control pulse is used as in the conventional circuit. You can perform equalization without it. Therefore, it is possible to omit the trouble of setting the width of the internal control pulse or setting the timing, and to omit the problem of optimizing the setting.

Further, equalization and precharge can always be optimized irrespective of the presence / absence of redundant use and the operation mode, and all or part of the ATD circuit can be omitted. Therefore, the power consumption of the ATD circuit can be reduced, and the output capability to the decoder or the ATD output capability of a part required can be enhanced, and the speed of the entire circuit can be increased. Become.

[0020]

As described above, the present invention automatically equalizes and precharges the output of the amplifier circuit based on the amplitude level of the signal input to the amplifier circuit. The output of the amplifier circuit can be equalized without using it. Therefore, it is possible to omit the trouble of setting the width and timing of the internal control pulse and optimizing it. Further, equalization and precharge can always be optimized regardless of the presence / absence of redundant use and the operation mode. Furthermore, ATD
Since all or part of the circuit can be omitted, power consumption in the ATD circuit can be reduced, and the output capability to the decoder or the ATD output capability of a part required can be enhanced. Enables speedup of the entire circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a configuration diagram showing a specific example of a semiconductor memory device of an embodiment.

FIG. 4 is a timing chart showing the operation of the circuit of FIG.

FIG. 5 is a configuration diagram showing another specific example of the semiconductor memory device.

6 is a timing chart showing the operation of the circuit of FIG.

FIG. 7 is a configuration diagram showing an example of a conventional semiconductor memory device.

[Explanation of symbols]

1 amplifier circuit 2 comparison control unit 3 equalize, precharge circuit 4 equalize, precharge circuit IN, INB input signal OUT, OUTB output signal EQ _O equalize, precharge signal V _DIF level difference V _REF1 , V _REF2 reference voltage

Claims (1)

[Claims] 1. An amplifier circuit for amplifying a read signal having a very small amplitude, a comparison control unit for deriving an equalize / precharge signal based on an amplitude level of the read signal input to the amplifier circuit, and the equalize / precharge circuit. A semiconductor memory device comprising: an equalizer for pre-charging an output of the amplifier circuit according to a charge signal;