JPH0546171B2 - - Google Patents
Info
- Publication number
- JPH0546171B2 JPH0546171B2 JP30135587A JP30135587A JPH0546171B2 JP H0546171 B2 JPH0546171 B2 JP H0546171B2 JP 30135587 A JP30135587 A JP 30135587A JP 30135587 A JP30135587 A JP 30135587A JP H0546171 B2 JPH0546171 B2 JP H0546171B2
- Authority
- JP
- Japan
- Prior art keywords
- load
- characteristic
- fold
- current
- current limiting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
Description
【発明の詳細な説明】
〔産業上の利分野〕
本発明は、電源から負荷へ流れる電流が負荷の
短絡等で過大になることを制限し、電源を保護す
る電流制限回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a current limiting circuit that protects a power supply by limiting the current flowing from a power supply to a load from becoming excessive due to a short circuit in the load or the like.
従来、電流制限回路として過電流制限時に電力
消費が著しく増大するのを避ける目的でフの字電
流制限回路が提案されている。
Conventionally, a fold-back current limiting circuit has been proposed as a current limiting circuit for the purpose of avoiding a significant increase in power consumption during overcurrent limiting.
フの字電流制限回路では、第３図に示す負荷特
性図のように負荷側電圧が低くなるほど供給電流
を小さくするため、負荷を接続した状態で電源を
投入した場合、負荷特性曲線がフの字特性曲線Ａ
の上側にないと負荷電圧が充分に供給されない欠
点がある。図において純抵抗特性Ｂであれば問題
はないが、負荷がDC/DCコンバータ等である負
性抵抗曲線Ｃでは、フの字特性曲線Ａの下側にな
る部分があるので負荷電圧が正規の値まで立上や
れない問題があつた。
In a fold-back current limiting circuit, the supply current decreases as the load-side voltage decreases, as shown in the load characteristic diagram shown in Figure 3. Therefore, when the power is turned on with a load connected, the load characteristic curve becomes fold-back. Characteristic curve A
If the voltage is not above , the load voltage will not be sufficiently supplied. In the figure, there is no problem if the pure resistance characteristic is B, but in the negative resistance curve C where the load is a DC/DC converter etc., there is a part below the fold-back characteristic curve A, so the load voltage is not normal. I had a problem where I couldn't get it up to the desired value.
また、フの字電流制限回路に並列に抵抗を接続
し負荷電圧を供給する回路が提案されているが、
負荷の短絡時には抵抗の電力消費が著しく増大す
るため抵抗の選択が難しいなど根本的な問題解決
には至つていない。 In addition, a circuit has been proposed that connects a resistor in parallel to the fold-back current limiting circuit to supply the load voltage.
The fundamental problem has not yet been solved, as the power consumption of the resistor increases significantly when the load is short-circuited, making it difficult to select a resistor.
このようなな問題点を解決するためにこの回路
は、フの字電流制限回路の入力端と出力端の両端
に正特性抵抗急変素子を接続したものである。
In order to solve these problems, this circuit has a positive characteristic resistance rapidly changing element connected to both the input end and the output end of a fold-back current limiting circuit.
この回路は正特性抵抗急変素子に流れる電流に
より、電源投入時には負荷電圧を正規の値まで立
上げ、過電流発生時には電流を制限するものであ
る。
This circuit uses the current flowing through the positive characteristic resistance change element to raise the load voltage to a normal value when the power is turned on, and limits the current when an overcurrent occurs.
本発明の一実施例である回路図を第１図に示
す。図において、１１は直流電源、１２は正特性
抵抗急変素子であり抵抗１３，１４，１５及びト
ランジスタ１６，１７からなるフの字電流制限回
路１８の入力端と出力端の両端に接続されてい
る。１９は負荷である。
A circuit diagram of an embodiment of the present invention is shown in FIG. In the figure, 11 is a DC power supply, and 12 is a positive characteristic resistance rapidly changing element, which is connected to both the input and output ends of a fold-back current limiting circuit 18 consisting of resistors 13, 14, 15 and transistors 16, 17. . 19 is a load.
次に動作について説明する。第２図ａは電源投
入時の電圧−電流特性図を示し、第２図ｂは過電
流制限特性図を示す。図においてＡはフの字特性
曲線、Ｄは常温時における正特性抵抗急変素子の
特性、Ｅは電源投入時の負荷特性曲線、Ｆは過電
流制限時の負荷特性曲線、Ｇは自己発熱時におけ
る正特性抵抗急変素子の特性である。電源投入時
において負荷電流は、正特性抵抗急変素子が常温
で低抵抗となつているため充分大きな値が流れ、
第２図ａに示す負荷特性Ｅのような負荷電圧の立
上上げが可能となる。また、負荷電圧がフの字特
性曲線Ａの非電流制限領域まで達すると、負荷電
流はトランジスタ１７を低い電圧降下を生させ通
過する。過電流制限時には負荷側の短絡時によつ
て負荷電圧が低下しフの字電流制限回路１８ぎ動
作すると共に、正特性抵抗急変素子は負荷電流の
増大による自己発熱によつて抵抗値が増加し第２
図ｂに示す従来のフの字特性曲線Ａに近似した過
電流制限を行う。 Next, the operation will be explained. FIG. 2a shows a voltage-current characteristic diagram when the power is turned on, and FIG. 2b shows an overcurrent limit characteristic diagram. In the figure, A is the fold-back characteristic curve, D is the characteristic of the positive resistance rapidly changing element at room temperature, E is the load characteristic curve at power-on, F is the load characteristic curve at overcurrent limit, and G is the characteristic curve at self-heating. This is a characteristic of a positive characteristic resistance sudden change element. When the power is turned on, the load current flows at a sufficiently large value because the positive characteristic resistance rapidly changing element has a low resistance at room temperature.
It becomes possible to raise the load voltage as shown in the load characteristic E shown in FIG. 2a. Furthermore, when the load voltage reaches the non-current limiting region of the fold-back characteristic curve A, the load current passes through the transistor 17 with a small voltage drop. During overcurrent limiting, the load voltage decreases due to a short circuit on the load side, causing the fold-back current limiting circuit 18 to operate, and the resistance value of the positive characteristic resistance sudden change element increases due to self-heating due to the increase in load current. 2
Overcurrent limitation is performed approximating the conventional fold-back characteristic curve A shown in FIG. b.
以上のように本発明は、電源投入時における充
分な負荷電流の確保と通常動作時の低い電圧降
下、及び過電流制限時の低消費電力化を同時に満
足させるものである。
As described above, the present invention simultaneously satisfies the requirements of ensuring sufficient load current when the power is turned on, low voltage drop during normal operation, and low power consumption during overcurrent limitation.
第１図は本発明の回路図、第２図ａは電源投入
時の電圧−電流特性図、第２図ｂは過電流制限時
の電圧−電流特性図、第３図は負荷特性図であ
る。
１１……直流電源、１２……正特性抵抗急変素
子、１８……フの字特性電流制限回路、１９……
負荷。
Figure 1 is a circuit diagram of the present invention, Figure 2a is a voltage-current characteristic diagram when the power is turned on, Figure 2b is a voltage-current characteristic diagram when overcurrent is limited, and Figure 3 is a load characteristic diagram. . 11... DC power supply, 12... Positive characteristic resistance sudden change element, 18... Fold-back characteristic current limiting circuit, 19...
load.
Claims (1)
電流制限回路において、フの字電流制限回路の入
力端子と出力端子との間に正特性抵抗急変素子を
接続してなる電流制限回路。1. A current limiting circuit that limits excessive current supplied from the power source to the load side, in which a positive characteristic resistance rapidly changing element is connected between the input terminal and the output terminal of the fold-back current limiting circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30135587A JPH01144320A (en) | 1987-11-28 | 1987-11-28 | Current limit circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30135587A JPH01144320A (en) | 1987-11-28 | 1987-11-28 | Current limit circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01144320A JPH01144320A (en) | 1989-06-06 |
| JPH0546171B2 true JPH0546171B2 (en) | 1993-07-13 |
Family
ID=17895867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30135587A Granted JPH01144320A (en) | 1987-11-28 | 1987-11-28 | Current limit circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01144320A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4526899B2 (en) * | 2004-08-09 | 2010-08-18 | 東芝三菱電機産業システム株式会社 | Driving circuit for semiconductor power converter |
| JP5783535B2 (en) * | 2012-03-22 | 2015-09-24 | Fdk株式会社 | DC power supply operation method |
-
1987
- 1987-11-28 JP JP30135587A patent/JPH01144320A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01144320A (en) | 1989-06-06 |
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