JPH054515U - Layout structure of capacitors in semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Objective] In a semiconductor integrated circuit device in which electrodes having electrodes made of different electrode materials are connected in parallel to obtain a desired combined capacitance, the capacitance value does not vary depending on the polarity of an applied voltage. Obtain a capacitor with excellent capacity symmetry. [Structure] On a semiconductor substrate, four capacitors 11 to 14 which are capacitively divided are formed in a 2 × 2 pattern in the horizontal and vertical directions. The first electrodes 11ML and 14ML of the two capacitors 11 and 14 formed at positions not adjacent to each other are connected to one wiring.
22L, and the second electrodes 11SL and 14SL are connected to the other wiring 21L
Connect to. On the other hand, the first electrodes 12M of the two capacitors 12 and 13 which are formed at positions not adjacent to each other.
L and 13ML are connected to the other wiring 21L, and the second electrode 12S
L and 13SL are connected to the one wiring 22L. As a result, the nonuniformity of the film thickness of the dielectric is averaged.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a layout structure of a capacitor in a semiconductor integrated circuit device, which enables to obtain a capacitor having excellent capacitance symmetry.

[0002]

[Prior Art]

 Conventionally, in a semiconductor integrated circuit device in which it is necessary to consider the symmetry of the capacitance of a capacitor, for example, in a semiconductor integrated circuit device in which a voltage controlled oscillator is integrated, the capacitor has a circuit configuration as shown in FIG. Has been done. In FIG. 5, reference numeral 51 is a first MOS capacitor, 52 is a second MOS capacitor, and the first MOS capacitor 51 has a high-concentration impurity diffusion layer whose metal electrode 51M made of, for example, aluminum is connected to the wiring 61. The substrate electrode 51S made of is connected to the wiring 62. On the other hand, in the second MOS capacitor 52, conversely, the metal electrode 52M is connected to the wiring 62 and the substrate electrode 52S is connected to the wiring 61.

In this way, as shown in FIG. 5, two MOS capacitors 51 and 52 designed so that the capacitance becomes one half of the desired capacitance are provided between the two wirings 61 and 62. The metal electrode and the substrate electrode connected to each of the two wirings 61 and 62 are connected in parallel so that the same number of them is provided, so that the symmetry of the capacitance is obtained.

That is, with the circuit configuration shown in FIG. 5, for example, when the wiring 61 becomes positive and the wiring 62 becomes negative, the metal electrode 51M of the first MOS capacitor 51 becomes positive, The substrate electrode 51S becomes negative, and conversely, the second MOS capacitor 52 has its metal electrode 52M negative and the substrate electrode 52S positive. As a result, the change in capacitance due to the difference in electrode material when the polarity of the applied voltage changes is changed by the two capacitors 51 and 52 compared to the case where the desired capacitance is obtained with one MOS capacitor. It is possible to cancel out, and the symmetry of the capacitance is obtained by preventing the capacitance value from changing even if the polarity of the applied voltage changes.

By the way, the circuit configuration as shown in FIG. 5 has a layout as shown in FIG. FIG. 4 is a conventional layout diagram of a capacitor in a semiconductor integrated circuit device. As shown in FIG. 4, the first MOS capacitor 51 is formed on the first-layer substrate electrode 51SL made of a high-concentration impurity diffusion layer formed on the surface layer of the Si substrate and on the first-layer substrate electrode 51SL. Further, it is formed by an insulating film (not shown) as the second layer and a third layer metal electrode 51ML formed on the second layer insulating film (not shown). Then, in the first MOS capacitor 51, the third layer metal electrode 51ML is connected to one third layer wiring 61L, and the first layer substrate electrode 51SL is connected to the other third layer via the through hole contact 51SC. It is connected to the wiring 62L.

The second MOS capacitor 52 includes a first-layer substrate electrode 52SL formed of a high-concentration impurity diffusion layer formed on the surface layer of the Si substrate, and a first-layer substrate electrode 52SL formed on the first-layer substrate electrode 52SL. It is composed of an insulating film (not shown) as two layers and a third-layer metal electrode 52ML formed on a second-layer insulating film (not shown), and the third-layer metal electrode 52ML is on the left side in the figure. Is connected to the other third layer wiring 62L, and the first layer substrate electrode 52SL is connected to the one third layer wiring 61L on the right side in the drawing through a through hole contact 52SC. Thus, conventionally, two capacitors 51 and 52 are formed side by side in the vertical direction (vertical direction in the figure).

[0007]

[Problems to be solved by the device]

 In the conventional layout of the capacitors in the semiconductor integrated circuit device, two capacitors to which the first and second electrodes made of different electrode materials are respectively connected are arranged between the two wirings. Since the first electrode and the second electrode connected to each are connected in parallel so that the number is the same, it is possible to reduce the change in capacitance due to the difference in electrode material when the voltage polarity changes. It is possible. However, since two capacitors are formed side by side in one direction, in the above example, in the vertical direction, when forming a large-capacity capacitor with a large capacitance, the insulating film that is the dielectric of the capacitor is used. Since the thickness tends to be non-uniform, there is a drawback in that the symmetry of the capacitance of the capacitor is easily damaged.

The present invention has been made in order to solve the above-mentioned conventional drawbacks, and is a semiconductor integrated circuit in which electrodes having electrodes made of different electrode materials are connected in parallel to obtain a desired combined capacitance. An object of the present invention is to provide a layout structure of a capacitor in a semiconductor integrated circuit device, which can obtain a capacitor having excellent capacitance symmetry.

[0009]

[Means for Solving the Problems]

 In order to achieve the above object, the layout structure of the capacitor in the semiconductor integrated circuit device according to the present invention is such that the first and second electrodes made of different electrode materials are connected to each other so that a desired combined capacitance is obtained. A plurality of capacitors divided into two capacitors are connected in parallel between two wires so that the first electrode and the second electrode connected to each of the two wires have the same number. In a layout structure of capacitors in a semiconductor integrated circuit device, 2n (n ≧ 2) capacitors, each of which has the first and second electrodes connected to each other and are capacitively divided, are horizontally and vertically arranged on a semiconductor substrate. The first electrode of the two capacitors formed in the 2 × 2 basic pattern and not adjacent to each other in this basic pattern is connected to one wiring. And the second electrode is connected to the other wiring, and the first electrode of the remaining two capacitors formed at positions other than the other adjacent to each other is connected to the other wiring. The second electrode is connected to the one wiring.

[0010]

[Action]

 FIG. 3 is a diagram for explaining the operation of the present invention, in which (a) is a diagram for explaining an example of the arrangement of capacitors according to the present invention, and (b) is related to the present invention. It is a figure which shows the example of a circuit structure of a capacitor.

In the layout structure of the capacitors in the semiconductor integrated circuit device according to the present invention, as shown in FIG. 3A, a basic pattern of 2 × 2 is formed on the semiconductor substrate in the horizontal and vertical directions. At least four capacitors C1 to C4 are divided into equal capacitances so as to have a desired combined capacitance when connected in parallel. Then, as shown in (a) and (b) of FIG. 3, the first electrodes M1 and M4 of the two capacitors C1 and C4 formed at positions not adjacent to each other are connected to one wiring L2. , The second electrodes S1 and S4 made of an electrode material different from that of the first electrode are connected to the other wiring L1.

In addition, the first electrodes M2 and M3 of the remaining two capacitors C2 and C3 which are formed at positions not adjacent to each other are connected to the other wiring L1 and the second electrodes S2 and S3 are connected. Is connected to the above-mentioned one wiring L2. As a result, the two sets of capacitors C1, C4, C2, C3 formed at positions not adjacent to each other are connected to the two wirings L1, L2 as equivalent from the viewpoint of electrical polarity. become.

Therefore, 2n (n ≧ 2) number of capacitors, in which the first and second electrodes made of different electrode materials are connected to each other on the semiconductor substrate and are capacitively divided, are arranged in a horizontal direction and a vertical direction of 2 × 2. Two sets of capacitors C1, C4, C2, C3, which are formed in a pattern and are formed in positions not adjacent to each other in this basic pattern, are electrically connected between the two wirings L1 and L2. By connecting in parallel so as to be equivalent from the viewpoint of polarity, a capacitor having a desired combined capacitance is formed, so that the unevenness of the film thickness of the dielectric insulating film is By averaging, it is possible to obtain a capacitor having excellent capacitance symmetry, in which the capacitance value does not change depending on the polarity of the applied voltage.

[0014]

【Example】

 The present invention will be described below based on embodiments. 1 is a layout diagram of a capacitor in a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a circuit configuration of the capacitor in FIG. In this embodiment, a MOS capacitor will be described as an example.

As the circuit configuration of the capacitor in this embodiment, as shown in FIG. 2, the first to fourth capacitors are so arranged that the capacitance between the two wirings 21 and 22 is one fourth of the desired capacitance. In total, four MOS capacitors 11 to 14 are connected in parallel. In the figure, 11M to 14M are metal electrodes of each capacitor, and 11S to 14S are substrate electrodes of each capacitor.

The circuit configuration shown in FIG. 2 is realized by the layout structure shown in FIG. As shown in FIG. 1, on the Si substrate, in the horizontal direction (left-right direction in the figure) and in the vertical direction (up-down direction in the figure) in a 2 × 2 pattern, the above-mentioned four M's OS capacitors 11-14 are formed.

The circuit configuration shown in FIG. 2 is realized by the layout structure shown in FIG. As shown in FIG. 1, two 2x2 patterns in the horizontal direction (horizontal direction in the figure) and the vertical direction (vertical direction in the figure) on the Si substrate are not adjacent to each other in the horizontal and vertical directions. Two sets of MOS capacitors 11, 14, 12, and 13 are arranged geometrically symmetrically, each set consisting of one set of MOS capacitors.

Of these, the first MOS capacitor 11 of the two MOS capacitors 11 and 14 forming one set is formed at the upper left position in the figure as shown in FIG. The first MOS capacitor 11 includes a first-layer substrate electrode 11SL formed of a high-concentration impurity diffusion layer formed on the surface layer of a Si substrate, and an insulation layer formed on the first-layer substrate electrode 11SL as a second layer. It is formed of a film (not shown) and a third-layer metal electrode 11ML formed on the second-layer insulating film (not shown). Then, in the first MOS capacitor 11, the third layer metal electrode 11ML is connected to one third layer wiring 22L, and the first layer substrate electrode 11SL is connected to the other third layer wiring 21L via the through hole contact 11SC. It is connected to the.

Of the two MOS capacitors 11 and 14 forming the one set, the fourth MOS capacitor 14 is formed at the lower right position in the figure as shown in FIG. Similar to the first MOS capacitor 11, the third layer metal electrode 14ML is connected to one third layer wiring 22L, and the first layer substrate electrode 14SL is connected to the other third layer wiring 21L via the through hole contact 14SC. It is connected to the.

On the other hand, of the two MOS capacitors 12 and 13 forming the other set, the second MOS capacitor 12 is formed at the upper right position in the figure as shown in FIG. The second MOS capacitor 12 is composed of a first-layer substrate electrode 12SL formed of a high-concentration impurity diffusion layer formed on the surface layer of the Si substrate, and a second layer formed on the first-layer substrate electrode 12SL. And an insulating film (not shown) and a third-layer metal electrode 12ML (not shown) formed on the second-layer insulating film. In contrast to the first and fourth MOS capacitors 11 and 14, the second MOS capacitor 12 has its third layer metal electrode 12ML connected to the other third layer wiring 21L. The first layer substrate electrode 12SL is connected to the one third layer wiring 22L via the through hole contact 12SC.

Of the two MOS capacitors 12 and 13 forming the other set, the third MOS capacitor 13 is formed at the lower left position in the figure as shown in FIG. The third-layer metal electrode 13ML is connected to the other third-layer wiring 21L, and the first-layer substrate electrode 12SL is connected to the one-side third layer via the through-hole contact 13SC. It is connected to the wiring 22L.

As described above, in a semiconductor integrated circuit device in which electrodes having electrodes made of different electrode materials are connected in parallel to obtain a desired combined capacitance, four capacitance-divided capacitors are formed on a Si substrate. The MOS capacitors 11 to 14 are formed in a 2 × 2 pattern in the horizontal direction and the vertical direction, and two sets of MOS are formed between the two wirings 21L and 22L at positions not adjacent to each other. Since the capacitors 11, 14, 12, 13 were connected in parallel so as to be equivalent from the viewpoint of electrical polarity, the non-uniformity of the film thickness of the dielectric insulating film is averaged and applied. It is possible to obtain a capacitor with excellent capacitance symmetry, where the capacitance value does not change depending on the voltage polarity. In the above embodiment, an example in which four capacitors are formed in a 2 × 2 pattern in the horizontal and vertical directions is shown, but the present invention is not limited to this, and a basic 2 × 2 pattern in the horizontal and vertical directions. By forming, for example, eight capacitors in the pattern, it is possible to obtain capacitors having better capacitance symmetry.

[0023]

[Effect of the device]

 As described above, according to the layout structure of the capacitor in the semiconductor integrated circuit device according to the present invention, the semiconductor integrated circuit device having electrodes made of different electrode materials and connected in parallel to obtain a desired combined capacitance In the above, the first and second electrodes made of different electrode materials are connected to each other on the semiconductor substrate, and 2n (n ≧ 2) number of capacitors, which are capacitively divided, are arranged in the horizontal and vertical directions. Two sets of capacitors formed by a basic pattern of × 2 and formed between two wirings at positions not adjacent to each other in this basic pattern are equivalent from the viewpoint of electrical polarity. By connecting them in parallel to form a capacitor having a desired combined capacitance, Non-uniformity of the thickness of the insulating film is averaged, is no different capacitance value I by the polarity of the applied voltage, it is possible to obtain an excellent capacitor symmetry capacity.

[Brief description of drawings]

FIG. 1 is a layout diagram of capacitors in a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a circuit configuration of a capacitor in FIG.

FIG. 3 is a view for explaining the operation of this invention.

FIG. 4 is a conventional layout diagram of capacitors in a semiconductor integrated circuit device.

5 is a diagram for explaining a circuit configuration of a capacitor in FIG.

[Explanation of symbols]

 11, 12, 13, 14 ... MOS capacitors 11SL, 12SL, 13SL, 14SL ... First layer substrate electrode 11ML, 12ML, 13ML, 14ML ... Third layer metal electrode 11SC, 12SC, 13SC, 14SC ... Through hole contact 21L, 22L ... Third layer wiring

Claims (1)

[Claims for utility model registration] Claims: 1. A plurality of capacitors, each having a first and a second electrode made of different electrode materials connected to each other and divided into capacitances to have a desired combined capacitance. Between the two wires, the first wire connected to each of the two wires
In a layout structure of a capacitor in a semiconductor integrated circuit device, in which the same number of electrodes and the second electrodes are connected in parallel, the first and second electrodes are formed on a semiconductor substrate.
2n (n ≧
2) two capacitors are formed in a horizontal and vertical direction in a basic pattern of 2 × 2, and one of the first electrodes of the two capacitors formed in positions not adjacent to each other in this basic pattern While connecting the second electrode to the other wire while connecting to the wire, and connecting the first electrode to the other wire in the remaining two capacitors formed at positions not adjacent to each other. A layout structure of a capacitor in a semiconductor integrated circuit device, wherein the second electrode is connected to the one wiring.