JPH0544852B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high voltage circuit having an output stage of CMOS configuration.

[Prior art and its problems]

Conventionally, a circuit as shown in FIG. 2 is known as a high voltage circuit having an output stage of a CMOS configuration. In FIG. 2, 16 is a control signal input terminal, 17 is a high voltage power supply terminal, 18 is a reference potential application terminal, 19 is a high voltage output terminal, 20 is a high voltage capacitor, 21 is a resistor, and 22 is a high voltage PMOS transistor. , 3 are high voltage NMOS transistors. This PMOS transistor 22 and NMOS transistor 23 constitute a high voltage inverter.

In the high voltage circuit configured as above, if we consider the case where the input signal to the input terminal 16 is periodic, it is determined by the capacitor 20 and the resistor 21.
The CR time constant needs to be sufficiently larger than the period of the signal input to the input terminal 16. Therefore, the capacitance value of the capacitor 20 and the resistance value of the resistor 21 must be selected in accordance with the input signal. On the other hand, if the input signal is not periodic, for example direct current, and has little change, and the time between signal change points is long, the charge stored in the capacitor 20 will be discharged, so the PMOS transistor 2
2 is turned off regardless of the input signal to the control signal input terminal 16, causing a malfunction of the high voltage CMOS transistor composed of MOS transistors 2 and 23.

Conventional high-voltage circuits with CMOS-configured output stages have the disadvantage of malfunctioning in response to non-synchronous signals with little variation, and in the case of input capacitance and resistance values in response to periodic signals. It has the disadvantage that selection must be made in accordance with the signal.

[Purpose of the invention]

The object of the present invention is to provide a
An object of the present invention is to provide a high voltage circuit having an output stage with a CMOS configuration.

[Structure of the invention]

The present invention provides a high voltage circuit having an output stage of a complementary circuit including a load transistor and a drive transistor, in which a capacitor and an input terminal are connected between a control signal input terminal of the complementary circuit and a gate of the load transistor. comprising a series circuit with a bistable element having logically the same output, one terminal of the capacitor being connected to the control signal input terminal;
The output terminal of the bistable element is connected to the gate of the load transistor, and the control signal input terminal is further connected to the gate of the drive transistor.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This embodiment has a high voltage output stage with a CMOS configuration, in which an N-well is formed on a p-type substrate, a PMOS high-voltage transistor is formed in the N-well, and a high-voltage NMOS transistor is formed in the P-type substrate region. It is an integrated circuit.

This high voltage circuit includes an output stage with a CMOS configuration consisting of a PMOS transistor 1 and an NMOS transistor 2, a bistable element 3 consisting of two sets of inverters and having an output that is logically the same as the input, and a high voltage capacitor 4. We are prepared. capacitor 4
One end of the capacitor 4 is connected to the control signal input terminal 5, and the other end of the capacitor 4 is connected to the input terminal 6 of the bistable element 3. Output terminal 7 of bistable element 3 is PMOS
Connected to the gate of transistor 1. The control signal input terminal 5 is also connected to the gate of the NMOS transistor 2.

Bistable element 3 is a high voltage PMOS transistor,
high voltage PMOS transistor 9 and two resistors 10,
11, and the input terminal 6 of the bistable element.
is connected to the gate of the PMOS transistor 8, and the output terminal 7 is connected to the drain of the PMOS transistor 9. Further, the gate of the PMOS transistor 8 is connected to the drain of the PMOS transistor 9, and the gate of the PMOS transistor 9 is connected to the drain of the PMOS transistor 8. these
The sources of the MOS transistors 8 and 9 are connected to the high voltage terminal 12, and the drains are connected to the resistors 10 and 9, respectively.
11 and is connected to a voltage application terminal 13.

The high voltage power supply terminal 12 is further connected to the source of the PMOS transistor 1, the connection point between the drain of the PMOS transistor 1 and the drain of the NMOS transistor 2 is connected to the high voltage output terminal 14, and the source of the NMOS transistor 2 is connected to the reference It is connected to the voltage application terminal 15.

A voltage of, for example, 200V is applied to the high voltage power supply terminal 12, and a voltage of, for example, 0V is applied to the reference potential application terminal 15.
voltage is applied. A signal of, for example, 10V is input to the control signal input terminal 5, and a voltage of, for example, 190V is input to the voltage application terminal 13, which is lower than the voltage of 200V at the high voltage power supply terminal 12 by the amplitude voltage of the input signal at the control signal input terminal 5. A voltage is applied.

Next, the operation of the high voltage circuit of this embodiment will be explained.

When an input signal of 10V is applied to the control signal input terminal 5, the state of the NMOS transistor 2 immediately changes from off to on. On the other hand, the input signal passes through the high voltage capacitor 4 to the input terminal 6 of the bistable element 3.
transmitted to. This turns off the PMOS transistor 8 and turns on the PMOS transistor 9. As a result, the input signal is latched, and a signal in phase with the latched signal is output to the output terminal 7 of the bistable element 3. This signal is applied to the gate of the PMOS transistor 1, which turns off the transistor 1 and the voltage at the output terminal 14 of the high voltage circuit becomes 0V.

Conversely, when the input signal is no longer applied to the control signal input terminal 5, the NMOS transistor 2 is turned off.
On the other hand, the state of bistable element 3 is reversed and the PMOS
Transistor 1 turns on and high voltage output terminal 1
4 outputs a voltage of 200V.

As described above, according to this embodiment, the input signal to the control signal input terminal 5 is latched by the bistable element 3, and the PMOS transistor 1 is turned on and off by the latched input signal, so that the input signal is Even if the time between signal change points is long and the capacitor 4 is discharged during this period, as long as it has a capacitance value that can invert the bistable element 3, the CMOS inverter can operate normally. It can be made to work. Generally, the capacitance value of the capacitor 4 required to invert the state of the bistable element may be much smaller than the high voltage capacitor of the conventional high voltage circuit shown in FIG. Furthermore, even if the input signal is periodic, the capacitance value of the high voltage capacitor 4 only needs to have a capacitance value necessary for inverting the state of the bistable element 3, regardless of the input signal. This eliminates the need for selecting the CR time constant in response to the input signal, which is required in conventional high-voltage circuits.

In this way, according to this embodiment, the capacitance value of the high voltage capacitor 4 can be made very small, which means that in an integrated circuit, the high voltage capacitor and resistor in the conventional circuit require a large area. In contrast, this means that it can be made in a small area. Therefore, the high voltage circuit of the present invention is particularly effective when integrated.

In the above embodiments, a CMOS circuit with an N-well structure has been explained as an example, but a CMOS circuit with a P-well structure has been described.
It is clear that the present invention can be similarly implemented with a CMOS circuit. Further, in the above embodiment, an element composed of two sets of inverters was used as an example of a bistable element, but the present invention can also be easily implemented using other bistable elements.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a high voltage circuit in which the output stage configured with CMOS operates normally for any input signal.

In addition, the present invention provides dielectric isolation between each element.
When applied to CMOS circuits, such as CMOS/SOS, it is ideal as a CMOS circuit.
In the case of CMOS/SOS, etc., the substrate of each transistor can be at the same potential as the source of each transistor, so the bistable element can be configured in CMOS. Therefore, it is possible to dramatically reduce the power consumption of the bistable element, making it ideal for high-voltage integrated circuits.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a high voltage circuit according to the present invention, and FIG. 2 is a diagram showing a conventional high voltage circuit. 1, 8, 9, 22... High voltage PMOS transistor, 2, 23... High voltage NMOS transistor,
3... Bistable element, 4, 20... High voltage capacitor, 5, 16... Control signal input terminal, 6... Input terminal of bistable element, 7... Output element of bistable element, 10, 11, 21...Resistance, 12,17...
High voltage power supply terminal, 13... Voltage application terminal, 14,
19...High voltage output terminal, 15, 18...Reference potential application terminal.

Claims (1)

[Claims] 1. In a high voltage circuit having an output stage of a complementary circuit consisting of a load transistor and a drive transistor, a capacitor is connected between the control signal input terminal of the complementary circuit and the gate of the load transistor, and the output stage is connected logically to the input. comprising a series circuit with a bistable element having the same output, one terminal of the capacitor being connected to the control signal input terminal, an output terminal of the bistable element being connected to the gate of the load transistor, and one terminal of the capacitor being connected to the control signal input terminal; A high voltage circuit characterized in that an input terminal is further connected to the gate of the drive transistor.