JPH0542182B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention mainly relates to an FDM/TDM conversion regenerative relay satellite communication system that performs mutual communication between a large number of small stations via a communication satellite.

[Prior Art] Small station communication systems that perform communication between a plurality of small earth stations via communication satellites are becoming promising. In small station communication systems, the SCPC/FDM method, which transmits and receives SCPC digital modulated signals by frequency division multiplexing (FDM), is dominant because of the simplicity of the equipment. However, in the SCPC/FDM method, when multiple carriers are commonly amplified in a transponder on a satellite, the operating point is set with sufficient back-off to reduce cross-modulation interference caused by nonlinear distortion of the amplifier. There is a need to. Therefore, a loss occurs in downlink signal power by the amount of output backoff.

As a promising method to improve this point, a method is being considered that performs FDM/TDM conversion on a satellite and then demodulates the TDM-converted signals of each channel using a multiplexing demodulation circuit. This method is
For example, "Frequency multiplexing using Chirp transform"
"Study of PSK signal simultaneous demodulation method" IEICE Satellite Communications Subcommittee SAT84-40 P17-24, Takeharu Gun (hereinafter referred to as
Reference 1). Here, we show that when signal regeneration is performed on a satellite, the uplink and downlink are separated and the addition of noise on the uplink and downlink is suppressed, which alone can significantly improve the BER.

FIG. 9 shows an example of a configuration for implementing the method of Document 1. 1 is a satellite antenna, 2 is a branching filter, 3 is an LNA
and a receiving device including a down converter, 90 a chirp filter, 91 a chirp signal generator, 9
2 is a mixer, 93 is a multiplexing demodulation circuit, 7 is a modulation circuit, and 8 is a transmitter including an up converter and an HPA. On the other hand, 10 is an earth station, 11 is a ground station antenna, 12 is a duplexer, 13 is a receiving device, 14
15 is a demodulator, 15 is a reception baseband signal processing circuit, 16 is a clock generation/synchronization circuit, 17 is a transmission baseband signal processing circuit, 18 is a modulator, 19
is the transmitting device.

FIG. 10 shows the basic configuration of the chirp Z conversion circuit shown in FIG. 9, and FIG. 11 shows input/output signal waveforms of each part in FIG. Referring to FIGS. 10 and 11, an input IF signal 201 (FIG. 11a) is swept by a first chirp signal 202 (FIG. 11b) from a chirp signal generator 91, Output 204 as shown in figure d
is obtained. This output 204 is generated by the second chirp signal 205 from the chirp signal generator 91.
The output baseband signal 206 is as shown in FIG. f. The Chirp Z-transform method, as detailed in Reference 1, is a powerful method for performing Fourier transform at high speed, and the FDM signal is naturally pulse-compressed.
The signal is converted into a sin x/x type signal as shown in FIG. 12a. Since the compressed pulse becomes 0 at regular time intervals, if the system is designed so that pulses from adjacent channels appear there, FDM/TDM conversion can be performed without interference between channels.

However, for this purpose, the break timing of the input IF signal 201 shown in FIG. 11a must match the sweep timing of the satellite's first chirp signal 202 shown in FIG. 11b. If there is an error in the timing between the two, the pulse waveform will deviate from the sin x/x shape shown in FIG. 12a, and interference between channels will occur. In particular, when the timing phase error is π, as shown in FIG. 12b,
Not only will the signal not appear at its original time position, but it will also cause the greatest amount of interference to adjacent channels. Therefore, in order to prevent interference between channels,
It is necessary to completely synchronize the transmission clock timing of each earth station with the frequency sweep timing of the chirp signal on the satellite.

[Problems to be Solved by the Invention] As described above, since clock phase errors immediately cause interference between channels, it is necessary to achieve extremely high precision clock synchronization.

Further, as a chirp filter, a SAW element is generally used, and problems such as variations in the chirp rate of the chirp filter and temperature fluctuations in frequency are also serious.

Furthermore, in small station communication systems, narrowband communication is normally performed due to limitations on power and frequency bands, but as is clear from Figure 11, the chirp filter is at least twice the data period. , which makes the circuit difficult to implement for narrower band signals.

The present invention is applied to a satellite communication system that receives a digitally modulated and FDM multiplexed signal, converts it from FDM to TDM, and regenerates it. The objective is to provide an FDM/TDM conversion regenerative relay satellite communication system that is free from interference and achieves stable characteristics with an all-digital configuration.

[Means for Solving the Problems] The present invention provides the above-mentioned means mounted on a satellite for receiving and processing SCPC digitally modulated and FDM multiplexed signals from a plurality of earth stations.
A transformer multiplexer type branching circuit (hereinafter referred to as
TMUX), the FDM clock and TDM
A phase difference with the TDM clock is detected, and a signal interpolation value (hereinafter referred to as an identification signal) at the TDM clock timing is calculated for each output channel of the TMUX based on the detected phase difference. Intermediate timing of TDM clock (reverse phase TDM
an interpolation circuit that calculates a signal interpolation value (hereinafter referred to as a zero-crossing signal) at the clock timing), and a data reproduction that performs data reproduction on the identification signal from the interpolation circuit and outputs it as demodulated data. a clock that has a circuit and detects a phase error of a transmitting clock of a transmitting signal of each earth station with respect to the TDM clock from the demodulated data and the zero-crossing signal, averages the detected phase error, and outputs it as clock phase error data. A digital demodulation circuit having a phase error detection circuit, and a demodulated signal (demodulated data and clock phase error data) of each channel from the digital demodulation circuit, and the demodulated data is arranged frame by frame at a time position determined by the channel. Regarding the clock phase error data, a time division multiplexing circuit is provided which performs time division multiplexing at a predetermined time position for each fixed number of frames (super frames) in an order determined by the channel, and the time division multiplexing signal from the time division multiplexing circuit is provided. , the common carrier wave on the satellite is modulated and sent to the downlink, and each earth station regenerates the time division multiplexed signal to establish frame and super frame synchronization, as well as transmitting clock phase error data of its own station. and further controls the transmitting clock phase of its own station based on the transmitting clock phase error data to establish clock synchronization in a loop including the round trip to the satellite.
This is an FDM/TDM conversion and regeneration relay satellite communication system that performs FDM/TDM conversion and signal regeneration on a satellite.

[Example] An example of the present invention is shown in FIG. The same parts as in FIG. 9 are given the same numbers. To explain the circuit configuration installed on satellite 9, 4 is TMUX
5 is a signal interpolation/demodulation circuit, and 6 is a time multiplexing (TDM) circuit.

FIG. 2 shows details of the satellite onboard circuit according to the invention. 20 is a local oscillator, 21 is a π/2 phase shifter, 2
2 and 23 are mixers, 24 and 25 are A/D converters with sampler functions, 26 is a clock source oscillator for TMUX, 27 and 28 are frequency dividers, and 29 is TMUX
type branching circuit, 30 is a latch circuit, 31-1 to 31
-N is an interpolation circuit, 32 is a TDM clock source oscillator, 33 is a frequency divider, 34-1 to 34-N are demodulation circuits, 35 is a time multiplexing circuit, 36 is a four-phase modulation circuit,
37 is a carrier oscillator.

Here, the TMUX type branching circuit 29 in FIG. 2 is added to the TMUX type branching circuit 4 in FIG.
1 to 31-N and demodulation circuits 34-1 to 34-N correspond to the signal interpolation/modulation circuit 5 in FIG. 1, and the time multiplexing circuit 35 corresponds to the time multiplexing circuit 6 in FIG. 1, respectively.

FIG. 3 shows the digital section of the TMUX type branching circuit 29 of FIG. 40 is a serial to parallel conversion circuit for converting N-channel serial input data into parallel output data, 41-1 to 41-N are digital filters, and 42 is an FFT (fast Fourier transform) circuit.

FIG. 4 shows details of the interpolation circuit 31 shown in FIG. 50 is a shift register; 51 and 52 are ROMs for storing filter tap coefficients, which will be described later;
53 is a latch circuit, 54 is a multiplier, and 55 is an adder, the operation of which will be described later.

FIG. 5 shows the sampling timing of data and clock phase error signals in an interpolation operation to be described later.

FIG. 6 shows details of the demodulation circuit 34 shown in FIG. 60 is a complex multiplier, 61 is a VCO, 62
63 is a carrier phase error detection section, and 64 is a clock phase error detection section. 65
is a multiplier, 66 and 67 are adders, and 68 and 69 are for cosine signal and sine signal generation, respectively.
ROM, 70 is a 1-bit delay memory, 71 is an adder, 72 is a constant multiplier, 73 is an adder, 74 is a multiplier, 75 is an adder, 76 is a data identifier, 77
is an exclusive OR gate, 78 is a change check circuit, 7
9 is a digital LPF, and 80 is an adder.

FIG. 7 shows a downlink signal frame structure.

The operation of the above-mentioned satellite-side onboard circuit of the present invention will be explained below. First, in Figure 2, the received reception
The IF FDM signal is separated for each channel at the TMUX29 output, frequency-converted to the OHz band, and further
It is sampled by the FDM clock (divider 28 output) and output. The operation of TMUX29 is
"TDM-EDM Transmultiplexer: Digital
"Polyphase and FFT" (IEEE
TRANSACTION ON COMM UNICATION,
VOL.COM-22, No.9SEPTEMBER1974), but will be briefly explained.

As shown in FIG. 3, the TMUX 29 includes N digital filters 41-1 to 41-N.
The FDM clock is used to receive IF FDM using a transformer multiplexer method using the FFT circuit 42.
It separates signals. That is, the receive IF
Each FDM channel of the FDM signal is channelized in units of FDM clock frequency, and in the transformer multiplexer method, as shown in Figure 13,
The first Δf step where Δf = FDM clock frequency
~Nth FDM channel separation is performed using fully digital signal processing. TMUX is essentially complex signal processing, where each channel output consists of real and imaginary signals. Also, as is clear from Figure 13, each
FDM channels are completely separated on the frequency axis, so if the frequency of the transmitting carrier from the earth station is correct, no inter-channel interference will occur.

However, in general, the data rate of each channel and
FDM clocks are asynchronous in frequency and phase. Therefore, in order to perform FDM/TDM conversion, the sample must be resampled with a TDM clock that matches the data rate. For this purpose, it is necessary to perform signal interpolation. In order to perform signal interpolation, the timing to be interpolated, that is, the TDM clock (clock oscillator 32
output) and the timing of the output data string of TMUX29, that is, the FDM clock (output of frequency divider 28)
It is necessary to know the time difference (phase difference) between This time difference can be easily detected by latching the contents of frequency dividers 28 and 27 with the TDM clock using latch circuit 30.

The principle of signal interpolation in the interpolation circuit shown in FIG. 4 is that the real part signal for each channel from TMUX29,
Each of the imaginary part signals is passed through an FIR filter, and the combination of the shift register 50, latch circuit 53, multiplier 54, and adder 55 shown in the upper part of FIG. 4 constitutes the FIR filter for the real part signal. , shift register 50 and latch circuit 53 in the lower part of FIG.
The combination of the multiplier 54 and the adder 55 constitutes an FIR filter for the imaginary part signal. For simplicity, FIG. 4 shows a 3-tap FIR type filter, but in general, the number of taps may be increased.

In FIG. 4, the ROMs 51 and 52 are each
This is a ROM that stores tap coefficients for obtaining signal interpolation values at the rising timing and falling timing of the TDM clock.
Time difference between clock and TDM clock (T _d )
The information, that is, the tap coefficient is read using the output of the latch circuit 30 in FIG. 2 as an address, and the FIR
The type filter performs weighting using the read tap coefficients.

In this way, the real part and imaginary part FIR type filters respectively detect the interpolated value which should be the rising point of the TDM clock, and the interpolated value which should be the rising point of the TDM clock, and the interpolated value immediately after that, in the middle of the change of the signal, within the so-called zero crossing point. Calculate the interpolated value.

The state of signal interpolation is shown in Figure 5, in which the Δ mark indicates the data output from TMUX29,
In other words, ◯ indicates the FDM clock timing, ◯ indicates the TDM clock rise timing, and × indicates the TDM clock fall timing. As shown in FIG. 5, in order to correctly detect the clock phase error, it is necessary to know the direction of change in the signal, and this is detected by the method described below.

To explain the operation of the demodulation circuit with reference to FIG. 6, this demodulation circuit reproduces data based on the signal from the interpolation circuit, and also detects clock phase error (timing error). Multiplier 60, VCO 61, loop filter 62,
A closed loop circuit consisting of the carrier phase error detection section 63 constitutes a normal synchronous detection QPSK demodulation circuit,
Regenerate demodulated data.

Clock phase error detection is performed based on the phase error component from the carrier phase error detection section 63, and the exclusive OR gate 77 in the clock phase error detection section 64 generates the above-mentioned change point presence/absence signal. In the change point detection circuit 78, when there is no change point in the data, the output is set to 0, and when there is a change point, the polarity is corrected in the multiplier 65 according to the data, and the output is set to 0 in the LPF 79. The clock phase error is then sufficiently averaged and outputted from the adder 80.

FIG. 7 shows the frame structure of the signal at the output of the time multiplexing circuit 35 in FIG. 2, in which the modulation data and clock phase error data output from the demodulation circuits 34-1 to 34-N in FIG. Multiplexed. One frame consists of a UW (unique word) that indicates the start of the frame, an SF (super frame) bit that indicates the start of a super frame, a TE section that indicates the clock phase error, and N of CH1 to CHN.
It consists of a data section that multiplexes channel signals.
SF changes every fixed number of frames to indicate the start of a superframe, and time-multiplexes the transmission clock phase errors of each channel to the TE section in a predetermined order.

Each earth station demodulates and reproduces the received signal, reproduces the frame signal shown in FIG. 7, and establishes frame synchronization and super frame synchronization. This is earth station 1 in Figure 1.
This is performed in the reception baseband signal processing circuit 15 at 0. Each earth station selects the clock phase error information of the channel transmitted by the earth station, and uses this to control the phase of the transmit clock in the transmit clock generating circuit 16.

FIG. 8 shows another example of the satellite onboard circuit, and the second
In the circuit shown in the figure, the order of the time multiplexing circuit 35 and the demodulating circuits 34-1 to 34-N is changed. That is, the signals are first time multiplexed, and demodulation is performed by the multiplexing demodulation circuit 93. The operation of the multiplexing demodulation circuit 93 for each channel is similar to that of the individual demodulation circuit shown in FIG. 6, but the difference is that signal processing is performed on time-multiplexed multi-channel signals in a time-division manner. That is, the 1-bit delay memory 70 in FIG. 6 is replaced with a RAM, and addresses are switched for each channel to perform multiplexing demodulation.

The multiplexed DEM method shown in FIG. 8 requires less hardware, but requires high-speed operation. On the other hand, although the individual DEM method shown in FIG. 2 has large hardware as a whole, the operation of each demodulation circuit is slow, and it is easy to convert it into a VLSI using CMOS technology.

As explained above, in the present invention, the phase of the own station's transmitting clock is controlled based on the phase error data from the communication satellite.
-During TDM conversion, there is no interference between channels due to channel clock phase errors, and the all-digital circuit configuration provides high stability and
It is possible to downsize by using VLSI. Also,
Not only does the FDM/TDM conversion allow the transponder to operate at saturation point, but the common carrier clock allows the earth station to reproduce the signals of all channels with just one demodulator.

[Effect of the invention] The present invention provides the following effects.

(1) By performing signal regeneration on the satellite, uplink and downlink can be separated and BER characteristics can be improved.

(2) FDM/TDM conversion allows transponders to be used at maximum output, improving downlink C/N and enabling direct communication between small stations.

(3) Compared to conventional FDM/TDM conversion methods, the method of the present invention is an all-digital circuit, has high quality and reliability, and can be significantly miniaturized using VLSI technology.

(4) Since TMUX can easily realize narrowband channel division, it is especially suitable for systems for small stations.

(5) For the above reasons, the present invention can be widely applied to future small station communication systems.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an FDM/TDM conversion regenerative relay satellite communication system according to the present invention. FIG. 2 shows the circuit configuration (IF section) on the satellite of the present invention, FIG. 3 shows the digital section of the transformer multiplexer shown in FIG. 2, and FIG. 4 shows the digital section of the transformer multiplexer shown in FIG. 5 is a diagram for explaining the signal interpolation operation of the interpolation circuit shown in FIG. 4, and FIG. 6 is a diagram showing the configuration of the digital demodulation circuit shown in FIG. 2. shows. FIG. 7 shows a frame structure of a downlink signal according to the present invention, and FIG. 8 shows another example of the circuit structure on a satellite according to the present invention. Fig. 9 shows a conventional circuit, Fig. 10 is a diagram for explaining the principle of chirp Z conversion, Fig. 11 is a diagram for explaining the basic operation of chirp Z conversion, and Fig. 12 is a diagram for explaining the basic operation of chirp Z conversion. FIG. 13 is a diagram for explaining the difficult problems of the conversion method, and is a diagram for explaining FDM channel separation performed by the transmultiplexer method in the present invention. In the figure, 9 is a satellite, 10 is an earth station, 20 is a local oscillator, 22 and 23 are mixers, 24 and 25 are A/D converters with a sampler function, 26 is a clock source for TMUX, 32 is a multiplex clock source, 37 is a carrier oscillator.

Claims (1)

[Claims] 1. A means installed on a satellite for receiving and processing SCPC digitally modulated and FDM multiplexed signals from a plurality of earth stations; A transformer multiplexer type branching circuit (hereinafter referred to as TMUX) that performs FDM separation into the first to Nth output channels by detecting the phase difference between the FDM clock and the TDM clock, and based on the detected phase difference. Said
A signal interpolation value (hereinafter referred to as an identification signal) at the TDM clock timing is calculated for each output channel of the TMUX, and a signal interpolation value at the intermediate timing of the TDM clock (reverse phase TDM clock timing) is calculated. It has an interpolation circuit that calculates an interpolated value (hereinafter referred to as a zero-crossing signal), and a data regeneration circuit that performs data regeneration on the identification signal from the interpolation circuit and outputs it as demodulated data, and the demodulated data and a digital demodulator having a clock phase error detection circuit that detects the phase error of the transmission clock of the transmission signal of each earth station with respect to the TDM clock from the zero-crossing signal, averages the detected phase error, and outputs it as clock phase error data. circuit, and demodulated signals of each channel (demodulated data and clock phase error data) from the digital demodulation circuit.
The demodulated data is time-division multiplexed frame by frame at a time position determined by the channel, and the clock phase error data is time-division multiplexed at a predetermined time position every fixed number of frames (super frames) in an order determined by the channel. The common carrier wave on the satellite is modulated by the time division multiplexed signal from the time division multiplexed circuit and transmitted to the downlink, and each earth station regenerates the time division multiplexed signal. It establishes frame and super frame synchronization, and also reproduces the transmitting clock phase error data of its own station, and further controls the transmitting clock phase of its own station based on the transmitting clock phase error data, thereby controlling the round trip to the satellite. An FDM/TDM conversion and regeneration relay satellite communication system that performs FDM/TDM conversion and signal regeneration on a satellite by establishing clock synchronization in a loop containing the FDM/TDM conversion.