JPH0541836A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To obtain a signal whose horizontal line number is the same number as that with the case of employing a solid-state image pickup element capable of progress scanning in a color television camera employing a 3-board type solid-state image pickup element and to obtain a signal with less deterioration in the vertical resolution. CONSTITUTION:The device is provided with a 1st solid-state image pickup element 21, 2nd and 3rd solid-state image pickup elements 22, 23 arranged spatially by one line in the vertical direction with respect to the 1st solid-state image pickup element 21, and 1st, 2nd and 3rd summing averaging devices 32-34 arithmetically averaging output signals of the elements and signals resulting from delaying the output signals by one horizontal scanning period respectively to extract the output signal of the 1st-3rd solid-state image pickup elements 21-23 and the output signal of the 1st-3rd arithmetic averaging devices 32-34 thereby obtaining a signal of a horizontal line number equal to that with the case of using a progress scan solid-state image pickup element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device for obtaining a high quality video signal by using an ordinary solid-state image pickup device.

[0002]

2. Description of the Related Art In recent years, a solid-state image pickup device has been applied to a television camera for EDTV, and an image pickup device capable of progress scanning (60 Hz / 525/1: 1) has been demanded.

A conventional solid-state image pickup device will be described below. FIG. 5 is a block diagram of a conventional image pickup device using three solid-state image pickup devices capable of progress scanning, FIG. 6 is a configuration diagram of the solid-state image pickup device used in the solid-state image pickup device, and FIG. FIG. Figure 5
In the above, the solid-state image pickup devices 1, 2, 3 for green, red, and blue are arranged so as to match the subject image, and the drive circuit 4 for the solid-state image pickup device is the solid-state image pickup devices 1, 2, 3 is a drive circuit for driving the solid-state image pickup device, a pulse generation circuit 5 for solid-state image pickup device is a pulse generation circuit for generating pulses to be supplied to the solid-state image pickup devices 1, 2 and 3, and a correlation 2
The heavy sampling circuits (hereinafter abbreviated as CDS) 6, 7, and 8 are preamplifiers for removing low-frequency noise of the solid-state image pickup device. 6 and 7, a photoelectric conversion element 9 is a light receiving element for converting a subject image into an electric signal, and a vertical transfer section 10 is a vertical charge transfer section for receiving charges of the light receiving element and transferring them in the vertical direction, horizontal transfer. The unit 11 is the vertical transfer unit 1.
A horizontal charge transfer unit that receives charges transferred from 0 and horizontally transfers the charges, and an output circuit that the output amplifier 12 converts the charges transferred from the horizontal transfer unit 11 into a voltage and outputs the voltage.
The vertical transfer electrode 13 is composed of one set of four electrodes for one photoelectric conversion element 9, and is an electrode for forming a potential well for vertically transferring the charge. The vertical signal line 14 is the vertical line. It is a pulse supply line for supplying a voltage to the transfer electrode 13.

The operation of the solid-state image pickup device having the above components will be described below.

First, the solid-state image pickup device pulse generation circuit 5 generates drive pulse signals such as a vertical transfer signal and a horizontal transfer signal for progress scanning the solid-state image pickup devices 1, 2 and 3, and this pulse signal is used for solid-state image pickup. The red, green, and blue video signals are respectively obtained by adding them to the solid-state image pickup devices 1, 2, and 3 via the device drive circuit 4 to obtain the CDS.
Remove low-frequency noise with, and phase-matched red with less noise,
Outputs green and blue video signals. The solid-state image sensor and transfer will be described in more detail below. In the solid-state image pickup devices 1, 2, and 3, the photoelectric conversion device 9 accumulates charges according to the intensity of light, and transfers the charges to the vertical transfer unit 10 in the vertical scanning blanking period. The electrode 13 connected by the signal line 14 has a frequency of 90 degrees out of phase, that is, 2 of the horizontal frequency of the interlaced scan.
A pulse signal having a doubled frequency of 31.5 KHz is added, and signal charges are vertically transferred to the horizontal transfer unit 11 by so-called four-phase driving. The signal of the number of photoelectric conversion elements provided in the horizontal direction is further transferred to the output amplifier 12 during the period of 31.7 μs, and the output amplifier 1
In step 2, the electric charges for each photoelectric conversion element are converted into voltages, and signals for green, red, and blue are output from the solid-state image pickup elements 1, 2, and 3, and the progress scan (6
The video signal for 0 Hz / 525/1: 1) is obtained.

[0006]

However, in the above-mentioned conventional configuration, it is necessary to transfer and read out the signals of the number of photoelectric conversion elements 9 every 60 Hz in the progress scan, and therefore the interlaced scan (60 Hz /
In the solid-state image pickup device of 525/2: 1), the electrode 13 of the vertical transfer unit 10 has two electrodes corresponding to one photoelectric conversion element 9, whereas in the solid-state image pickup device for progress scan, the vertical electrode is vertical. It is necessary to arrange four electrodes corresponding to one photoelectric conversion element 9 in the electrode 13 of the transfer unit 10. For this reason, the area of one electrode must be reduced, so that fine processing in the semiconductor is required, and the area of each electrode 13 is reduced, so that the maximum transfer capacity of the vertical transfer unit 10 is reduced. In the horizontal transfer unit 11, the interlaced scan solid-state image pickup device transfers a signal of one line in a period of 63.4 μs, whereas the solid-state image sensor of half of the progress scan is 31.7 μs.
The signal of one line must be transferred during the period. Therefore, in the case of a solid-state imaging device having the same horizontal pixels, the frequency of the horizontal driving pulse of the progress scan is doubled compared with the interlaced scan, so that the transfer efficiency is deteriorated and the power is significantly increased. Had.

The present invention solves the above-mentioned problems of the prior art by using a solid-state image pickup device for interlaced scan which has been conventionally used and has little deterioration in frequency characteristics and a solid-state image pickup device for progress scan. Another object of the present invention is to provide a solid-state imaging device for obtaining signals of the same number of horizontal lines.

[0008]

To achieve this object, a solid-state image pickup device according to a first aspect of the present invention is provided with a first solid-state image pickup device and a space for one line in a direction perpendicular to the first solid-state image pickup device. The second and third solid-state image pickup elements that are arranged to be displaced from each other, and the first and the first solid-state image pickup elements that are driven by the same drive pulse.
A drive pulse generation circuit for generating drive pulses for the second and third solid-state image pickup devices, and a first pulse for delaying output signals of the first, second, and third solid-state image pickup devices by one horizontal scanning period, respectively. The second and third 1H delay lines, and the first, second and third
First, second, and third for obtaining an interpolation signal by averaging the output signal of the third solid-state image sensor and the corresponding first, second, and third 1H delay line output signals, respectively. And an output signal of the first, second, and third solid-state imaging devices and an interpolation signal of the first, second, and third addition and averaging circuits. ing.

A solid-state image pickup device according to the second aspect of the present invention includes first, second and third solid-state image pickup elements arranged so as to be spatially aligned with each other.
A drive pulse generation circuit for generating a pulse for driving the read timing of the second and third solid-state image pickup devices by 1 field with respect to the read-out timing of the first solid-state image pickup device; , The first, second, and third delaying the output signals of the third solid-state image sensor for one horizontal scanning period, respectively.
A third 1H delay line and the first, second, and third output signals corresponding to the output signals of the first, second, and third solid-state imaging devices, respectively.
A first, a second, and a third arithmetic mean circuit for arithmetically averaging a third 1H delay line output signal to obtain an interpolation signal, and the first, second, and third solid-state imaging devices Output signal and the interpolation signals of the first, second and third averaging circuits are output.

[0010]

According to the first aspect of the present invention, the interlaced scan is arranged in which the second and third solid-state image pickup devices are spatially offset by one line in the vertical direction with respect to the first solid-state image pickup device. The output signals of the first, second, and third solid-state imaging devices and the signals obtained by delaying the output signals by one horizontal period by the 1H delay line are added and averaged by the addition and averaging circuit to obtain the first, second, and third output signals. By obtaining the interpolation signal in the vertical direction of the third solid-state image sensor, the output signal obtained from the first solid-state image sensor spatially coincides with the second and third interpolation signals, and the second and third solid-state image sensors are obtained. The output signal obtained from the image sensor spatially coincides with the first interpolation signal. Therefore, the first
By using the output signals of the second and third solid-state image pickup devices and the corresponding first, second and third interpolation signals as output signals, it is possible to use a solid-state image device of interlaced scan. Regardless, it is possible to obtain a signal in which the number of horizontal lines in one filled period is equal to the number of horizontal lines in the progress scan.

According to the second aspect of the present invention, the first aspect of the present invention has the above-mentioned structure.
The interlace-scanned first driven by the drive pulse generation circuit for the solid-state image pickup device which drives the read timing of the second and third solid-state image pickup devices by shifting by 1 field from the read-out timing of the solid-state image pickup device Output signals of the second and third solid-state image pickup devices and signals obtained by delaying the output signals by one horizontal period by a 1H delay line are added and averaged by an addition and averaging circuit to obtain the first, second, and third solid-state image pickup devices. By obtaining the interpolation signal in the vertical direction of the element, the output signal obtained from the first solid-state image sensor spatially matches the second and third interpolation signals and is obtained from the second and third solid-state image sensors. The resulting output signal spatially coincides with the first interpolated signal.
Therefore, by using the output signals of the first, second, and third solid-state image pickup devices and the corresponding first, second, and third interpolation signals as output signals, the number of horizontal lines in one filled period A signal corresponding to the same number of horizontal lines as that of the progress scan can be obtained.

[0012]

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the solid-state image sensor 21 is spatially displaced from the solid-state image sensor 21 in the vertical direction by one line.
2, 23 are arranged, a solid-state image sensor drive circuit 24 for driving the solid-state image sensors 21, 22, 23 is provided, and a solid-state image sensor drive circuit 24 for driving the solid-state image sensors 21, 22, 23. A pulse to be supplied to the solid-state image pickup device is generated by the pulse generation circuit 25. Next, CDS 26,2
Reference numerals 7 and 28 are for removing low-frequency noise by performing correlated double sampling on the output signals from the solid-state imaging devices 21, 22, and 23, and the respective output signals are 1H extension lines 29, 30, and 31. It is extended by one horizontal period. Further, the output signals of the CDSs 26, 27 and 28 and the output signal of the 1H delay line are added and averaged by the averaging circuits 32 and 3 respectively.
3 and 34 add and average to obtain an interpolation signal, and the time compression circuits 35, 36, 37, 38, 39 and 40 use the CDS 26, 2
The output signals of 7 and 28 and the output signals of the averaging circuits 32, 33 and 34 are shortened to half each horizontal scanning, and the parallel-serial conversion path 41 of the time compression circuits 35 and 36. Parallel-to-serial conversion of the output signals is performed to obtain output signals having twice the number of horizontal scanning lines of the solid-state imaging device 21 obtained in one filled period. Similar to the parallel-serial converter 41, the parallel-serial converter 42 performs parallel-serial conversion on the output signals of the time compression circuits 37, 38 to obtain twice the horizontal of the solid-state image sensor 22 obtained within one filled period. The parallel-serial converter 43 is for obtaining an output signal having the number of scanning lines, and the parallel-serial converter 43 similarly performs parallel-serial conversion of the output signals of the time compression circuits 39, 40 to obtain the solid state within one filled period. It is composed of a parallel-serial converter for obtaining an output signal having twice the number of horizontal scanning lines as the image pickup device 23.

The operation of the solid-state image pickup device of the present embodiment having the above structure will be described below. As shown in FIG. 2, the solid-state image sensor 21 includes solid-state image sensors 22 and 2
3 are spatially offset by one line in the vertical direction, and are driven by the same drive signal for the solid-state imaging device. Therefore, the waveforms shown in the waveform diagram of FIG. 3 from the CDSs 26, 27, 28. a, a ', a "are obtained, provided that FIG.
Numerical values 2n, ..., 2 (n + 1), 2 (n +)
2), 2 (n + 3), 2n + 1,2 (n + 1) +1,2
(N + 2) +1, (n + 3) +1 and the like indicate spatial horizontal line numbers with the solid-state image sensor 21 as a reference. In addition, the horizontal line numbers in the waveforms a, a ′, and a ″ increase by 2 for interline reading. The solid-state image pickup devices 21 and 23 are spatially perpendicular to the solid-state image pickup device 21. Since it is shifted by one line in the direction, the timing of the output signals of the CDSs 27 and 28 is shifted by one line with respect to the CDS 26. Next, CDS2
The output signals of 6, 27 and 28 become signals of waveforms b, b ', b "as shown in FIG. 3 by 1H delay lines 29, 30 and 31 for delaying one horizontal scanning period, respectively, and further 1H.
The delay lines 29, 30, 31 output signals and the CDS output signals are added and averaged by addition and averaging circuits 32, 33 and 34, that is, the waveforms a and b, a'and b ', a "and b" are added and averaged. The interpolated signals having the waveforms c, c ′ and c ″ shown in FIG. The output signals of the CDSs 26, 27, 28, that is, the waveforms a, a ', a "and the averaging circuit 3
2, 33, 34 output signals, that is, waveforms c, c ', c "
Are time compression circuits 35, 37, 39, 36, 3 respectively.
8 and 40, the signal parts are time-compressed to ½ for each horizontal scanning to obtain waveforms d, d ′,
d ″, e, e ′, e ″ are obtained, and then, in the parallel-serial converter 41, the signal part of the waveform e is in the first half of one horizontal period, and the signal part of the waveform d is in the second half of one horizontal period. The output signal f is obtained by arranging the signal parts at equal intervals and by arranging the signal parts at equally spaced times. Similarly, in the parallel-serial converters 42 and 43, output signals f'and f "
And the output signal f of the parallel-to-serial converter 41 is further halved in the horizontal scanning period by the ½H delay circuit 44.
By delaying, it is possible to obtain the output signal g that spatially coincides with the output signals f ′ and f ″ in the vertical direction and also coincides in timing.

As a result, the number of horizontal lines obtained in one field is the same as the number of horizontal lines obtained by using the solid-state image sensor of the interlaced scan, that is, the number of lines of the interlaced scan, although the solid-state image sensor of the interlaced scan is used. The number of output signals is twice as many as that of When the output signal g is a signal obtained from the solid-state image sensor, the output signals f ′ and f ″ are interpolation signals, while when the output signal g is an interpolation signal, the output signals f ′ and f ′,
Since f ″ is a signal obtained from the solid-state image sensor,
The vertical resolution of the interpolation signal obtained by adding the lines is lower than the resolution of the signal obtained from the solid-state image sensor, but at least one of the three output signals g, f ′, and f ″ is solid-state image pickup. A signal obtained from the element is included, and even when, for example, three signals are mixed to form a luminance signal, deterioration in resolution of the luminance signal can be prevented.

As described above, according to this embodiment, the solid-state image pickup device 21 is spatially vertically displaced with respect to the solid-state image pickup devices 22, 23, and the output signals of the solid-state image pickup devices 21, 22, 23 and one horizontal direction. The number of horizontal lines of the signal obtained in one filled period is the progress scan, even though the interlaced scan solid-state image sensor is used by obtaining the interpolated signal by adding and averaging the signals delayed for the scanning period. The same number of horizontal line signals as those obtained by using the solid-state image pickup device are obtained, and at least one of the output signals of the solid-state image pickup device is the same as the output signal. Can be suppressed to a small degree.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 4, the solid-state imaging devices 21, 22, 23 and the CDSs 26, 2
7, 28 and 1H delay lines 29, 30, 31; averaging circuits 32, 33, 34; time compression circuits 35, 36, 3
7, 38, 39, 40 and parallel-serial converter 4
1, 42 and 43 have the same configuration as that of FIG.
The difference from FIG. 1 is that the solid-state imaging device 21 and the solid-state imaging device 2 are different.
2 and 23 are arranged so as to be spatially aligned in the vertical direction, and drive the solid-state image pickup device 21 to drive the solid-state image pickup device 21.
And a solid-state image sensor drive circuit 51 for driving the solid-state image sensors 22 and 23 are separately provided to generate a pulse for driving the solid-state image sensor 21 by shifting the read mode of the solid-state image sensors 22 and 23 by 1 field. Solid-state image sensor pulse generation circuit 52 and parallel-serial converters 41, 4
In the case of odd-numbered fields, the output signals of the 1/2 delay circuit 53 and the parallel-serial conversion are used for delaying the output signals of 2, 43 by 1/2 respectively. And output signals of the parallel-to-serial converter 41 and the output signals of the half delay lines 54 and 55 in the case of an even field. , 57 and 58 are provided.

The operation of the solid-state image pickup device configured as described above will be described below. When the solid-state imaging device 21 reads odd fields, the solid-state imaging devices 22 and 23
Is an even field read, and when the solid-state image sensor 21 is an even field read, a pulse is generated in the solid-state image sensor pulse generation circuit 52 such that the solid-state image sensors 22 and 23 are odd field read. By driving the solid-state image pickup device 21 by the image pickup device drive circuit 50 and driving the solid-state image pickup devices 22 and 23 by the solid-state image pickup device drive circuit 51, the waveforms a, a ′ of FIG.
The signal indicated by a ″ can be obtained from the solid-state imaging devices 21, 22, and 23, the selection circuit 56 selects the signal that has passed through the half H delay line 53, and the selection circuits 57 and 58 select the parallel-serial converter. By selecting the output signals of 42 and 43, the selection circuits 46, 47 and 4 are selected similarly to the first embodiment.
3, the output signals g, f ', f "shown in Fig. 3 are obtained. In the even field, the solid-state image pickup device 21 outputs the output signal a'or a", and the solid-state image pickup devices 22, 23.
Since the signal of the line corresponding to the output signal a is obtained from the output signal from the output signal, the selection circuit 56 selects the output signal of the parallel-serial converter 41, and the selection circuits 57 and 58 select the output signals of the 1 / 2H delay lines 54 and 55. The output signal f'is obtained from the selection circuit 56 and the signal having the line number shown in the output signal g is obtained from the selection circuits 57 and 58, and the same result as that of the first embodiment is obtained.

As described above, according to the second embodiment, the solid-state image pickup device 21 is driven by being shifted by 1 field with respect to the solid-state image pickup devices 22 and 23, and the output signals of the solid-state image pickup devices 21, 22 and 23 are set to 1 and 1. The number of horizontal lines obtained in one filled period is the same as that of the progress scan in spite of using the interlaced scan solid-state image pickup device by obtaining the interpolated signal by each addition average with the signal delayed in the horizontal scan period. A signal having the same number of horizontal lines as that obtained by using the solid-state image sensor is obtained, and at least one of the signals is the same as the output signal of the solid-state image sensor. Deterioration can be suppressed to a low level.

Although the time compression circuits 35 and 36 and the parallel-serial converter 41 are separately provided in the first embodiment, they can be realized by one circuit using a memory capable of writing and reading independently. Time compression circuit 3
It is obvious that the memories 7, 38 and the parallel-serial converter 42 and the time compression circuits 39, 40 and the parallel-serial converter 43 can also be realized by the memory. See also FIG.
As shown in FIG.
It is obvious that the same effect can be obtained in the reading by the so-called photodiode mix mode, in which the photoelectric conversion elements of the horizontal line are added in the vertical transfer section, and the addition is read by changing the combination for each field. ..

[0021]

As described above, according to the first aspect of the present invention, the first solid-state image pickup device and the second and the third solid-state image pickup devices are arranged so as to be spatially offset by one line in the vertical direction. And a drive pulse generation circuit for generating drive pulses for the first, second, and third solid-state image pickup elements driven by the same drive pulse, and the first, second, and third
The first, second, and third 1H delay lines that delay the output signal of the third solid-state image sensor by one horizontal scanning period, and the output signals of the first, second, and third solid-state image sensors, respectively. The first, second, and third 1H delay line output signals, respectively, are added and averaged to obtain an interpolation signal, and first, second, and third arithmetic mean circuits are provided. By using the output signals of the second and third solid-state image pickup devices and the interpolation signals of the first, second and third addition and averaging circuits as outputs, it is possible to use the interlaced scan solid-state image pickup devices. The number of horizontal lines obtained in one filled period is the same as the number of horizontal lines obtained by using the progressive scan solid-state image sensor, and at least one of the signals is the same as the output signal of the solid-state image sensor. As the output signal It can be suppressed to reduce the resolution degradation when making the luminance signal in order.

The solid-state image pickup device according to the second aspect of the present invention includes first, second and third solid-state image pickup elements spatially aligned with each other.
A drive pulse generation circuit for generating a pulse for driving the read timings of the second and third solid-state image pickup devices by shifting the read-out timings of the first and second solid-state image pickup devices by one field from each other; 2, first and third delaying the output signals of the third solid-state image sensor for one horizontal scanning period
The first and second corresponding 1H delay lines and the first and first output signals corresponding to the output signals of the first, second and third solid-state imaging devices, respectively.
A first, a second, and a third arithmetic mean circuit for arithmetically averaging the second and third 1H delay line output signals to obtain an interpolated signal, respectively. By outputting the output signal of the solid-state image pickup device and the interpolation signal of the first, second, and third averaging circuits, the same effect as that of the first invention can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a solid-state imaging device according to a first embodiment of the present invention.

FIG. 2 is a spatial layout diagram of the solid-state image sensor.

FIG. 3 is a waveform diagram of each part of the block diagrams of the first and second embodiments.

FIG. 4 is a block diagram of a solid-state imaging device according to the second embodiment.

FIG. 5 is a block diagram of a conventional solid-state imaging device.

FIG. 6 is a configuration diagram of a solid-state image sensor used in a conventional example.

FIG. 7 is a partially enlarged view of the solid-state image sensor.

[Explanation of symbols]

 21,22,23 Solid-state imaging device 24,50,51 Solid-state imaging device drive circuit 25,52 Solid-state imaging device pulse generation circuit 29,30,31 1H delay line 32,33,34 Addition / averaging circuit 35,36,37 , 38, 39, 40 Time compression circuit 41, 42, 43 Parallel-serial converter 44, 53, 54, 55 Half delay line 56, 57, 58 Selection circuit

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 9/07 A 8943-5C

Claims (4)

[Claims] 1. The same drive pulse as that of the first solid-state image sensor and the second and third solid-state image sensors spatially displaced by one line in the vertical direction with respect to the first solid-state image sensor. And a drive pulse generation circuit for generating drive pulses for the first, second, and third solid-state image pickup elements driven by, and output signals of the first, second, and third solid-state image pickup elements, respectively. The first, second, and third 1H delay lines for delaying the horizontal scanning period, and the first, second, and third output signals of the first, second, and third solid-state image pickup devices corresponding to the respective output signals. A first, a second, and a third averaging circuit for respectively averaging the 1H delay line output signal, and the output signals of the first, second, and third solid-state image pickup devices and the first and second
A solid-state imaging device that outputs the output signals of the second and third adders. 2. The same drive pulse as that of the first solid-state image pickup device and the second and third solid-state image pickup devices spatially displaced by one line in the vertical direction with respect to the first solid-state image pickup device. And a drive pulse generation circuit for generating drive pulses for the first, second, and third solid-state image pickup elements driven by, and output signals of the first, second, and third solid-state image pickup elements, respectively. The first, second, and third 1H delay lines for delaying the horizontal scanning period, and the first, second, and third output signals of the first, second, and third solid-state image pickup devices corresponding to the respective output signals. First, second, and third arithmetic and averaging circuits for respectively averaging the 1H delay line output signals, output signals of the first, second, and third solid-state imaging devices and the first and second ，
First, second, third, fourth, fifth and sixth time compression circuits for time-compressing the video signal portion with the output signal of the third arithmetic mean circuit to each half for each horizontal scanning. And for each horizontal scanning period, the first, fourth, second, fifth, third, and sixth time compression circuit output signals are converted from parallel to serial, and the first, second, and third solid-state signals are converted. 2 for image sensor
A parallel-serial converter for obtaining an output signal having twice the number of horizontal scanning lines; and a half-delay line for delaying the first parallel-serial converter by a half of the horizontal scanning period. Solid-state imaging device. 3. A first, a second, and a third solid-state image pickup device which are spatially aligned and arranged, and a second and a third solid-state image pickup device with respect to a read timing of the first solid-state image pickup device. The drive pulse generating circuit for generating a pulse for driving the read timing of 1 is shifted by 1 field, and the output signals of the first, second and third solid-state image pickup devices are set to 1 respectively.
The first, second, and third 1H delay lines for delaying the horizontal scanning period, and the first, second, and third output signals of the first, second, and third solid-state image pickup devices corresponding to the respective output signals. 1st output for averaging the 1H delay line output signal and output signal 2 respectively
A solid-state imaging device comprising a third arithmetic mean circuit and outputting the output signals of the first, second, and third solid-state imaging devices and the output signals of the first, second, and third arithmetic mean circuits. 4. A first, a second, and a third solid-state image pickup device which are spatially aligned and arranged, and a second and a third solid-state image pickup device with respect to a read timing of the first solid-state image pickup device. The drive pulse generating circuit for generating a pulse for driving the read timing of 1 is shifted by 1 field, and the output signals of the first, second and third solid-state image pickup devices are set to 1 respectively.
The first, second, and third 1H delay lines for delaying the horizontal scanning period, and the first, second, and third output signals of the first, second, and third solid-state image pickup devices corresponding to the respective output signals. 1st, 2nd and 2nd for respectively averaging the 1H delay line output signal and
Each of the video signals of the third arithmetic mean circuit, the output signals of the first, second, and third solid-state image pickup devices and the output signals of the first, second, and third arithmetic mean circuits is horizontally arranged. 1st, 2nd, 3rd, 4th, time-compressed by half for each scan
The fifth and sixth time compression circuits and the first, fourth, second, fifth, third and sixth time compression circuit output signals are respectively parallel-serial exchanged within one horizontal scanning period. A parallel-serial converter for obtaining an output signal having twice the number of horizontal scanning lines corresponding to the first, second, and third solid-state imaging devices and the first, second, and third parallels for each field. A solid-state imaging device comprising: a half delay line for alternately delaying an output signal of a serial converter by a half horizontal scanning period.