JPH0541453A - Semiconductor integrated circuit and layout method thereof - Google Patents

Abstract

PURPOSE:To make it possible to test only a matrix system-testable circuit block based on a matrix system out of circuit blocks which can not be tested based on a ricks test system without adversely affecting the circuit blocks. CONSTITUTION:There are laid out test circuits having sense circuits 7a, 7b and drive circuit 6a and 6b along two sides where circuit blocks adjoin so that sense lines 4a, 4b and probe lines 3a and 3b connected with nodes out of circuit blocks 9a and 9b to be matrix-tested may not pass on a block 10 for which no matrix test is carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a layout method thereof, and in particular, a first circuit block which can be tested by a matrix test method and a second circuit block which cannot be tested by a matrix test method are mixed. The present invention relates to a semiconductor integrated circuit and a layout method thereof.

In recent years, the functions of electronic devices have become increasingly sophisticated,
The semiconductor integrated circuit has become complicated, and accordingly, the scale of the semiconductor integrated circuit has increased and the function has become complicated. Therefore, in such a semiconductor integrated circuit, almost all the internal gates are not connected to the external pins, and the test of the operating state of these internal gates is important for improving the reliability of the semiconductor integrated circuit.

Therefore, the applicant of the present invention previously disclosed in Japanese Patent Laid-Open No. 61-42.
In Japanese Patent Publication No. 934, a semiconductor integrated circuit having a test circuit by a matrix test method suitable for a gate array device or a standard cell array device is proposed. However, not all types of circuit blocks can be tested by the matrix test method, and some circuit blocks cannot be tested by this matrix test method. Therefore, in a semiconductor integrated circuit in which these two circuit blocks coexist, it is important how to arrange the circuit blocks that can be tested by the matrix test method on the chip.

[0004]

2. Description of the Related Art FIG. 13 is a block diagram showing an example of a semiconductor integrated circuit having a test circuit based on a matrix test method.
In the figure, input / output regions (I / O) 2a, 2b, 2c, 2d are provided in the periphery of the chip 1 of the semiconductor integrated circuit, and a plurality of gates (cells) are arranged in a matrix on the chip 1. Arranged and interconnected appropriately according to the logic design to form a logic circuit or the like.

On the chip having the above structure, the probe lines 3 are arranged at regular intervals along the row direction of the gate.
In addition, sense lines 4 are arranged at regular intervals along the column direction of the gates, and switching field effect transistors 5, for example, are arranged at the intersections of the probe lines 3 and the sense lines 4. The gate electrode of the transistor 5 is connected to the probe line, and the output terminal of the desired gate is connected to the sense line 4 via the transistor 5.
It is connected to the.

Further, the probe line 3 is provided on the left side of the chip.
Probe line driver circuits 6 for sequentially selecting the sensor lines 4 are formed, and a sense circuit 7 for selecting each of the sense lines 4 is provided on the lower side of the chip. Further, a test control circuit 8 for supplying a clock to the probe line driver circuit 6 and the sense circuit 7 and for extracting a monitor output is provided in the corner of the chip 1.

In the conventional semiconductor integrated circuit having such a configuration, at the time of testing, each time the probe line driver circuit 6 receives a clock from the test control circuit 8, the probe line 3 is selected one by one, for example, from top to bottom. To go. When one probe line is selected, all the transistors 5 connected to it are turned on, and the output of the gate connected to that transistor is read out to the sense line 4.

On the other hand, the sense circuit 7 has all the sense lines 4 within the period in which one of the probe lines 3 is selected by the clock from the test control circuit 8.
Are sequentially selected one by one, and the potential (data) from each sense line 4 sequentially obtained by this is supplied to the test control circuit 8. As a result, the test control circuit 8 sequentially outputs the data from each sense line 4 by monitoring.

Thereafter, the same operation as described above is repeated.
In addition, the sense lines 4 are sequentially selected one by one, and all the probe lines 3 are selected within one sense line selection period.
The output data of each gate can be tested in the same manner by sequentially selecting one by one.

According to such a matrix test method, unlike the conventional scan method, it is possible to perform a test not for each flip-flop but for each gate, and for observing an arbitrary gate output in a chip. Not only can it be applied to defect adjustment, but it can also test the operating status of in-chip gates.

[0011]

However, the circuit block which can be tested by the above matrix test method can be applied to a circuit block in which the probe lines 3 and the sense lines 4 can be arranged in a matrix like a gate cell array. , Random access memory (RAM), read-only memory (ROM), and other circuit blocks that require a particularly high degree of integration, and central processing unit (CPU) and the like. Circuit blocks are generally called macrocells), and their layout is often completed as a general-purpose library, and they are reused for many semiconductor devices. It is extremely difficult to arrange probe lines and sense lines for the method It is difficult.

In recent years, however, since semiconductor integrated circuits have been highly functionalized, as shown in FIG. 14, a testable circuit block 9 (this is called a matrix test block) by the matrix test method is provided on the same chip. A semiconductor integrated circuit in which a circuit block (which is called a matrix non-testable block) 10 which is difficult to test by applying the matrix test method such as the RAM, ROM, and CPU is arranged is considered.

In such a semiconductor integrated circuit, since the probe line and the sense line cannot pass through the matrix test non-blocking block 10, the matrix test block 9 of this semiconductor integrated circuit can also be tested by the matrix test method. There wasn't.

Although it is possible to rearrange the circuit block 10 in which the matrix test method cannot be applied so that the matrix test method can be applied, it takes enormous time and cost, and even if the relayout is performed, it is more than the conventional one. However, since the extra area is consumed, the area of the entire chip increases, which further increases the cost. Further, since the area increases, the wiring length becomes longer and the speed cannot be reduced, which is not realistic.

The present invention has been made in view of the above points,
An object of the present invention is to provide a semiconductor integrated circuit and a layout method thereof in which only testable circuit blocks by the matrix test method can be tested by the matrix test method without affecting the circuit blocks that cannot be tested by the matrix test method. To do.

[0016]

As shown in FIG. 1, the present invention relates to an integrated circuit chip 1; a plurality of circuit blocks 9a and 9b formed together with a block 10 on which the matrix test is not performed, and circuit blocks. Corresponds to a plurality of circuit nodes 100 (corresponding to the output terminal of the cell 11), a plurality of sense lines 4a and 4b connected to the respective circuit nodes via the switch 12, and arranged so as to intersect the sense lines. And a plurality of probe lines 3a and 3b for controlling the switches, respectively, which are provided for the circuit block so that the sense line and the probe line do not pass over the block where the matrix test is not performed. And test circuits 6a, 6b, 7a, 7b arranged along two adjacent sides; the test circuit outputs the signal of the sense line. Sense circuit 7a to sense the 択的,
7b and drive circuits 6a and 6b for selectively driving the probe line.

[0017]

Since the test circuits are arranged along the two sides of the circuit block so that the sense line and the probe line do not pass over the block on which the matrix test is not performed, even if the blocks on which the matrix test is not performed are mixed. , It is possible to test the circuit block that performs the matrix test by the matrix test method.

[0018]

FIG. 11 is a diagram showing an arrangement according to the first embodiment of the present invention. The same components as those in FIGS. 13 and 14 described above are designated by the same reference numerals. Two matrix test blocks 9a and 9b and one matrix test non-block 10 are arranged on the semiconductor chip 1. The matrix test blocks 9a and 9b are obtained by dividing the matrix test block 9 shown in FIG. 14 so that each block has a rectangular shape.

A probe line driver 6a and a sense circuit 7a for testing the matrix test block 9a.
Are arranged along each edge of the matrix test block 9a. The test control circuit 8a is provided near the probe line driver 6a and the sense circuit 7a. A plurality of probe lines 3a extending from the probe line driver 6a extend in the row direction. The probe line driver 6a is close to the I / O area 2c. A plurality of sense lines 4a extending from the sense circuit 7a
Extends in the row direction. The sense circuit 7a is close to the I / O area. Similarly, a probe line driver 6b for testing the matrix test block 9b and a sense circuit 7b are arranged along each edge of the matrix test block 9b. The probe line driver 6b is close to the matrix test-disabled block 10. The test control circuit 8b is provided near the probe line driver 6b and the sense circuit 7b. The test control circuit 8b is close to the matrix test block 9a. A plurality of probe lines 3b extending from the probe line driver 6b extend in the row direction. A plurality of sense lines 4b extending from the sense circuit 7b extend in the column direction. With the above configuration, all cells in the matrix test blocks 9a and 9b can be tested by the matrix test.

FIG. 2 is a flow chart of a procedure for determining a layout on a chip including a matrix test block and a matrix test non-blocking block. First, it is determined whether or not the matrix test block and the matrix test non-block are mixed (step 101). Since the layout arrangement shown in FIG. 4 is taken as an example here, the determination result that they are mixed is obtained.

Next, it is determined whether the matrix test block is rectangular (step 102). Since the matrix test block 9 is not rectangular in the example shown in FIG. 4, in this case, the process proceeds to step 103 in FIG. 2 to divide the matrix test circuit block into all rectangular circuit blocks, and then to step 104, A probe line driver circuit, a sense circuit, a control circuit, a sense line, and a probe line are arranged and formed for each divided circuit block.

By the layout method described above, as shown in FIG. 1, the matrix test circuit block 9 is divided into rectangular circuit blocks 9a and 9b, and the probe lines are provided on the left side and the lower side of the divided matrix test circuit block 9a. The driver circuit 6a and the sense circuit 7a are formed, respectively, and the test control circuit 8a is formed, and although not shown, the probe line driver circuit 6a is formed.
A plurality of probe lines selected by only the plurality of sense lines and a plurality of sense lines selected only by the sense circuit 7a are orthogonal to each other, and the matrix test method capable block 9a is provided.
Wired on. Similarly, a dedicated probe line driver circuit 6b, a sense circuit 7b, and a test control circuit 8 are also provided for the divided matrix test block 9b.
b, and a sense line and a probe line not shown are arranged and formed, respectively.

With such a layout arrangement, the probe line and the sense line can be wired only at a position avoiding the matrix test method non-circuit block 10. Therefore, according to the present embodiment, the circuit block 10 that is difficult to test by the matrix test method is not affected at all,
Circuit block 9a that can be tested by the matrix test method,
Only 9b can be tested by the matrix test method.

In FIG. 1, the matrix testable circuit block is divided in the row direction, but it goes without saying that it may be divided in the column direction.

FIG. 3 shows a read system provided in the matrix test block 9a shown in FIG. The matrix test block 9a has a plurality of cells 11 arranged in a matrix. Each cell 11 is connected to the sense line 4a connected to the sense circuit 7a via the corresponding switching transistor 12. Each transistor 1
2 is an N-channel field effect transistor such as a MOS transistor. The gate of each transistor is
It is connected to the corresponding probe line 3a extending from the probe line driver 6a. The matrix test block 9b is also configured similarly to the matrix test block 9a.

FIG. 4 shows the matrix test block 9b, the probe line driver 6b, and the sense circuit 7 shown in FIG.
FIG. 6 is a block diagram showing in detail b and the test control circuit 8b. Pad 12 connected to the input side of cell 11
Are arranged in a line in the I / O area 2b. Cell 11
The pads 13 connected to the output side of are arranged in a line in the I / O area 2a. A plurality of cells 11, transistors 12, probe lines 3b and sense lines 4b are provided in the matrix test block 9b. The probe line driver 6b includes a row selection counter 6b-1 and a row selection decoder 6b-2. The sense circuit 7b is composed of a cyst register or a combination of a cyst register and a data compression circuit. The data read via the sense line 4b is output to the I / O pad 15 provided in the I / O area 2a. The test control circuit 8b receives a clock signal, a control signal and a data signal via the I / O pad 14 in the I / O area 2a. Then, the test control circuit 8b uses the row selection counter 6b-1.
And a clock signal to the sense circuit 7b.

In FIG. 5, the test control circuit 8
Data signals supplied to the row selection counter 6b-1 via b are load data D0, D1, D2 ... Row selection counter 6b-via test control circuit 8b
The control signals supplied to 1 include a clear signal, a clock signal, an enable signal, and a load signal. The load data D0, D1, D2, ... Are synchronized with the load signal and the row selection counter 6b while the enable signal is being supplied.
Loaded to -1. The row selection counter 6b-1 starts counting operation in synchronization with the clock signal, and output lines A0, A1, A2, connected to the row selection decoder 6b-2.
Activate one by one. Row selection decoder 6b-
2 is composed of a NAND gate 28 and an inverter 29.
The row selection counter 6b-1 is cleared in response to the clear signal.

FIG. 6 is a circuit diagram showing details of the sense circuit 7b. The sense circuit 7b is a multiplexer (MUX) 3
1 and a flip-flop (FF) 32. The clock signal from the test control circuit 8 is input to the flip-flop 32. Each multiplexer (selector)
31 selects either the data from the previous flip-flop 32 or the data read via the corresponding sense line 4b. The data output from the final stage flip-flop 32 is output to the I / O pad 15.

FIG. 7 is a diagram showing a modification of the first embodiment of the present invention. In FIG. 7, the same components as those shown in the figure are designated by the same reference numerals. The arrangement of FIG. 7 is shown in FIG.
In place of the probe line driver 6b, the sense circuit 7b and the test control circuit 8b, a probe line driver 6c, a sense circuit 7c and a test control circuit 8c are provided. Probe line driver 6c
Are arranged along the I / O region 2a, and the sense circuits 7c are arranged along the I / O region 2b. The test control circuit 8c is provided near the probe line driver 6c and the sense circuit 7c. The test control circuit 8c is located near the chip corner. The position of the test control circuit 8c is different from that of the configuration of FIG. 3 in the test control circuit 8c and the I / O pad 1.
4 (FIG. 4), the length of the connecting wiring can be shortened.

FIG. 8 is a diagram showing an arrangement according to the second embodiment of the present invention. As shown in the figure, three matrix test blocks 49a, 49b, 49c and four matrix non-testable blocks 40a, 40b, 40c, 40d.
Is provided. No matrix test block 40
a and 40b are a RAM area and a CPU area, respectively, and matrix non-testable blocks 40c and 40d are ROM areas, respectively. Probe line driver 4
6a, 46b and 46c are provided along the left side of the matrix test blocks 49a, 49b and 49c, respectively, and the sense circuits 47a, 47b and 47c are respectively provided with the matrix test blocks 49a, 49b and 4c.
It is provided along the lower side of 9c. The test control circuits 48a, 48b and 48c are provided in the lower left corners of the matrix test blocks 49a, 49b and 49c, respectively.

FIG. 9 is a diagram showing an arrangement according to the third embodiment of the present invention. The chip 1 shown in FIG. 9 includes a matrix test block 5a and two matrix test non-blocks 5a.
It has 0a (CPU) and 50b (RAM) and a logic block 51. The logic block 51 has a plurality of cells, as shown in FIG. However, it is not necessary to test these cells. This is because the logic block 51 has a small number of cells or a pattern which has already been designed and confirmed to operate. Therefore, the logic block 5 is handled in the same manner as the CPU area 50a and the RAM area 50b and is recognized as a matrix test non-blockable block. That is, the test circuit is not provided in the logic block 51. The probe line driver 56, the sense circuit 57, and the test control circuit 58 are provided in the matrix test block 59.

FIG. 10 shows a modification of the arrangement shown in FIG. Figure 1
Matrix test block 66 with two chips 0
a, 69b, and two non-matrix testable blocks 60a (CPU) and 60b (RAM).

The probe line driver 69a, the sense circuit 67a, and the test control circuit 68b are provided in the matrix test block 69a. Similarly, the probe line driver 66b and the sense circuit 67b
And a test control circuit 68b are provided in the matrix test block 69b. A test control circuit 68a adjacent to the probe line driver 66a and the sense circuit 67a is provided at the chip corner. Therefore, the length of the connection wiring between the test control circuit 68a and the corresponding I / O pad can be shortened. This means that the test control circuit 68b
Can also be said.

FIG. 11 is a diagram showing an arrangement according to the fourth embodiment of the present invention. The chip 1 of FIG. 11 has a non-rectangular matrix test block 7a and four matrix test non-permissible blocks 70a (ROM), 70b (CPU), 70c.
(RAM) and 70d (ROM). The fourth embodiment does not follow the procedure of FIG. The sense circuit 77 is located along the I / O area 2d. One end of the sense circuit 77 is close to the ROM area 70a, and the other end is close to the test control circuit 78.

The probe line driver for matrix test block 7a has two sub-blocks 76a and 7a.
It consists of 6b. The sub block 76a is provided between the I / O area 2c and the lower left edge of the matrix test block 7a, and the other sub block 76b is the ROM area 70.
It is provided between d and the upper left edge. Similar to FIG. 5, the enable signal (decode signal) from the row selection counter in the sub block 76a passes through the area 75 and is supplied to the sub block 76b.

The probe lines 73a and 73b extend from the sub-block 76b of the probe line driver, and the probe lines 73c and 73d extend to the sub-block 7.
It extends from 6a. The probe line 73a extends to the left end of the RAM area, and the probe line 73b extends CP.
It extends to the left end of the U area 70b. Similarly, the probe line 73c extends to the left end of the CPU area 70b, and the probe line 73d extends to the left end of the ROM area 70a. The sense lines 74a, 74b, 74c and 74d extend to the sense circuit 77. The sense line 74a extends to the lower end of the CPU area 70b, and the sense line 74b extends to the lower end of the RAM area 70c. The sense line 74c extends to the boundary between the matrix test block 7a and the I / O area 2b. The sense line 74d extends to the lower end of the enable signal passing region 75. The sense circuit 77 may be divided into two or more sub-blocks instead of or together with the probe line driver. FIG. 12 is a diagram showing an arrangement in which the RAM 10a is provided in a part of the rectangular matrix test block 9c.

[0037]

As described above, according to the present invention, it is possible to prevent both the probe line and the sense line from passing over the matrix test non-blocking block, so that the necessary circuit can be obtained without affecting the matrix test non-blocking block. Only the blocks can be tested using the matrix test method, the degree of freedom in chip design is increased, and the matrix test method can be applied to a semiconductor integrated circuit with a minimum area.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a procedure for determining a layout according to the present invention.

3 is a diagram showing a read system provided in a matrix test block 9a in FIG.

FIG. 4 is a block diagram showing details of a matrix test block 9b and its peripheral circuits in FIG.

FIG. 5 is a diagram showing details of a row selection counter and a row selection decoder.

FIG. 6 is a diagram showing details of a sense circuit 7b.

FIG. 7 is a diagram showing a modification of the first embodiment of the present invention.

FIG. 8 is a diagram showing a second embodiment of the present invention.

FIG. 9 is a diagram showing a third embodiment of the present invention.

FIG. 10 is a diagram showing a modification of the second embodiment of the present invention.

FIG. 11 is a diagram showing a fourth embodiment of the present invention.

FIG. 12 is a diagram showing an array when matrix test blocks are not rectangular.

FIG. 13 is a diagram showing a configuration example of a conventional semiconductor integrated circuit having a test circuit based on a matrix test method.

FIG. 14 is a diagram showing an example of an array in which matrix test blocks and matrix test non-blocks are mixed.

[Explanation of symbols]

9a, 9b, 49a, 49b, 49c, 59, 69a,
69b, 79 1st circuit block (matrix test block) 10, 40a, 40b, 40c, 50a, 50b, 5
1, 60a, 60b, 70a, 70b, 70c, 70d
Second circuit block (block not capable of matrix test) 6a, 6b, 6c, 46a, 46b, 46c, 56, 6
6a, 66b, 76a, 76b Probe line driver 7a, 7b, 7c, 47a, 47b, 47c, 57,
67a, 67b, 77 sense circuits 8a, 8b, 8c, 48a, 48b, 48c, 58, 6
8a, 68b, 78 test control circuit

Claims (9)

[Claims] 1. An integrated circuit chip (1); a circuit block (9a, 9b) formed together with a block (10) for which a matrix test is not performed on the integrated circuit chip, the circuit block including a plurality of circuit nodes (100). , A plurality of sense lines (4a, 4b) connected to each circuit node via a switch (12), and a plurality of probe lines (3a) arranged to intersect the sense lines and controlling the corresponding switches, respectively. , 3b); provided for the circuit block and arranged along two adjacent sides of the circuit block so that the sense line and the probe line do not pass over the block not subjected to the matrix test. A test circuit (6a, 6b, 7a, 7b); the test circuit selectively senses a signal of the sense line. 7b) and a drive circuit (6a, 6b) for selectively driving the probe line, a semiconductor integrated circuit. 2. The circuit block includes a first block and a second block, each of which is substantially quadrangular, and a size of the second block is smaller than that of the first block. The semiconductor integrated circuit according to claim 1, wherein another circuit block is formed adjacently. 3. The integrated circuit chip is a master slice integrated circuit chip, the circuit block includes a plurality of basic cells arranged so that different logic circuits can be configured by changing wiring, and the other circuit block is a dedicated circuit. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit is formed by the circuit pattern. 4. The semiconductor integrated circuit according to claim 3, wherein the dedicated circuit includes at least one of a memory circuit and a central processing unit. 5. The semiconductor integrated circuit according to claim 1, wherein the test circuit is arranged along an edge of the integrated circuit chip. 6. The integrated circuit chip is a standard cell type integrated circuit chip, the circuit block has a standard cell structure, and the other circuit block is formed with a dedicated circuit pattern. Semiconductor integrated circuit. 7. The semiconductor integrated circuit according to claim 1, wherein the circuit block has a polygonal shape, and the probe line and the sense line are arranged on the entire surface of the block. 8. The at least one of the sense circuit and the drive circuit is divided into two or more regions and arranged along two adjacent sides of the circuit block.
Semiconductor integrated circuit. 9. A circuit formed on an integrated circuit chip (1) is classified into a first circuit block (9a, 9b) that performs a matrix probing test and a second circuit block (10) that does not perform a matrix probing test. A step of dividing the first circuit block into a plurality of substantially rectangular sub-blocks; and a plurality of sense lines (4a, 4) in each sub-block.
b) and arranging the probe lines (3a, 3b); test circuits (6a, 6b, 7) connected to the sense lines and the probe lines along two adjacent sides of each sub-block.
a, 7b, 8a, 8b), and a layout method of the semiconductor integrated circuit.