JPH0541432A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a manufacturing method making it easy to recognize whether a photo resist film is exposed and developed with desired precision, by a method wherein, in the manufacturing method of a high integration level IC containing a multilayer interconnection layer having step-differences, an L/S pattern for inspection is formed on the photo resist film corresponding with each of the wiring layers. CONSTITUTION:On a semiconductor substrate 1, function regions like wiring layers are formed in a plurality of layers. L/S patterns 2a-5d for inspection are formed for the respective processes, on the peripheral parts 1A-1D of a photo resist film covering the whole chip surface containing step-differences generated in the processes. At the same time as the formation of conductor wiring layers, interlayer insulating films, etc., the above L/S patterns are formed in the mutually adjacent positions by photolithography. The title manufacturing method contains the process wherein the resolution of the L/S pattern is inspected with a microscope in each forming process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor integrated circuit device (IC), and more particularly to a method for manufacturing such an IC having a multi-layer wiring layer.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor elements formed in a semiconductor substrate, the circuit wiring patterns formed on the surface of the substrate via an insulating film are becoming finer and more highly integrated.
A pattern having a line width of 1 μm or less has been required.
For the miniaturization / high integration of the elements in the semiconductor substrate and the miniaturization / high integration of the circuit wiring pattern on the substrate surface, the definition of the real image of the light-shielding mask formed on the photoresist film in the lithography process ( Resolution: Reso
must be secured. Therefore, as a light source of a reduction projection exposure apparatus (stepper) usually used for exposing a photoresist film, a light source with a short wavelength such as an excimer laser has been used. This is because, as is well known, this resolution increases substantially in proportion to the shortening of the wavelength of the light source of the above-mentioned exposure apparatus. On the other hand, the resolution is the numerical aperture (Numerica) of the lens of the exposure apparatus.
l Aperture: NA). That is, the larger the numerical aperture (NA), the higher the resolution. Therefore, in the exposure apparatus, a light source having a short wavelength is used as a light source, and a method of increasing the numerical aperture has been conventionally used because the shortening of the wavelength has reached a limit as a practical problem. However, the depth of focus (DO) of the optical system of this exposure apparatus is
Since F) is inversely proportional to the square of the numerical aperture, increasing the numerical aperture and increasing the resolution inevitably reduces the depth of focus,
The allowable range of the optimum focus in the exposure process becomes narrow.

[0003]

In the exposure of the photoresist film in the lithography process for forming the impurity diffusion layer in the semiconductor substrate, since the film usually fits in substantially the same plane, the optimum focus is within the allowable range. Narrowing is not a problem. However, since the wiring layer formed on the surface of the substrate via the insulating film, especially the photoresist film for forming each layer of the multi-layered wiring layer due to high integration, is formed on a flat surface with steps, the resist film It becomes difficult to put the whole into the above-mentioned allowable range. If even a part of the photoresist film is exposed in a state of deviating from the above-mentioned allowable range, the circuit pattern of that part causes a short circuit or a disconnection of the circuit, which reduces the yield rate of the product.

On the other hand, the above-mentioned reduction projection exposure apparatus is usually equipped with an auto-focusing device so that the above-mentioned optimum focus is automatically determined. However, the precise measurement of the distance by this device allows the reflected light from the IC surface to be reflected. Since the interference is caused by the above, the step on the surface affects the interference of this light and impairs the accuracy of distance measurement. Therefore, in the lithography processing of the IC surface including the step,
After the exposure and development of the photoresist film, a method of advancing to the next step after observing the entire actual circuit pattern or the circuit pattern portion including the above-mentioned step by a microscope is adopted. Instead of an actual circuit pattern, a predetermined check pattern formed in advance on the peripheral portion of the chip (usually line and pattern in which stripes and spaces are alternately arranged)
A method of confirming a space (Line and Space (L / S) repeating pattern, shown in Integrated Circuit Handbook (1968, Maruzen, P269, FIG. 6.109)) with a microscope is also adopted. However, since the former method becomes difficult to implement as the actual circuit pattern becomes complicated, the latter method tends to be adopted more generally.

Even with the latter method, the adverse effect of the step difference cannot be eliminated. That is, even if the optimum focus can be determined for the check pattern formed directly on the IC substrate, it cannot be determined whether the wiring patterns at different levels by the step difference are within the allowable range of the optimum focus. ..

Therefore, an object of the present invention is to provide a method for manufacturing a highly integrated IC including a multi-layer wiring layer with steps.
It is an object of the present invention to provide a manufacturing method in which it is easy to confirm whether or not the exposure and development of the photoresist film corresponding to each of the wiring layers are performed with a desired definition.

[0007]

A highly integrated IC according to the present invention is provided with the above-mentioned check patterns at at least two levels among a plurality of levels respectively corresponding to the multi-layer wiring layers, and these check patterns are simultaneously observed by a microscope. It is characterized in that it is arranged in the vicinity of the peripheral portion of the IC chip so as to be possible. The plurality of check patterns formed at different levels of the multi-layer wiring layer are formed in parallel with the actual circuit pattern of each layer in the peripheral portion of the chip. If there are no restrictions on the layout of actual circuit patterns, the check patterns can be formed on the interlayer insulating films of these patterns or on the extended portions of equivalent members that are substantially on the same plane as the patterns. If there is such a restriction, a dummy multi-layer wiring layer different from the actual circuit pattern is formed in parallel with each layer of the actual multi-layer wiring layer, and the check patterns are provided at positions close to each other in each of the dummy wiring layers. Form.

According to the present invention, in the wiring pattern forming step of each layer of the multi-layer wiring layer on the surface of the highly integrated IC chip, the real image of the light-shielding mask corresponding to the wiring pattern formed on the photoresist film is within the allowable range of the optimum focus. Since it can be checked whether or not there is at least two levels on the IC chip by observing with a microscope, it is possible to avoid deterioration of the resolution of the light-shielding mask real image.

[0009]

Next, two embodiments of the present invention will be described with reference to the drawings. First, referring to FIG. 1 showing an embodiment in which the present invention is applied to manufacture of a highly integrated DRAM device, a photoresist is applied to the entire surface of a semiconductor substrate 1 made of silicon (Si), and then a mask pattern corresponding to an active region is formed. The photoresist film is exposed through the vias and the substrate surface other than those corresponding to the active regions is subjected to a field oxide film forming step. In parallel with this, the L / S pattern 2a is formed on the field oxide film peripheral portion 1A (FIG. 1A).
Since the L / S pattern 2a can be formed in the peripheral edge portion 1A of the field oxide film, the opening for the active region is outside the range of FIG. 1A and is not shown.

Next, a step of forming a photoresist film on the entire surface of the field oxide film (FIG. 1 (a)) having the openings and performing a desired patterning to form a gate insulating film in the openings. At the same time, in parallel, L / S patterns 3a and 3b are respectively formed on the field oxide film peripheral portion 1A and the gate wiring layer peripheral portion 1B which are on the same plane as the field oxide film and the gate insulating film, respectively (FIG. b)). At that time, the L / S pattern 2a formed on the peripheral portion 1A of the field oxide film is removed by etching (illustrated by a dotted line in FIG. 1B).

Further, the first polysilicon wiring layer connected to the drain region (or source region, not shown) formed in each of the above active regions is similarly formed with a photoresist film, a wiring pattern exposure and Simultaneously with the step of forming through development, in parallel with the field oxide film, the gate wiring layer and the polysilicon wiring layer, the L / S patterns 4a, 4b and 4 are formed on the peripheral portions 1A to 1D respectively.
c is formed (FIG. 1C). In this step, the L / S patterns 3a and 3b formed in parallel with the gate wiring layer are removed by etching (shown by dotted lines in FIG. 1C).

Next, a second polysilicon wiring layer forming a capacitor connected to each source region (or drain region, not shown) of each of the above active regions is formed with a dielectric layer by an interlayer insulating layer. In parallel with the subsequent formation process, L /
S patterns 5a, 5b, 5c and 5d are formed on peripheral portions 1A, 1B, 1C and 1D on the same plane as the field oxide film, the gate wiring layer and the polysilicon wiring layer, respectively (FIG. 1 (d)). Along with this step, the L / S patterns 4a, 4b and 4c are removed (shown by the dotted line in FIG. 1D). The L / S patterns 2a, 3a, 3b,
All of 4a to 4c and 5a to 5d are formed at positions close to each other so as to be in the visual field of the optical microscope.

The L / S pattern 5 is subjected to the series of steps described above.
Semiconductor chip 1 on which a, 5b, 5c and 5d are formed
Referring to FIG. 2 which is an enlarged schematic view of the L / S pattern forming portion in FIG. 1D and FIG. 3 which is a sectional view thereof, the L / S patterns 5a, 5b, 5c and 5d are formed on the substrate 1. The peripheral portions 1A of the field oxide film 7a, the gate wiring layer 7b, the first polysilicon wiring layer 7c, and the second polysilicon wiring layer 7d, which have different levels with the interlayer films 8b to 8d sandwiched therebetween, with reference to the surface of The state formed in 1B, 1C and 1D is schematically shown.

In the above-described series of steps, it is checked whether the photoresist film for forming the gate wiring layer 7b (FIG. 3) is within the allowable range of the optimum focus of the exposure apparatus, which is the L / S pattern. This is done by simultaneously checking the resolution of 3a and 3b with a microscope (Fig. 1).
(B)). Similarly, to check whether the formation of the field oxide film 7a, the gate wiring layer 7b, and the first polysilicon wiring layer 7c is within the allowable range, the resolution of the L / S patterns 4a, 4b, and 4c is checked by a microscope. (Fig. 1 (c)). In addition, from the field oxide film 7a to the second polysilicon wiring layer 7d
It is checked by checking the L / S patterns 5a, 5b, 5c and 5d with a microscope whether or not the values up to the above are within the allowable range (FIG. 1 (d)).
As described above, in this embodiment, it is possible to easily confirm whether or not the wiring pattern of the formed wiring layer is formed with the required resolution in the desired process at the photoresist patterning step. If the result of the confirmation shows that the resolution is insufficient, the chip is re-coated with photoresist, exposed and developed. This can significantly improve the yield rate of products.

Next, referring to FIG. 4, a second embodiment of the present invention shown in a sectional view similar to that of FIG. 3 has a concave portion 9 (a deep portion in the same figure) formed in advance in the peripheral portion of the chip 1 by etching or the like. Although the height is emphasized, the L / S pattern 10a similar to that of the first embodiment is actually formed on the order of several .mu.m.
0a and another L / S pattern 10b on the wiring layer are subjected to resolution check by a microscope. Since each point is the same as that of the first embodiment, further description will be omitted, but this configuration is similar to that of the first embodiment.
It will be clear that it can be applied to IC devices other than RAM.

In the above first and second embodiments, L /
As the S pattern, the width and the spacing are each 0.4 to
A pattern composed of three stripes having a length of 0.8 μm and a length about 10 times the width was used. Further, it is suitable that the magnification of the above-mentioned confirmation microscope is about 20 to 100 times, and it is 4 in the embodiment.
0 times that used.

[0017]

As described above, according to the present invention, L / Ls formed at a plurality of locations on a semiconductor chip having height differences.
By putting the S pattern in the same field of view of the optical microscope and confirming its shape, it is possible to easily determine whether or not the entire surface of the semiconductor chip is within the depth of focus of the exposure light in advance before performing exposure with the reduction projection exposure apparatus. Since it can be inspected, it is not necessary to correct the depth of focus each time.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a first embodiment of the present invention, and FIGS. 1A to 1D are plan views of an IC chip for explaining a manufacturing process of a DRAM having a MOS structure.

FIG. 2 is an enlarged schematic plan view of a part of the plan view of FIG. 1 (d).

FIG. 3 is a vertical sectional view taken along line XX of FIG.

FIG. 4 is a vertical sectional view of an IC chip for explaining a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Field oxide film peripheral part 1B Gate wiring layer peripheral part 1C 1st polysilicon wiring layer peripheral part 1D 2nd polysilicon wiring layer peripheral part 2a, 3a, 3b, 4a-4c, 5a-5d L / S
Pattern 7a Field oxide film 7b Gate wiring layer 7c First polysilicon wiring layer 7d Second polysilicon wiring layer 8b to 8d Interlayer film 9 Recesses 10a, 10b L / S pattern

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI Technical display location 7013-4M H01L 21/30 341 K 7013-4M 341 P

Claims (3)

[Claims] 1. A semiconductor substrate having a large number of high-density impurity diffusion regions therein and electrically connected to the diffusion regions, respectively, and layered on the surface of the semiconductor substrate via an insulating film. A semiconductor integrated circuit device having a plurality of formed conductor wiring layers and having a surface including a plurality of surface portions defined by at least one of the insulator film and the wiring layer with respect to the substrate surface. 2. At least two surface portions each having substantially the same height as at least two predetermined heights out of the plurality of heights, the surface being free from electrical coupling with the conductor wiring layer. Forming a photoresist film for lithography processing for forming the wiring layer at positions adjacent to each other in a portion, and performing a predetermined line and A method of manufacturing a semiconductor integrated circuit device, comprising: exposing through a light-shielding mask of a space pattern to develop respective real images of the line-and-space pattern; and simultaneously inspecting the resolution of the real images with a microscope. 2. The semiconductor integrated circuit device is a dynamic RAM having a MOS structure, and the surface portion is formed in parallel with the formation of the plurality of conductor wiring layers and the insulator film. 1. A method for manufacturing a semiconductor integrated circuit device according to 1. 3. A step of etching the substrate prior to forming the diffusion region to form a recess defining at least one of the plurality of heights at a position corresponding to the surface portion of the substrate. The method of manufacturing a semiconductor integrated circuit device according to claim 1, including the above.