JPH0541373A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0541373A
JPH0541373A JP19634991A JP19634991A JPH0541373A JP H0541373 A JPH0541373 A JP H0541373A JP 19634991 A JP19634991 A JP 19634991A JP 19634991 A JP19634991 A JP 19634991A JP H0541373 A JPH0541373 A JP H0541373A
Authority
JP
Japan
Prior art keywords
protective film
photoresist
semiconductor device
manufacture
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19634991A
Other languages
Japanese (ja)
Other versions
JP2786029B2 (en
Inventor
Sunao Nakamura
直 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP3196349A priority Critical patent/JP2786029B2/en
Publication of JPH0541373A publication Critical patent/JPH0541373A/en
Application granted granted Critical
Publication of JP2786029B2 publication Critical patent/JP2786029B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To shorten the process period of the title manufacture and to reduce the cost of the title manufacture when a protective film for a semiconductor device is formed. CONSTITUTION:Aluminum wiring 8 is patterned; after that, a photoresist 10 is coated, exposed to light and developed; and an electrode part is opened. After that, ions are implanted at a high dose; the surface of the resist is hardened; and the resist is used as a protective film as it is. As a result, a process is simple as compared with the formation of a protective film in conventional cases, the process period of the tile manufacture can be shortened and the cost of the title manufacture can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特に配線の腐食やデバイスの劣化を防ぐための
保護膜の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a protective film for preventing corrosion of wiring and deterioration of devices.

【0002】[0002]

【従来の技術】図2を用いて従来の半導体装置の保護膜
形成方法を説明する図2(a)までの製造フローを簡単
に説明する。まずMOSトランジスタを形成するために
必要であるP型領域2,N型領域3となるウエル領域
(Pウエル,Nウエル)を形成する。さらに素子分離領
域を形成するために局所酸化方式により、厚い酸化膜領
域4(フィールド)とそれに囲まれたMOSトランジス
タを形成する拡散層領域を形成する。次に素子領域に相
当するウエハ表面を酸化してゲート酸化膜を形成し、そ
の上にゲートとなる多結晶シリコン膜を堆積させる。次
にゲート部5を残して他の部分をエッチングし、ゲート
部とフィールド酸化膜をマスクにしてイオン打込みを行
ない、熱処理を行って拡散層6を形成する。この後配線
間の絶縁性を保つための層間膜7を堆積させ、拡散層へ
配線を接続するためのコンタクト穴あけのエッチング処
理を行ない配線となるアルミニウム8を堆積させ、パタ
ーンニングを行う。次に図2(b)に示すように保護膜
9を成長させ、図2(c)に示すようにフォトレジスト
を塗布し、露光,現像してパターニングを行う。そし
て、図2(d)に示すように電極部となる部分の保護膜
をエッチングし、最後に図2(e)に示すようにフォト
レジストを除去することにより、従来まで保護膜を形成
していた。
2. Description of the Related Art A manufacturing flow up to FIG. 2A for explaining a conventional method for forming a protective film of a semiconductor device will be briefly described with reference to FIG. First, well regions (P well, N well) to be the P type region 2 and N type region 3 necessary for forming a MOS transistor are formed. Further, in order to form an element isolation region, a thick oxide film region 4 (field) and a diffusion layer region for forming a MOS transistor surrounded by the thick oxide film region 4 are formed by a local oxidation method. Next, the surface of the wafer corresponding to the element region is oxidized to form a gate oxide film, and a polycrystalline silicon film to serve as a gate is deposited thereon. Next, the gate portion 5 is left and other portions are etched, ion implantation is performed using the gate portion and the field oxide film as a mask, and heat treatment is performed to form the diffusion layer 6. After that, an interlayer film 7 for maintaining the insulation between the wirings is deposited, an etching process for contact hole formation for connecting the wiring to the diffusion layer is performed, and aluminum 8 to be the wiring is deposited, and patterning is performed. Next, a protective film 9 is grown as shown in FIG. 2B, a photoresist is applied as shown in FIG. 2C, and exposure and development are performed for patterning. Then, as shown in FIG. 2D, the protective film in the portion to be the electrode portion is etched, and finally the photoresist is removed as shown in FIG. It was

【0003】[0003]

【発明が解決しようとする課題】従来までは、保護膜を
形成するために、保護膜成長フォトレジスト塗布・パタ
ーンニング,保護膜エッチング,フォトレジスト除去と
いった工程が必要であり、保護膜形成においては工期短
縮,コスト低減を達成するのは困難であった。
In the past, steps such as protective film growth photoresist coating / patterning, protective film etching, and photoresist removal were required to form a protective film. It was difficult to reduce the construction period and cost.

【0004】本発明の目的は、半導体装置の保護膜形成
において、工期短縮、コスト低減を達成することを目的
とする。
An object of the present invention is to achieve a shortened construction period and cost reduction in forming a protective film for a semiconductor device.

【0005】[0005]

【課題を解決するための手段】前記目的を達成するため
に本発明の半導体装置の製造方法は、アルミニウム堆
積,パターンニング後アルミニウム上に直接フォトレジ
ストを塗布し、電極部を開孔するために露光,現像す
る。その後フォトレジストを高ドーズイオン打込みで硬
化させ、このレジスト自体を保護膜とするものである。
In order to achieve the above-mentioned object, a method of manufacturing a semiconductor device of the present invention is to deposit a photoresist and directly apply a photoresist on the aluminum after patterning to open an electrode portion. Expose and develop. After that, the photoresist is hardened by high dose ion implantation, and the resist itself is used as a protective film.

【0006】[0006]

【実施例】次に本発明について図面を参照して説明す
る。図1は、本発明の一実施例を説明するための工程順
に示した半導体素子の断面図である。図1(a)は配線
となるアルミニウムのパターンニングまで終わった状態
を示している。この状態から従来までは、保護膜となる
膜を成長させていたが、本発明では、図1(b)に示す
ように、フォトレジストをウエハ全面に塗布し、電極部
を開孔するために露光,現像を行う。この後図1(C)
に示すように、フォトレジストに対し高ドーズのイオン
打込みを行う。有機物であるフォトレジストは、この高
ドーズのイオン打込みで表面が焼け、硬くなるわけであ
る。このイオン打込みに関しては、注入原子の種類に気
をつける必要があり、例えば、金属原子をレジストに打
込むとリークの原因となったり、デバイスの劣化を招く
ことになるのでシリコン原子等の半導体あるいは絶縁体
の原子を打込むのが適切である。またドーズ量に関して
も、アルミニウム電極部の導電性が損なわれず、かつ充
分レジストが硬化するよう制御しなければならない。例
えばシリコン原子を打込む時は1×1018/cm-3〜1
×1014/cm-3の間に最適点がある。もちろんレジス
トの種類によってこの値も多少増減する。このようにし
て得られたフォトレジストは、保護膜として充分耐性を
持ち組立工程でのモールド封入に対しても従来までの保
護膜と同等の強度・保護能力を備えている。
The present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views of a semiconductor device in the order of steps for explaining an embodiment of the present invention. FIG. 1A shows a state in which patterning of aluminum to be wiring is completed. From this state to the conventional method, a film serving as a protective film was grown, but in the present invention, as shown in FIG. 1B, a photoresist is applied to the entire surface of the wafer to open the electrode portion. Perform exposure and development. After this, Fig. 1 (C)
As shown in, a high dose ion implantation is performed on the photoresist. The photoresist, which is an organic substance, has its surface burned and hardened by this high-dose ion implantation. Regarding this ion implantation, it is necessary to pay attention to the type of implanted atoms. For example, when a metal atom is implanted into a resist, it may cause a leak or cause deterioration of the device. Implanting atoms of the insulator is appropriate. Also, the dose amount must be controlled so that the conductivity of the aluminum electrode portion is not impaired and the resist is sufficiently cured. For example, when implanting silicon atoms, 1 × 10 18 / cm -3 -1
There is an optimum point in the range of × 10 14 / cm -3 . Of course, this value may increase or decrease depending on the type of resist. The photoresist thus obtained has sufficient resistance as a protective film, and has the same strength and protective ability as the conventional protective film against mold encapsulation in the assembly process.

【0007】[0007]

【発明の効果】以上説明したように本発明の半導体装置
の製造方法では、アルミニウム配線後に保護膜を成長さ
せ、エッチングするという工程を省き、フォトレジスト
自体を塗布し保護膜とするため、工期短縮,コスト低減
という効果を有する。
As described above, in the method for manufacturing a semiconductor device of the present invention, the process of growing a protective film after aluminum wiring and etching is omitted, and the photoresist itself is applied as the protective film, so that the manufacturing period is shortened. , It has the effect of cost reduction.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を説明するために工程順に示
した半導体素子の断面図である。
FIG. 1 is a cross-sectional view of a semiconductor device shown in the order of steps for explaining an embodiment of the present invention.

【図2】従来の半導体装置の製造方法を説明するために
工程順に示した半導体素子の断面図である。
FIG. 2 is a cross-sectional view of a semiconductor element, which is shown in order of steps for explaining a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 Pウエル 3 Nウエル 4 フィールド酸化膜 5 多結晶シリコンゲート 6 拡散層 7 層間絶縁膜 8 アルミニウム配線 9 保護膜 10 フォトレジスト 1 Semiconductor Substrate 2 P Well 3 N Well 4 Field Oxide Film 5 Polycrystalline Silicon Gate 6 Diffusion Layer 7 Interlayer Insulation Film 8 Aluminum Wiring 9 Protective Film 10 Photoresist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置の製造方法において、アルミ
ニウム配線を形成する工程と、前記アルミニウム配線の
形成された半導体基板上にフォトレジストを塗布する工
程と、前記フォトレジストを露光,現像しパット部を開
孔する工程と、前記パット部の開孔されたフォトレジス
ト自体を硬化させる工程とを有し、前記硬化されたフォ
トレジストをそのまま保護膜とすることを特徴とする半
導体装置の製造方法。
1. A method of manufacturing a semiconductor device, comprising: a step of forming aluminum wiring; a step of applying a photoresist on a semiconductor substrate having the aluminum wiring formed thereon; and a step of exposing and developing the photoresist to form a pad portion. A method of manufacturing a semiconductor device, comprising: a step of forming a hole; and a step of curing the photoresist itself, which has been opened in the pad portion, and using the cured photoresist as it is as a protective film.
JP3196349A 1991-08-06 1991-08-06 Method for manufacturing semiconductor device Expired - Lifetime JP2786029B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3196349A JP2786029B2 (en) 1991-08-06 1991-08-06 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3196349A JP2786029B2 (en) 1991-08-06 1991-08-06 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0541373A true JPH0541373A (en) 1993-02-19
JP2786029B2 JP2786029B2 (en) 1998-08-13

Family

ID=16356365

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3196349A Expired - Lifetime JP2786029B2 (en) 1991-08-06 1991-08-06 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2786029B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646869A (en) * 2013-11-29 2014-03-19 上海华力微电子有限公司 Wafer cleaning method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5141963A (en) * 1974-10-07 1976-04-08 Suwa Seikosha Kk Shusekikairosochino kozo
JPS5141964A (en) * 1974-10-07 1976-04-08 Nippon Electric Co
JPS5632731A (en) * 1979-08-27 1981-04-02 Fujitsu Ltd Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5141963A (en) * 1974-10-07 1976-04-08 Suwa Seikosha Kk Shusekikairosochino kozo
JPS5141964A (en) * 1974-10-07 1976-04-08 Nippon Electric Co
JPS5632731A (en) * 1979-08-27 1981-04-02 Fujitsu Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103646869A (en) * 2013-11-29 2014-03-19 上海华力微电子有限公司 Wafer cleaning method

Also Published As

Publication number Publication date
JP2786029B2 (en) 1998-08-13

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Legal Events

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A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19980428