JPH0541097A - Static type semiconductor storing device - Google Patents

Abstract

PURPOSE:To perform a burn-in in a short time and to reduce a time for screening. CONSTITUTION:A pulse signal with a prescribed pulse width is generated by a pulse generating circuit 63 in accordance with the level change of a chip enable control signal/CE1 and a write enable control signal/WE and the output Q of a flip-flop 66 is set to a 'H' level in an interval when the chip enable control signal CE2 is activated. The above-mentioned pulse signal and the output Q of the flip-flop 66 are supplied to a row decoder through an OR gate 67.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a static type semiconductor memory device in which data write / read operations are performed, and more particularly to a static type semiconductor memory device in which burn-in time after manufacturing is shortened.

[0002]

2. Description of the Related Art In a semiconductor memory in which data writing / reading operations are performed, for example, a static semiconductor memory having static memory cells, a word line is selected and selected according to an address signal when writing or reading data. Data is written to or read from the memory cell connected to the word line.

Generally, in a static semiconductor memory,
Current is consumed in the memory cell during the period selected by the word line. Therefore, in recent static semiconductor memories, in order to reduce power consumption, word lines are driven in a pulsed manner, and when the data writing / reading period ends, the driving of the word lines is stopped. Being developed.

On the other hand, when manufacturing and shipping a semiconductor device, in order to ensure its reliability, a potential defect of the semiconductor device is exposed so that a good product is not deteriorated or a defective product is not provided.
Screening is performed to remove defective semiconductor devices. As a screening method, a burn-in method that can simultaneously realize electric field acceleration and temperature acceleration is widely used. In this burn-in method, the voltage is higher than the actual working voltage,
By operating the semiconductor device at a temperature higher than the actual use temperature, the semiconductor device may be subjected to stress more than the initial failure period under the actual use condition in a short time, which may cause initial operation failure. Are selected and screened before shipment. As a result, the semiconductor device that may cause the initial malfunction is effectively removed, and the reliability of the product can be improved.

In the field of semiconductor memory, it is necessary to apply voltage stress to a word line for a predetermined period at the time of burn-in. However, in the conventional static semiconductor memory, since the word line is pulse-driven for the purpose of reducing power consumption, only a very small voltage stress can be applied with one access, and long-time screening is required. There is a problem that it becomes necessary.

[0006]

As described above, the conventional static semiconductor memory device has a problem in that it takes a long time for burn-in because the word line is constantly pulse-driven.

The present invention has been made in consideration of the above circumstances, and an object thereof is to carry out burn-in in a short time and to shorten the time required for screening. It is to provide a device.

[0008]

In a static semiconductor memory device of the present invention, a word line to which a static memory cell is connected and the word line is continuously driven for a period defined by an external control signal. And a word line driving means for driving the same.

Further, the word line drive means detects a level change of each of the first chip enable control signal and the write enable control signal and generates a first pulse signal having a predetermined pulse width. Means, second pulse signal generating means for generating a second pulse signal having a pulse width corresponding to the activation period when the second chip enable control signal is activated, the first pulse signal, and A logical sum gate supplied with a second pulse signal,
It is characterized by comprising an address decoding means for supplying the address signal and the output of the logic gate and controlling the supply of the output of the logic gate to the word line corresponding to the address signal.

[0010]

When the burn-in is performed, the driving period of the word line can be set by the external control signal, and thus the voltage stress can be applied to the circuit connected to the word line for a necessary period with one access. You can

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

FIG. 4 is a block diagram showing a schematic structure of the entire static type semiconductor memory device of the present invention. In the figure, a row address buffer 11 receives an external row address and generates an internal row address having a complementary level for each bit from the external row address. This internal row address is supplied to the row decoder 12. The output of the row decoder 12 is supplied to the memory cell array 13.
In this memory cell array 13, static type memory cells (not shown) are arranged in the row direction and the column direction, and the memory cells arranged in each row are connected to a plurality of word lines (not shown) and arranged in each column. The cells are connected to a plurality of bit line pairs (not shown). Then, based on the output of the row decoder 12, 1 of the memory cell array 13 is
Two word lines are selected.

On the other hand, the column address buffer 14 receives an external column address and generates an internal column address having a complementary level for each bit from the external column address. This internal column address is supplied to the column decoder 15. The output of the column decoder 15 is supplied to the column select gate 16. The column select gate 16 selects one of a plurality of bit line pairs of the memory cell array 13 based on the output of the column decoder 15.

Reference numeral 17 is a sense amplifier. The sense amplifier 17 amplifies a read potential from a memory cell connected to one bit line pair selected by the column select gate 16 at the time of data reading and outputs it as data to the outside, and at the time of data writing. , A potential corresponding to write data is supplied to the memory cells connected to one bit line pair selected by the column select gate 16.

Reference numeral 18 is a control circuit. This control circuit 18
Various internal control signals are generated based on a write control signal / WE and two types of chip select control signals / CE1 and CE2 supplied from the outside. The pulse signal WP which is one internal control signal generated here is supplied to the row decoder 12.

FIG. 5 is a circuit diagram showing a detailed structure near the memory cell array 13 in the above embodiment. A large number of memory cells are provided in the memory cell array 13 as described above, and only one memory cell 20 is shown in the figure. The memory cell 20 is a so-called E / R type memory cell in which resistors are used as the load elements 21 and 22, and N-channel MOS transistors are used as the drive elements 23 and 24 and the transfer gates 25 and 26. The memory cell 20 is connected to the word line WL and the bit line pair BL, / BL.

A bit line precharge / equalize circuit 30 is connected to the bit line pair BL, / BL. In this circuit 30, P-channel MOS transistors 31 and 32 for bit line precharge control are inserted between the bit lines BL and / BL and the power supply voltage Vcc. A P-channel MOS transistor 33 for controlling bit line equalization is inserted between the bit lines BL and / BL. And for each of the above transistors
The precharge control signal φP is supplied to the gates of 31, 32 and 33.

Further, P is connected to the bit line pair BL, / BL.
The channel side write select circuit 40P and the N channel side write select circuit 40N are connected. One P-channel side write select circuit 40P includes a bit line pair BL, /
P-channel MOS that is inserted between BL and the power supply voltage Vcc, and the gate is supplied with the write select signal / SWE
It is composed of transistors 41 and 42. The other N-channel side write select circuit 40N includes a bit line pair BL, / B
It is composed of N-channel MOS transistors 43 and 44 which are inserted between L and the data line pair DL and / DL and whose gate is supplied with the write select signal SWE.

In the column select gate 16, an N-channel MOS transistor is inserted between the source and drain in the middle of each of the bit line pair BL, / BL, and the decode output CDL of the column decoder 15 is supplied to the gate. 51 and 52 are provided. The MOS transistors used in the circuit of FIG. 5 are all enhancement type.

FIG. 1 shows a detailed structure of a circuit portion for generating the pulse signal WP in the control circuit 18. The write enable control signal / WE is supplied to one input terminal of a 2-input AND gate 62 via an inverter 61. The one chip select control signal / CE1 is an inverter
It is supplied to one input terminal of a 2-input AND gate 64 via 63. The other chip select control signal CE2 is supplied to the other input end of the 2-input AND gate 64.

The output of the AND gate 64 is supplied to the other input terminal of the AND gate 62. Also, AND gate
The output of 62 is supplied to the pulse generation circuit 65 and also to the data input terminal of the D-type flip-flop 66. The pulse generation circuit 65 generates a pulse signal having a predetermined pulse width when the output of the AND gate 62 rises. The pulse signal generated by the pulse generation circuit 65 is a 2-input OR gate 67.
Is supplied to one input terminal.

On the other hand, the chip select control signal CE2
Is supplied to the fall detection circuit 68. This fall detection circuit
68 generates a pulse signal having a predetermined pulse width each time the output level of the signal CE2 changes from the "H" level to the "L" level, that is, at the falling edge of the signal CE2. The pulse signal generated by the fall detection circuit 68 is supplied to the reset input terminal of the flip-flop 66.

The chip select control signal CE2 is further supplied to the clock signal input terminal of the flip-flop 66 via the delay circuit 69. The Q output of the flip-flop 66 is supplied to the other input terminal of the OR gate 67, and the output of the OR gate 67 is supplied to the row decoder 12 as the pulse signal WP.

The three types of control signals will be described below. The write enable control signal / WE is a signal which is set to the "L" level when the memory is in the write mode, and the two types of chip select control signals. / CE
1 and CE2 are signals for selecting a read / write operation and a chip select function or a data backup function. In the memory of this embodiment, the burn-in period is set using one of the chip select control signals CE2.

FIG. 2 is a circuit diagram showing a detailed structure of the row decoder 12. The row decoder 12 is provided with AND gates 70, 70, ... With a plurality of inputs. These AN
The pulse signal WP output from the circuit shown in FIG. 1 is supplied in parallel to one input terminal of each of the D gates 70, 70, ..., And the row address buffer 11 is supplied to the remaining input terminals.
Row addresses RA0, RA1, ... RA output from
n, / RA0, RA1, ... RAn, ... RA0, RA1,
... / RAn is supplied. And these AND gates
Any one of the plurality of word lines WL is selectively driven by the outputs of 70, 70, ....

Next, the data write (write) operation of the memory configured as described above will be described with reference to the timing chart of FIG. There are three types of write operation of the memory of this embodiment: a write operation by the control signal / WE, a write operation by the chip enable control signal / CE1 and a write operation by the chip enable control signal CE2.

First, in the write operation by the control signal / WE, the chip enable control signal CE2 is at "H" level,
This is performed in a state where the chip enable control signal / CE1 is fixed at the "L" level. In this state / W
When E changes from "H" level to "L" level,
In the circuit shown in, the output of the inverter 61 rises from the "L" level to the "H" level. At this time, CE2 is at "H" level, the output of the inverter 63 to which / CE1 is input is at "H" level, and both signals are input to AND
The output of the gate 64 is at "H" level. Therefore,
When / WE changes from "H" level to "L" level,
The output of the AND gate 62 changes from "L" level to "H" level. Then, the level change of the output of the AND gate 62 is detected by the pulse generating circuit 65, and the pulse generating circuit 65 generates the pulse signal WP having a predetermined pulse width. The pulse width of the pulse signal WP is set to a short period sufficient to write data in each memory cell. The pulse signal WP is supplied to the row decoder 12 via the OR gate 67. The row decoder 12 outputs the pulse signal WP from one of the AND gates 70, 70, ... Which corresponds to the external row address. As a result, one word line WL to which this pulse signal WP is supplied is driven only for the period of the signal WP, and the memory cell connected to this word line WL is selected. At this time, the write potential is supplied from the sense amplifier 17 to the memory cell 13 via the column select gate 16, and data is written to the memory cell selected by the word line WL.

The write operation by the control signal / CE1 is
The operation is performed in a state where the chip enable control signal CE2 is fixed at "H" level and the write enable control signal / WE is fixed at "L" level. When / CE1 changes from "H" level to "L" level in this state, the output of the inverter 63 rises from "L" level to "H" level in the circuit shown in FIG. At this time, since CE2 is at "H" level, when / CE1 changes from "H" level to "L" level, the output of the AND gate 64 changes from "L" level to "H" level. On the other hand, since the output of the inverter 61 to which / WE is input is at the “H” level,
When CE1 changes from "H" level to "L" level,
The output of the AND gate 62 changes from "L" level to "H" level. Then, the level change of the output of the AND gate 62 is detected by the pulse generation circuit 65, and the pulse generation circuit 65 generates the pulse signal WP having the same pulse width as the case of the level change of / WE. Similarly, data writing is performed.

The write operation by the control signal CE2 is performed with the chip enable control signal / CE1 fixed at the "L" level and the write enable control signal / WE fixed at the "L" level. When CE2 changes from the "L" level to the "H" level in this state, the output of the AND gate 62 in the circuit shown in FIG. 1 rises from the "L" level to the "H" level. Further, since CE2 is supplied as a clock signal to the flip-flop 66 via the delay circuit 69, the Q output of the flip-flop 66 rises to "H" level when CE2 changes to "H" level. Therefore, the pulse signal W output from the OR gate 67
P rises to "H" level after CE2 changes to "H" level. Next, when CE2 changes from the "H" level to the "L" level, the outputs of the AND gate 64 and the AND gate 62 also sequentially fall from the "H" level to the "L" level. Further, when CE2 falls to the “L” level, the fall detection circuit 68 detects this fall, and the fall detection circuit 68 outputs a signal having a predetermined pulse width. And
After this signal is input to the reset input terminal of the flip-flop 66, the flip-flop 66 is reset and its Q output falls to "L" level.

That is, in the case of the write operation by CE2, the pulse width of the pulse signal WP is set according to the pulse width of CE2 as shown in FIG.
The word line WL is selectively driven only during the pulse width of P. Therefore, voltage stress can be applied to the word line for an arbitrary period during burn-in, and the time required for screening can be shortened. Moreover, in the normal data write operation (write operation by / WE and / CE1), since the word line is driven in a pulsed manner, there is no fear that power consumption will increase. Although only the data write operation is described in the above embodiment,
Of course, the data can be read.

In the above embodiment, the case where the chip enable control signal CE2 is used to set the drive period of the word line at the time of burn-in has been described. However, the drive period of the word line is set using another external control signal. Of course, it may be set.

[0032]

As described above, according to the present invention,
It is possible to provide a static semiconductor memory device capable of performing burn-in in a short time and shortening the time required for screening.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a detailed configuration of a partial circuit of a device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a partial circuit of a device according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the apparatus according to the embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of an entire apparatus according to an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a detailed configuration of a partial circuit of a device according to an embodiment of the present invention.

[Explanation of symbols]

11 ... Row address buffer, 12 ... Row decoder, 13 ... Memory cell array, 14 ... Column address buffer, 15 ... Column decoder, 16 ... Column select gate, 17 ... Sense amplifier, 18 ... Control circuit, 20 ... Memory cell, 30 ... Bit line precharge / equalize circuit, 40P ... P channel side write select circuit, 40N ... N channel side write select circuit, 61, 63 ... Inverter, 62, 64 ... AND gate, 65
… Pulse generator, 66… D-type flip-flop, 67… O
R gate, 68 ... Fall detection circuit, 69 ... Delay circuit.

Claims (2)

[Claims] 1. A word line connected to a static memory cell, and a word line driving means for continuing the driving of the word line during a period defined according to an external control signal. Static semiconductor memory device. 2. A first pulse signal generating circuit for generating a first pulse signal having a predetermined pulse width by detecting a level change of each of a first chip enable control signal and a write enable control signal by the word line driving means. Means, second pulse signal generating means for generating a second pulse signal having a pulse width corresponding to the activation period when the second chip enable control signal is activated, the first pulse signal, and It comprises an OR gate to which a second pulse signal is supplied, and an address decoding means to which an address signal and the output of the logic gate are supplied and which controls the supply of the output of the logic gate to a word line according to the address signal. The static semiconductor memory device according to claim 1, wherein