JPH0540689A - Buffer memory control system - Google Patents

Abstract

PURPOSE:To solve a problem to generate data transfer frequently when a certain processor (CPU) makes access an area including a lock word in a buffer memory control system for an information processor providing with buffer memory (LBS) in plural CPUs controlled with a swap system. CONSTITUTION:This system is comprised in such a way that the holding state of the exclusive area of another CPU is changed from an exclusive state (E=1) to a shared state (E=0), and its own LBS is registered in the shared state, and when an area including the lock word that exists in the LBS of another CPU is rewritten, the area is updated to the exclusive area, and the data transfer can be prevented from being performed at the next exclusive readout by a compare and swap (CS) instruction when no block exists in its own LBS in the exclusive readout of the exclusive area including the lock word by the CS instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a plurality of processors (CP
U) is a buffer memory (LBS) controlled by swap method
The present invention relates to a control method of a buffer memory in an information processing device including the.

Conventionally, memory access is performed at high speed,
An information processing apparatus (multiprocessor system) is known in which a processor (CPU) has a swap-type buffer memory (LBS) in order to improve the processing capacity, and also has a plurality of processors (CPU).

In such a system, an area acquired by a certain processor (CPU) is placed in an exclusive state so as not to be used by another processor (CPU), for example, read → comparison → write is performed as a series of operations. Until the instruction ends, an instruction that does not allow the update of the area by another processor (CPU), that is, a compare & swap instruction (C
S command).

When an exclusive area acquired by a certain processor (CPU) is used by another processor (CPU) for the purpose of accessing the area by using the CS instruction, the area is self-owned. If it does not exist in the buffer memory (LBS) of the processor (CPU), the corresponding block is transferred from the other buffer memory (LBS) to its own buffer memory (LBS) and the other buffer memory (LBS) is invalidated. Then, the own buffer memory (LBS) is set to the exclusive state and referred to.

Therefore, a plurality of processors (CPUs) are
Each time the S instruction is used, data transfer of the block including the exclusive area occurs, which is also a factor that hinders the performance of the information processing apparatus.

From the above, the plurality of processors (C
Even if the PU) uses the CS instruction, a buffer memory control method that can complete the minimum required data transfer is required.

[0007]

2. Description of the Related Art FIGS. 3 to 6 are views for explaining a conventional buffer memory control system, FIG. 3 shows a conceptual diagram of an information processing apparatus, and FIG. 4 shows a conceptual diagram of a buffer memory (LBS). 5 and 6 show an example of the operation flow when accessing the buffer memory.

As shown in FIG. 3, an information processing apparatus related to the present invention comprises a plurality of processors (CPU) 1, each of which is provided with a buffer memory (LBS) 10 shown in FIG. During memory access, the tag memory (TAG) 11 of its own buffer memory (LBS) 10 is searched, and when there is no block containing the desired data in the buffer memory (LBS) 10, main memory control is performed. Send a read / write request to the device (MCU) 2, move the block existing in the buffer memory (LBS) 10, or the main memory (MSU) 3 of the other processor (CPU) 1 to the own buffer. Register in memory (LBS) 10.

FIG. 4 shows a configuration example of the buffer memory (LBS) 10 and the tag memory (TAG) 11. In this figure, V indicates a valid bit of a block, and when the block is valid, V = 1 indicates that data corresponding to the main memory unit (MSU) 3 indicated by the upper address portion exists. When V = 0, it means that it is in an unused state.

Further, in the figure, E is a flag showing the exclusive / shared state of the corresponding block. When E = 0, the shared state is shown, and when E = 1, the exclusive state is shown. Shows.

The buffer memory (LB
5 and 6 show examples of the operation flow when S) 10 is accessed. In the swap type buffer memory device, all processors (CPU0 to CPUn) 1 can hold the read (that is, multiple processors (CPU) 1 can hold the latest data), and read / write is not possible in the “shared” state. Then, the block in the buffer memory (hereinafter referred to as LBS) 10 is held, and in the case of writing, the requested processor
(CPU) Holds only 1 and is readable / writable "exclusive"
Hold the block in the state.

Further, for exclusive control among a plurality of processors (CPU0 to CPUn) 1, as described above, read-compare-write is performed as a series of operations, and the other processors wait until the instruction is completed. Command that does not allow update (CS: Compare an
d Swap instruction, etc.) is provided, and references and updates of the exclusive area (lock word) are performed.

In the conventional swap type buffer memory device, in the case of such a CS instruction, exclusive control can be realized by operating on the premise of writing even at the first reading.

That is, looking at the time of exclusive read in the operation flow of FIG. 5, when the own LBS 10 exists in the exclusive state, the own LBS 10 is read, but the own LBS 10 is read.
When not present in the conventional method, other processors (CPU)
When it exists in LBS 10 of 1, it moves out (transfers) from another LBS 10 and invalidates (BI) the corresponding block of the other LBS 10 that has been moved out to put its own LBS in an exclusive state. {Refer to processing steps 100 to 102} Then, when it does not exist in the LBS 10 of the other processor (CPU) 1, it is read and registered as “exclusive” from the main memory unit (MSU) 3. {Refer to processing steps 100 to 103} As a specific example, when a certain processor (CPU0) 1a has acquired the exclusive area, another processor (CPU0)
1) When 1b executes the above-mentioned CS command for the exclusive area including the lock word, the above exclusive read is executed, and since the exclusive area does not exist in its own LBS 10, the processing moves to processing steps 101 and 102. L of processor (CPU0) 1a
Move out (transfer) the corresponding block from BS 10,
The LBS 10 of the processor (CPU0) 1a is invalidated (BI), and its own LBS 10 is set to the exclusive state.

Here, when the processor (CPU0) 1a tries to release the lock and accesses the block concerned, the block is already in the LBS 10 of the processor (CPU1) 1 as described above. Since it has moved, the same operation as above is performed, and moveout (transfer) is performed again.

[0016]

In such exclusive control, the number of processors (hereinafter, CPU) increases,
When the number of collisions of CPU access to the exclusive area increases, if the exclusive area is regularly accessed to wait for a lock word (wait for acquisition of a lock word), the CPU that is actually using the exclusive area Data transfer from the LBS to the LBS of the waiting CPU frequently occurs (the above moveout), which causes a problem in the performance of the information processing apparatus.

In view of the above-mentioned conventional drawbacks, the present invention provides a buffer memory control system capable of reducing the data transfer between CPUs until the lockword is released when waiting for the lockword by a CS instruction. The purpose is that.

[0018]

1 and 2 are flowcharts showing an embodiment of the present invention. The above problems can be solved by the buffer memory control method configured as follows. In an information processing device having a plurality of processors (CPUs) 1a, 1b, ... each having a buffer memory (LBS) 10 controlled by a swap method, a block in the buffer memory (LBS) 10 is a rewritten block. Yes, or the "exclusive" (E = 1) state that indicates that the block has been read for rewriting, and the "shared" (E = 0) that indicates that the block has been read for only reading. ) Is a buffer memory device which controls on the basis of two states, and when a block in the buffer memory (LBS) 10 of a processor (CPU) 1a is rewritten by the processor (CPU) 1a. , Processor (CPU) 1b other than the processor (CPU) 1a
Is rewritten only when the content of the block has a certain value (all "0"), when the block is read, the block of the buffer memory (LBS) 10 of the processor (CPU) 1a If the block is in the exclusive state, the block is in the exclusive state (E
= 1) to the shared state (E = 0), and the processor (CPU) 1b that has requested the exclusive read transmits a signal indicating that the exclusive processing has failed together with the read data, Request processor (CPU) 1b buffer memory (LB
S) 10 also registered in shared state {processing steps 100, 101, 104,
106}, and the buffer memory (L) in the request processor (CPU) 1b
If it is held in the BS) 10 in a shared state, it is read as it is {processing steps 100, 107, 108} and the processor (C
The block of the processor (CPU) 1a is set to the exclusive state (E = 1) only when writing is performed to the block of the buffer memory (LBS) 10 of the PU) 1a {processing steps 110, 111, 112, 11
3} is configured.

[0019]

That is, in the present invention, the exclusive read is performed in the read by the CS instruction, but when it is held in the shared state in the LBS of another CPU, the state is not changed and the data is directly stored in the own LBS. Even if the data is transferred and held in the shared state in the own LBS, the read is performed as it is.

If the LBS of the other CPU is held in the exclusive state, the holding state of the other CPU is changed from exclusive (E = 1) to shared (E = 0), and the shared state is maintained in the own LBS. Configure to register.

Therefore, when waiting for a lock word with the CS instruction, data is transferred by moving out to its own LBS only when the lock word is first referenced, but the block containing the lock word is in a shared state. (E
= 0), it remains in the corresponding LBS, so it is sufficient to refer to its own LBS for the next access for waiting, and the data transfer of the block containing the lock word is not performed. ..

Then, the CPU belonging to the corresponding LBS is
Only when the area containing the lock word is rewritten in order to release the lock word, the CPU has its own LB.
Since S is written exclusively, other CPs will be written later.
When there is a wait access from U, data transfer occurs only at that time, and there is an effect that the data transfer between CPUs until the lock is released can be reduced.

[0023]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 and 2 are flow charts showing an embodiment of the present invention.

In the present invention, a plurality of processors (CP
U) 1 is the buffer memory (LB
In the information processing device equipped with S) 10, when the exclusive read of the exclusive area including the lock word is performed by the CS instruction, if the corresponding block does not exist in its own buffer memory (LBS) 10, the block exists. Other processors (C
PU) 1 buffer memory (LBS) 10 holding status is exclusive
Change from (E = 1) to the shared state (E = 0), register it in its own buffer memory (LBS) 10 in the shared state, and
U) When the area containing the lock word in the buffer memory (LBS) 10 of 1 is rewritten, the area in the shared state is updated to the exclusive area, and the next exclusive read is performed by the CS instruction. The means by which data transfer occurs is the means necessary for practicing the present invention. The same reference numerals denote the same objects throughout the drawings.

Hereinafter, referring to FIG. 3 and FIG.
The buffer memory control method of the present invention will be described with reference to the flowchart of FIG. FIG. 3 described above shows a conceptual diagram of the information processing apparatus, and FIG. 4 shows a conceptual diagram of the LBS. In the information processing device shown in FIG. 3, each processor (CPU0, CP
For example, U1, ~) 1 executes the following instruction sequence.

XR R0, R0: Value when the lock word is unlocked LA R1, X'FFFFFFFF ': Value for putting the lock word in the lock state LOOP: CS R0, R1, LOCK: Lock acquisition processing BNZ LOOP : Re-processing when lock cannot be acquired L R2, LOCK + 4: Processing performed by acquiring lock A R2, LOCK + 4: Processing performed by acquiring lock ST R0, LOCK: Lock release processing B ** *: Here, the case where the processor (CPU1) 1a acquires the lock to perform processing and the processor (CPU2) 1b waits for the lock will be described. However, each instruction is basically processed in one cycle, the access time of the MSU is, for example, 20 cycles, the access time of the LBS of the other CPU is, for example, 10 cycles, and the LBS of the other CPU is invalidated or It is assumed that the state change takes, for example, 5 cycles.

The processor (CPU1) 1a acquires the lock in advance (executes the above instruction ,,,) and the processor (CP
U2) 1b also tries to acquire the lock, and the above CS
An exclusive read is performed by executing an instruction (execution of the above instructions ,,), but since it already exists in the LBS 10 of the processor (CPU1) 1a in the exclusive state (E = 1), in the case of the present invention, the processor is used. (CPU1) Sharing the block of LBS 10 of 1a
As (E = 0), the data of the block of the processor (CPU1) 1a is transferred to the LBS 10 of the processor (CPU2) 1b and registered in the shared state (E = 0). {Processing steps 100, 10 in FIG. 1
See 1,104,106} The lock has already been taken by the processor (CPU1) 1a, and the CS instruction uses the condition code (CC
= 1: Lock acquisition failure), the label “LOOP” is returned to the above instruction sequence, and the CS instruction is executed again.

The processor (CPU1) 1a uses its own L as a subsequent instruction.
After reading BS 10, I try to rewrite it with an instruction,
Since the block is in the shared state (E = 0) {that is, write added}, the block of the LBS 10 of the processor (CPU2) 1b is invalidated, and the write block of its own LBS 10 is set to the exclusive state before writing. To do. {Processing steps in FIG. 1
110,111,112,113} The processor (CPU2) 1b has the LBS 10 block of the processor (CPU1) 1a because the block of its own LBS 10 is invalidated when the second CS instruction is executed.
From the same as above. That is, the processor (CPU1) 1a
Data transfer is performed by moving out from LBS 10 of.

However, since the lock has not been released, the CS command is executed again by the condition code (CC =
(1: Lock acquisition failure) ends. Finally, the processor (C
PU1) 1a tries to rewrite the lock word to release the lock, but since the block is in the shared state,
Disable the block of processor (CPU2) 1b, and set its own LBS
The block is put in the exclusive state and writing for releasing the lock is performed.

When the processor (CPU2) 1b again reads the lock word by the CS instruction (resulting in data transfer), the lock can be acquired this time, and the CS instruction receives the normal condition code (CC = 0: lock). Acquire) ends.

As described above, according to the present invention, the processor (CPU1) 1a, which has acquired the lock, releases the lock until the processor (CPU2) 1b executes the CS instruction for acquiring the lock. Data transfer does not occur from the LBS 10 of the CPU2) 1a to the LBS 10 of the processor (CPU1) 1b, and the execution time of the processor (CPU1) 1a that has acquired the lock can be shortened.

The effect of shortening the execution time of the processor (CPU1) 1a is that the difference increases exponentially as the number of CPUs waiting for the lock increases. As described above, the buffer memory control method according to the present invention is provided with a plurality of processors.
(CPU) 1, buffer memory controlled by swap method
In an information processing device equipped with (LBS) 10, when performing exclusive read of an exclusive area including a lock word with a CS instruction, if the corresponding block does not exist in its own buffer memory (LBS) 10, Change the holding state of the buffer memory (LBS) 10 of another existing processor (CPU) 1 from the exclusive state (E = 1) to the shared state (E = 0) and share it with its own buffer memory (LBS) 10. When the area containing the lock word existing in the buffer memory (LBS) 10 of the other processor (CPU) 10 is rewritten, the area is updated to the exclusive area and the CS instruction is issued. The feature is that data transfer is caused at the next exclusive read.

[0033]

As described above in detail, the buffer memory control system of the present invention is provided with a plurality of processors (CPUs).
In addition, in an information processing device that has a buffer memory (LBS) that is controlled by the swap method, when performing an exclusive read of the exclusive area including the lock word with the CS instruction, the corresponding block becomes its own buffer memory (LBS). When it does not exist, the holding state of other processors (CPU) is changed from the exclusive state (E = 1) to the shared state (E = 0), and its own buffer memory (L
BS) in a shared state, and when the area containing the lock word existing in the buffer memory (LBS) of the other processor (CPU) is rewritten, the area in the shared state is updated to the exclusive state. , The data transfer is caused at the next exclusive read by the CS instruction.
When there is a CPU waiting for the release of the lock word, the execution time of the CPU acquiring the lock word can be reduced, and the processing performance of the multiple processors can be improved.

[Brief description of drawings]

FIG. 1 is a diagram (1) showing a flow chart of an embodiment of the present invention.

FIG. 2 is a flowchart showing an embodiment of the present invention (part 2).

FIG. 3 is a diagram explaining a conventional buffer memory control method (No. 1).

FIG. 4 is a diagram for explaining a conventional buffer memory control system (part 2).

FIG. 5 is a diagram explaining a conventional buffer memory control method (No. 3).

FIG. 6 is a diagram for explaining a conventional buffer memory control system (part 4).

[Explanation of symbols]

1 Central processing unit (CPU0, CPU1, to CPUn) 1a Central processing unit (CPU0), 1b Central processing unit (CPU1) 10 Buffer memory (LBS) 11 Tag memory (TAG) 2 Main memory control unit (MCU) 3 Main memory Unit (MSU) 100 to 108,110 to 113 Processing step V Effective bit E flag
(Shared / exclusive)

Claims (1)

[Claims] 1. A buffer memory (LBS) in an information processing device comprising a plurality of processors (CPU) (1a, 1b, ...) and a buffer memory (LBS) (10) controlled by a swap method.
The block in (10) is a rewritten block,
Alternatively, there is a “exclusive” (E = 1) state that indicates that the block has been read for rewriting and a “shared” (E = 0) state that indicates that the block has been read for only reading. It is a buffer memory device which controls on the basis of the two states, and a block in the buffer memory (LBS) (10) of a processor (CPU) (1a) is rewritten by the processor (CPU) (1a). If a processor (CPU) (1a) other than the processor (CPU) (1a) has a certain value (all "0") in the block, the block is read. If the block of the buffer memory (LBS) (10) of the processor (CPU) (1a) is in the exclusive state when it is executed, the block is changed from the exclusive state (E = 1) to the shared state (E = (0) and
A signal indicating that the exclusion process has failed is transmitted to the processor (CPU) (1b) requesting the exclusive read together with the read data, and the buffer memory (LBS) in the request processor (CPU) (1b) is transmitted. ) (10) is also registered in the shared state, and if it is held in the shared state in the buffer memory (LBS) (10) in the request processor (CPU) (1b), it is read as it is and the processor ( CPU (1a) buffer memory (LBS) (10) only when the write occurs in the block, the processor (CPU) (1
A buffer memory control method in which the block of a) is placed in an exclusive state (E = 1).