JPH0540667A - Abnormality detecting method for main processor and firmware runaway preventing method for i/o processor - Google Patents

Abstract

PURPOSE:To realize a method to prevent the runaway of an I/O processor by providing plural I/O processors separately from a main processor and surely detecting the abnormality of the main processor in an abnormality preventing method for communication equipment which performs communication line control by firmware. CONSTITUTION:The communication equipment consisting of the main processor 100 and a communication adaptor 200 is constituted so as to detect the abnormality of the main processor 100 by providing a decision means 240 which decides whether or not data transfer between buffer memory 230 in the communication adaptor 200 and main memory 120 in the main processor 100 can be performed, and deciding whether or not direct memory access between the buffer memory 230 and the main memory 120 can be performed by the decision means 240 when the transfer of data between the communication adaptor 230 and a counter device 300 is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of detecting an abnormality in a communication device in which a plurality of I / O processors other than a main processor are provided and line control is performed by firmware.

For example, in a node device that constitutes a packet switching network and a device that collects and distributes data, it is necessary to reduce the load on the main processor in order to improve the processing capability of the device. Therefore, a method of providing a plurality of I / O processors in the device and controlling with firmware is widely adopted. The communication procedure may differ depending on the type of the opposite device.
By being absorbed by the O processor and the firmware, communication is performed independently of the main processor.

In such an apparatus including a plurality of I / O processors other than the main processor, when the main processor has an abnormality, the abnormality is surely detected and the abnormality detection of the main processor is notified to the opposite device. A method is required.

[0004]

2. Description of the Related Art FIG. 4 shows a block diagram for explaining a conventional example. In the figure, 100 is a main processor including a microprocessor 110, a main memory 120, and a direct memory access controller (hereinafter referred to as DMAC) 130, 200A is a communication adapter including an I / O processor 210, firmware 220, and buffer memory 230, and 300 is Line control unit 310, buffer memory 320
It is an opposite device with.

In the figure, for example, when data is transmitted from the opposite device 300 to the communication adapter 200A, the opposite device 300 sends the data in the buffer memory 320 through the line control unit 310, and the communication adapter 200A.
On the side, the received packet is written in the buffer memory 230 via the I / O processor 210 controlled by the firmware 220.

Next, the packet written in the buffer memory 230 is controlled by the DMAC 130 and transferred to and written in the main memory 120. In this configuration, the I / O processor 210 is the microprocessor 1
It communicates with the opposite device 300 independently of the I / O device 10, and unless I / O is cut off or a reset signal is input, I / O
The processor 210 continues to operate independently.

Further, the I / O processor 210 is generally configured to be connected to a plurality of opposed devices 300 to perform parallel processing. Device 30
A buffer memory 230 is provided in the I / O processor 210 so that the transmission / reception timing with 0 is not brought into the processing of the processor 110. Therefore, data can be received from the opposite device 300 as long as the buffer memory 230 has a free space, and data can be transmitted to the opposite device 300 as long as there is data to be transmitted in the buffer memory 230.

[0008]

In the above-mentioned conventional example, an abnormality occurs in the microprocessor 110, and data is transferred from the buffer memory 230 in the communication adapter 200A to the main memory 120 in the main processor 100. Buffer memory 230
If there is a vacancy, the link level is normal, data is received, and the firmware 220 runs out of control.

Data transfer from the communication adapter 200A to the main processor 100 is generally performed in a direct memory access mode (hereinafter referred to as a DMA mode), and transfer of received data from a plurality of opposite devices 300 is performed in parallel. Therefore, it is difficult to associate with the opposite device 300 that is executing transmission / reception.

As described above, although the main processor 100 becomes abnormal and the data to be exchanged, collected and distributed, etc. is not delivered to the main processor 100, the opposite device 300 can transfer data to and from the communication adapter 200A. Since transmission / reception is possible, it is determined that transmission / reception has been completed normally.

Therefore, in such a case, the data backup required and the line switching required in the duplex system are not performed, and the reliability of the data is lowered.

Further, even if the higher level recovery is performed, it takes time, so that it is not sufficient in the case of a network or a device which requires a high response. The present invention intends to realize a method for surely detecting an abnormality of a main processor and preventing runaway of an I / O processor.

[0013]

FIG. 1 is a block diagram for explaining the principle of the present invention. Reference numeral 100 in the figure denotes a microprocessor 110, a main memory 120, and a DMAC 13.
0 is a main processor, and 200 is a communication adapter having an I / O processor 210, firmware 220, and a buffer memory 230.

Reference numeral 240 is a determination means for determining whether or not data transfer in the DMA mode is possible between the buffer memory 230 in the communication adapter 200 and the main memory 120 in the main processor 100. The main processor 200 determines whether or not direct memory access (hereinafter, referred to as DMA) is possible between the buffer memory 230 and the main memory 120 when the device 200 transmits / receives data to / from the opposite device 300. Detect 100 abnormalities.

Further, the communication adapter 200 is used as the opposite device 3.
Buffer memory 23 when transmitting / receiving data to / from 00
0 and the main memory 120 determines whether or not data transfer in the DMA mode is possible by the determination means 240, and D
If MA is possible, data transmission / reception is performed, and if DMA is not possible, the opposite device 300 is instructed to stop data transmission.

[0016]

Operation: Main processor 100 and communication adapter 200
There are the following types of data transmission and reception to and from.

Transmission data (main processor → communication adapter) Transmission completion notification (main processor ← communication adapter) Reception data (main processor ← communication adapter) Abnormality occurrence notification (main processor ← communication adapter) Communication adapter error, procedure error, etc. Line control Instruction (main processor → communication adapter) Open / close instruction When there is an abnormality in the main processor 100, there is no possibility of abnormality. Therefore, abnormality detection is detected by whether or not DMA transfer can be performed normally.

When an abnormality in the DMA mode transfer is detected, the buffer memory 230 is set to the busy state,
Abnormal termination is made by notifying the opposing device 300.
With the above operation, it becomes possible to reliably detect the abnormality of the main processor 100.
When an abnormality of 0 is detected, it is possible to notify the opposite device 300 of the abnormality and surely terminate the abnormality.

[0019]

FIG. 2 is a flowchart of an embodiment of the present invention. The operation of the present invention will be described with reference to a flowchart.

Communication adapter 200 and opposite device 300
Set up the line with. The determination means 240 determines whether or not DMA mode transfer is possible between the main memory 120 and the buffer memory 230.

In the case where the DMA mode transfer is not permitted, the main processor 100 is in an abnormal state, and therefore the opposite device 300 is instructed to stop the data transmission. If the DMA mode transfer is possible, the data is received from the opposite device 300 and the buffer memory 230
Write in.

Next, the data written in the buffer memory 230 is transferred to the main memory 120 in the DMA mode. Buffer memory 2 that receives and transfers a series of data
When the content of 30 is lost, the reception data ends. When there is subsequent data, the process returns to, and if DMA mode transfer is possible, the next data from the opposite device 300 is received and the buffer memory 230 Write in.

FIG. 3 is a diagram for explaining the line control system according to the embodiment of the present invention. Communication adapter 200 and opposite device 300
The communication procedure with HDLC (High-l
evelData Link Control Procedure) is described as an example.

(A) shows a normal state. The figure shows the operation centering on the communication adapter 200. Reception means reception of data (I packet, shown as I in the figure) from the opposite device 300, and main transfer is written in the buffer memory 230. The data is transferred to the main memory 120 under the control of the DMAC 130.

In this case, the main transfer is normal (OK in the figure).
Is shown), the positive response RR (Receive Ready) which permits the transmission of the next data to the opposite device 300.
Send a signal.

(B) shows an abnormal state (NG in main transfer). A case is shown in which the data received from the opposite device 300 is attempted to be transferred to the main memory 120 under the control of the DMAC 130, but the transfer is impossible. At this time, the next data is transmitted to the opposite device 300. A negative response RNR (Receive Not Ready) signal for instructing stop is transmitted. The RNR signal appears as busy in the buffer memory 230 of the communication adapter 200 when viewed from the opposite device 300.

(C) shows an abnormal state (already detected abnormality).
When it is detected that the DMA mode transfer cannot be performed at the previous transfer of the I packet, the I packet is received and written in the buffer memory 230 in this operation, but the abnormality of the DMA mode transfer is already detected. Therefore, the I packet of this time is not transferred to the main memory 120, and the RNR signal is sent to the opposite device 300 when the I packet is received.

If an abnormality is detected during data transmission, the data is replaced with an abort pattern and transmitted,
The received data is invalidated on the communication adapter 200 side. Therefore, the abnormality of the main processor 100 can be reliably detected and notified to the opposite device 300.
The runaway of the firmware 220 of the O processor 210 can be prevented, and the data after the abnormality is backed up on the opposite device 300 side, so that the reliable recovery can be performed.

[0029]

When transmitting / receiving data between the communication adapter and the opposite device, it is possible to detect the abnormality of the main processor by detecting whether or not the DMA mode transfer between the buffer memory of the communication adapter and the main memory of the main processor is possible. When the abnormality of the main processor is detected, the abnormality information can be accurately notified to the opposite device, and the opposite device can perform quick and reliable recovery.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a flowchart of an embodiment of the present invention.

FIG. 3 is a diagram illustrating a line control system according to an embodiment of the present invention.

FIG. 4 is a block diagram illustrating a conventional example.

[Explanation of symbols]

 100 Main Processor 110 Processor 120 Main Memory 130 DMAC 200, 200A Communication Adapter 210 I / O Processor 220 Firmware 230, 320 Buffer Memory 240 Judgment Unit 300 Opposed Device 310 Line Control Unit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G06F 13/28 310 L 7052-5B H04L 12/56

Claims (2)

[Claims] 1. A main processor (10) comprising a microprocessor (110), a main memory (120) and a direct memory access controller (130).
0), I / O processor (210), and firmware (22
0) and a communication adapter (200) including a buffer memory (230), the buffer memory (230) in the communication adapter (200) and the main memory () in the main processor (100). 120) is provided with a determination means (240) for determining whether or not data transfer in the direct memory access mode is possible, and when the communication adapter (200) transmits / receives data to / from the opposite device (300), Buffer memory (23
0) and the main memory (120) whether or not direct memory access is possible, the judging means (240)
The main processor (10
0) The abnormality detection method of the main processor which detects the abnormality. 2. A data transfer in a direct memory access mode between the buffer memory (230) and the main memory (120) when the communication adapter (200) sends and receives data to and from the opposite device (300). Is determined by the determination means (240),
When direct memory access is possible, data transmission / reception is performed, and when direct memory access is not possible, the opposite device (300) is instructed to stop data transmission. Firmware runaway prevention method.