JPH0537598A - Fault signal detection circuit - Google Patents

Abstract

PURPOSE:To decrease number of gates of an LSI and to reduce the cost by using one detection release protection circuit so as to detect/release a fault detection signal in 3 protection stages independently of the mode. CONSTITUTION:A mode selection means 6 selects a 1st AIS release code detection means 4 in the normal mode and outputs it to a detection release selection means 3. On the other hand, in the case of the concatenation mode, the means 6 outputs an output of a 2nd AIS release code detection means 5 to the means 3. The means 3 selects an output of the AIS detection code detection means 2 or an output of the means 6 and sends it to a detection release protection means 7. The means 7 outputs a detection signal when a detection code from the means 3 is consecutive thrice and outputs a release signal when the release code is consecutive thrice and it is sent to a detection release detection means 8. The means 8 outputs AIS when the means 8 receives the detection signal and when the means 8 receives a release signal, the AIS is released. Thus, number of gates of the LSI is decreased and the cost is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal detection circuit for informing a failure detection in a digital transmission system. More specifically, it is a wide band IS which is a digital transmission system.
The present invention relates to a detection circuit for an AIS (Alarm Indication Signal) that notifies a failure detection in a terminal device that controls information transmission based on a standard of SONET (Synchronous Optical NETwork) as a DN.

[0002]

2. Description of the Related Art In SONET, which is a digital transmission system, AIS means that a terminal device that detects a failure in a transmission path sends bits in a frame as all marks to an upper or lower terminal device, It is a signal for notifying a failure in the terminal device of the lower group.

For example, FIG. 1 is a schematic diagram showing a configuration example of a network of a digital transmission system targeted by the present invention. Lower group terminal equipment LS as shown in FIG.
1, an upper group terminal station device US1, a higher group terminal station device US2,
It is assumed that the line between the lower group terminal station device LS1 and the upper group terminal station device US1 fails in a network in which the lower group terminal station device LS2 is sequentially connected in series. In this case, the higher-order upper group terminal station device US1 detects the failure and
Send IS. This AIS is received by the other upper group terminal station device US2, and the upper group terminal station device US2 detects the AIS and transmits the AIS to the lower group terminal station device LS2. To detect.

FIG. 2 is a schematic diagram showing the structure of a SONET STS-12 (12 multiplexed) frame format. One frame is composed of 1080 bytes (90 bytes x 12 multiplex) x 9 lines. The overhead part is a header for data for frame sync signal or various auxiliary signal transmission, and a payload part for information signal transmission. It is divided into The frame repetition period, that is, one frame period
125 μs.

A frame synchronization signal,
It includes all the various signals required for the transmission of multiple signals such as error monitoring code, channel identification signal, maintenance channel, and alarm signal. Taking the first line of the frame as an example, the overhead bytes A1, A2, and C1 each consist of 12 bytes # 1 to # 12 corresponding to 12 multiplexes, and each byte consists of 8 bits. ing. The overhead bytes H1 and H2 in the fourth row are all-marked bytes when AIS is detected.

The present invention relates to a detection circuit for an AIS sent from a subordinate terminal device (Path level) in such a SONET STS-N (N is a multiplexing number and 1 to ∞) frame format.

In the two modes, it is general that the number of protection stages is set to multiple in order to detect and cancel AIS. For example, if the number of protection stages is three, the conventional technique requires three protection circuits for each of the two-mode detection and cancellation circuits. However, if such a detection and release circuit requires a three-stage protection circuit, the number of gates of the LSIs that make up the device will become enormous, thus increasing the power consumption. It becomes difficult to incorporate the function of, and the cost naturally increases.

FIG. 3 is a block diagram showing a conventional configuration of an AIS detection circuit. It shows a configuration in which the number of protection stages is 3 for both detection and cancellation, and the detection codes for the two modes are the same and the cancellation codes are different. Shows.

In FIG. 3, reference numeral 11 is an H1, H2 byte latch for latching the above-mentioned H1, H2 byte data DATA extracted from each frame of the input signal. this
The H1 and H2 byte data latched by the H1 and H2 byte latch 11 are applied to one input terminal of each of the two-input AND gates 12 and 13.

The mode signal MODE is directly input to the other input terminal of the AND gate 12, and the output is given to the first AIS code detector 14. The mode signal MODE is inverted and input to the other input terminal of the AND gate 13, and the output is given to the second AIS code detector 15.

The mode signal MODE indicates a normal mode when the value is "1" and a concatenation mode when the value is "0".

By the way, in the normal mode, the mode signal MO
Since DE is “1”, the H1 and H2 byte data latched by the H1 and H2 byte latch 11 is given to the first AIS code detector 14 through the AND gate 12, but in concatenation mode, the mode signal MODE Is "0", so H1,
H1 and H2 byte data latched in H2 byte is AN
It is provided to the second AIS code detector 15 via the D gate 13.

The outputs of both AIS code detectors 14 and 15 are input to detection / release protection circuits 21 and 22 having the same configuration.

The configuration of both detection / release protection circuits 21 and 22 will be described by taking the first detection / release protection circuit 21 to which the output of the first AIS code detector 14 is input as an example.

The output of the first AIS code detector 14 is input to the D terminal of the first D flip-flop 31. The Q terminal of the first D flip-flop 31 is connected to the D terminal of the second D flip-flop 32 and the first input terminal of the 3-input AND gate 34 and is an inverting output terminal.
The #Q terminal is connected to the first input terminal of the 3-input AND gate 35. Further, the Q terminal of the second D flip-flop 32 is connected to the D terminal of the third D flip-flop 33 and the 3-input terminal.
It is connected to the second input terminal of the AND gate 34, and the #Q terminal is connected to the second input terminal of the AND gate 35.
The Q terminal of the third D flip-flop 33 is connected to the third input terminal of the AND gate 34, and the #Q terminal is A
It is connected to the third input terminal of the ND gate 35. Also,
The output of the AND gate 34 is connected to the S terminal of the SR flip-flop 36, and the output of the AND gate 35 is connected to the R terminal of the SR flip-flop 36.

Incidentally, the C clock of each D flip-flop 31, 32, 33 is supplied with a protection clock CK having a period of 125 μs, that is, one frame period.

Therefore, H1 and H2 latched by the H1 and H2 byte latches 11 over three consecutive clocks of the protection clock.
If the byte contains AIS, in other words, if the H1 and H2 bytes contain AIS for 3 consecutive frames, it is detected by the first AIS code detector 14, and at the first clock. Q is taken into the first D flip-flop 31
The signal "1" is output from the terminal and the first signal is output at the second clock.
Signal "1" output from D flip-flop 31
Is taken into the second D flip-flop 32, a signal "1" is output from its Q terminal, and the second D flip-flop 32 outputs the second D
The signal "1" output from the flip-flop 32 is taken into the third D flip-flop 33, and the signal "1" is output from the Q terminal thereof. 3 D flip-flops 3
The outputs of the Q terminals of 1, 32, and 33 are all "1", and the output of the AND gate 34 is also "1", so the SR flip-flop 36
Is set and its set output "1" is output as AIS.

On the other hand, since the first AIS code detector 14 outputs the signal "0" when detecting the release code, it is latched in the H1 and H2 byte latches 11 for three consecutive clocks of the protection clock. If the generated H1 and H2 bytes do not include AIS, in other words, if the H1 and H2 bytes do not include AIS in three consecutive frames, the first AIS code detector
Since 14 detects the AIS cancellation code, all the #Q terminal outputs of each D flip-flop 31, 32, 33 become "1", and AND
The output of the gate 35 also becomes "1" and the SR flip-flop 36
Is reset. That is, AIS is released.

The above-described configuration and operation are the same in the second AIS code detector 15 and the second detection / release protection circuit 22 connected to the AND gate 13.

[0020]

By the way, the conventional AIS detection circuit as described above is provided with a separate detection / release protection circuit for each of the two modes. The number of protection steps is 3
It is composed of steps. For this reason, as mentioned above, the number of gates of the LSIs that make up the device becomes enormous, and therefore the power consumption increases, but on the other hand, it becomes difficult to incorporate other functions on the LSIs, and the cost naturally increases. There is a problem.

The present invention has been made in view of the above circumstances, and one detection / release protection circuit can detect and release AIS with three protection stages regardless of the mode. It is an object of the present invention to provide an AIS detection circuit that solves the above problems.

[0022]

FIG. 4 is a block diagram showing the principle configuration of the AIS detection circuit of the present invention, in which the number of protection stages is 3 stages for both detection and cancellation, and the detection codes for two modes are the same and cancelled. The configuration when the codes are different is shown.

In FIG. 4, reference numeral 1 is the aforementioned 8-bit H1 extracted from each frame of the input signal.
H1 and H2 byte latch means for latching H2 byte data DATA. The 16-bit data of the H1 and H2 bytes latched by the H1 and H2 byte latch means 1 is the AIS detection code detection means 2, the first AIS cancellation code detection means 4 and the second AI.
Each is given to the S release code detecting means 5.

The AIS detection code detecting means 2 converts the H1 and H2 byte data supplied from the H1 and H2 byte latching means 1 into data.
If the AIS is included, the signal "1" is output, and if it is not included, the signal "0" is output. The signal output from the AIS detection code detection means 2 is the detection / cancellation selection means 3
Has been entered in.

On the other hand, the first AIS cancellation code detecting means 4 is
If the H1 and H2 byte data provided from the H1 and H2 byte latching means 1 includes the AIS cancel code in the normal mode which is the first mode, the signal "0" is output and the second AIS cancel code detecting means. Reference numeral 5 outputs a signal "1" if the H1 and H2 byte data provided from the H1 and H2 byte latch means 1 includes the AIS cancellation code in the concatenation mode which is the second mode. Both AIS release code detecting means 4, 5
The signal output from is input to the mode selection means 6.

The mode signal MODE indicates a normal mode when the value is "1" and a concatenation mode when the value is "0".

By the way, in the normal mode, the mode signal MO
Since DE is "1", the mode selection means 6 selects the output of the first AIS release code detection means 4 and outputs it to the detection / release selection means 3, while the mode signal MO in the concatenation mode.
Since DE is "0", the mode selection means 6 selects the output of the second AIS cancellation code detection means 5 and outputs it to the detection / cancellation selection means 3.

The detection / release selection means 3 outputs the output of the AIS detection code detection means 2 when "0" is given as the select signal SE, and the mode selection means 6 when "1" is given. Are selected and applied to the detection / release protection means 7 together.

The detection / cancellation protection means 7 has a three-step protection function, and the AIS provided from the detection / cancellation selection means 3 is provided.
Detection signal when the detection code is input three times in a row
1 "is output and is given from the detection / cancellation selection means 3
When the IS cancellation code is input three times in succession, the cancellation signal "1" is output. Both signals output from the detection / release detection means 7 are given to the detection / release detection means 8,
The detection / release detection means 8 outputs AIS by setting the output signal to "1" when the detection signal is given,
When the release signal is given, the output signal is set to "0" to release the output AIS.

The output signal of the detection / release detection means 8 is the select signal SE of the detection / release selection means 3 described above.

[0031]

The operation of the principle configuration of the AIS detection circuit of the present invention as described above is as follows.

H1, H2 Byte latched by means 1
The H1 and H2 byte data are given to the AIS detection code detecting means 2, the first AIS cancellation code detecting means 4 and the second AIS cancellation code detecting means 5, respectively. When the H1 and H2 byte data latched by the H1 and H2 byte latch means 1 contains the AIS detection code, the output signal of the AIS detection code detecting means 2 is set to "1", and the first mode is set. If the AIS cancellation code in the normal mode is included, the output signal of the first AIS cancellation code detecting means 4 is "1", and the AIS cancellation code in the concatenation mode which is the second mode is included. In this case, the output signal of the second AIS cancellation code detecting means 5 becomes "1".

By the way, assuming that the AIS is released, in other words, the output signal of the detection / release detection means 8 is "
If it is "0", the select signal SE given to the detection / cancellation selecting means 3 is "0", so that the detection / cancellation detecting means 8 selects the output signal of the AIS detection code detecting means 2. In this state, if the H1 and H2 bytes latched by the H1 and H2 byte latching means 1 contain an AIS detection code, it is detected by the AIS detection code detecting means 2 and detected by the detection / cancellation selecting means 3.・ Release protection means 7
Given to. This state is the protection clock 3 not shown.
When continuing over the clock, the detection / release protection means 7 outputs the detection signal "1" to the detection / release detection means 8.
And As a result, the detection / release detection means 8 outputs AIS by setting its output signal to "1".

On the other hand, if AIS is being output now, in other words, the output signal of the detection / release detection means 8 is "
If it is "1", the selection signal SE given to the detection / release selection means 3 is "1", so that the detection / release detection means 8 selects the output signal of the mode selection means 6. Further, assuming that the normal mode is set, the mode signal MODE given to the mode selection means 6
Is "1", the mode selection means 6 selects the output signal of the first AIS cancellation code detection means 4 and outputs it to the detection / cancellation selection means 3. In this state, if the H1 and H2 bytes latched by the H1 and H2 byte latching means 1 contain the AIS cancel code in the normal mode, it is detected by the first AIS cancel code detecting means 4 and the mode selecting means. 6 and the detection / cancellation selection means 3 to the detection / cancellation protection means 7. When this state continues for 3 clocks of the protection clock (not shown), the detection / release protection means 7 detects
The release signal output to the release detecting means 8 is set to "1". As a result, the detection / release detection means 8 sets the output signal to "0" to release the AIS.

If the concatenation mode is set, the mode signal given to the mode selecting means 6 is given.
Since MODE is "0", the mode selection means 6 is the second AIS.
The output signal of the release code detection means 5 is selected and output to the detection / release selection means 3. In this state, if the H1 and H2 bytes latched by the H1 and H2 byte latching means 1 include the AIS cancellation code in the concatenation mode, the second AIS cancellation code detecting means 5 detects it and the mode selecting means 6
And the detection / cancellation protection means 7 through the detection / cancellation selection means 3. When this state continues for 3 clocks of the protection clock not shown, the detection / release protection means 7
Is the release signal output to the detection / release detection means 8.
As a result, the detection / release detection means 8 sets its output signal to "0" to release the AIS.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments.

FIG. 5 is a block diagram showing the configuration of an embodiment of the AIS detection circuit of the present invention, in which the number of protection stages is 3 for both detection and cancellation, and the detection codes for the two modes are the same and the cancellation codes are respectively. The configuration when different is shown.

In FIG. 5, reference numeral 1 is an H1, H2 byte latch 1 as H1, H2 byte latch means, which latches the H1, H2 bytes input as data. This H
H1, H2 byte latched by 1 and H2 byte latch 1 is AI
AIS detection code detector as S detection code detection means 2,
They are provided to a first AIS cancellation code detector 4 as a first AIS cancellation code detecting means and a second AIS cancellation code detector 5 as a second AIS cancellation code detecting means, respectively.

The AIS detection code detector 2 outputs a signal "1" if the H1 and H2 bytes given from the H1 and H2 byte latch 1 contain AIS. The signal output from the AIS detection code detector 2 is input to the detection / cancellation selector 3 as detection / cancellation selection means.

On the other hand, the first AIS cancellation code detector 4 is H
If the H1 and H2 bytes given by the 1 and H2 byte latch 1 contain the AIS cancellation code in the normal mode which is the first mode, the signal "1" is output, and the second AIS cancellation code detector 5 If the H1 and H2 bytes given from the H1 and H2 byte latch 1 contain the AIS cancel code in the concatenation mode which is the second mode, the signal "1" is output. The signals output from both AIS cancellation code detectors 4 and 5 are input to a mode selector 6 as a mode selection means.

The mode signal MODE indicates a normal mode when the value is "1" and a concatenation mode when the value is "0".

By the way, in the normal mode, the mode signal MO
Since DE is "1", the mode selector 6 selects the output of the first AIS cancellation code detector 4 and outputs it to the detection / cancellation selector 3. On the other hand, in the concatenation mode, the mode signal MODE
Is "0", the mode selector 6 selects the output of the second AIS cancellation code detector 5 to detect and cancel the selector 3.
Output to.

The detection / cancellation selector 3 selects the output of the AIS detection code detector 2 when "0" is given as the select signal SE, and the mode selector when the same is given "1". The outputs of 6 are selected and given to the detection / release protection circuit 7 as detection / release protection means.

The detection / cancellation protection circuit 7 has a three-stage protection function, and the AIS supplied from the detection / cancellation selector 3
Detection signal when the detection code is input three times in a row
1 ”is output and is given from the detection / release selector 3 A
When the IS cancellation code is input three times in succession, the cancellation signal "1" is output.

The detection / release protection circuit 7 is provided with three stages of D flip-flops 71, 72, 73 and two AND gates 74, 75, and its concrete configuration is as follows.

The output of the detection / cancellation selector 3 is input to the D terminal of the first D flip-flop 71. The Q terminal of the first D flip-flop 71 is the D terminal of the second D flip-flop 72 and the first of the three-input AND gates 74.
The #Q terminal, which is the inverting output terminal, is connected to the first input terminal of the 3-input AND gate 75. Further, the Q terminal of the second D flip-flop 72 is the AND terminal of the D terminal of the third D flip-flop 73 and the three inputs.
It is connected to the second input terminal of gate 74, and the #Q terminal is
It is connected to the second input terminal of the AND gate 75. The Q terminal of the third D flip-flop 73 is an AND gate
It is connected to the third input terminal of 74, and the #Q terminal is connected to the third input terminal of AND gate 75. Also, AND
The output of the gate 74 is connected to the S terminal of the SR flip-flop 8 as the detection / release detection means, and the output of the AND gate 75 is connected to the R terminal of the SR flip-flop 8.

The D flip-flops 71, 72, 73 are supplied at their C terminals with 125 μs, that is, a protection clock PCK having one frame cycle as one cycle.

Therefore, the detection / release selector 3 detects / detects
Each time the signal “1” is input to the release protection circuit 7, it is taken into the first D flip-flop 71 at the first clock and the signal “1” is output from its Q terminal, and at the second clock, the signal “1” is output. Signal output from D flip-flop 71 of 1 "
1 "is taken into the second D flip-flop 72 and its Q
The signal "1" is output from the terminal and the second signal is output at the third clock.
Signal "1" output from the D flip-flop 72 of
Is taken into the third D flip-flop 73, and the signal "1" is output from its Q terminal. Therefore, if the signal "1" is input to the detection / release protection circuit 7 over three consecutive protection clocks, three D flip-flops 7 are provided.
The outputs of the Q terminals of 1, 72, 73 are all "1", and the output of the AND gate 74 is also "1", so the SR flip-flop 8
Is set and its set output "1" is output as AIS.

On the other hand, the signal "0" is detected from the detection / cancellation selector 3 over three consecutive clocks of the protection clock.
If input to the release protection circuit 7, each D flip-flop
71Q, 72Q, and 73QQ output are all "1", and AND gate
The output of 75 also becomes "1" and the SR flip-flop 8 is reset. That is, AIS is released.

Both signals output from the detection / release protection circuit 7 are applied to the SR flip-flop 8. The SR flip-flop 8 sets the output signal to "1" when the detection signal is applied. AIS is output by, and when the release signal is given, the output AIS is released by setting the output signal to "0".

The output signal of the SR flip-flop 8 is the select signal SE of the detection / cancellation selector 3 described above.

The operation of one embodiment of the AIS detection circuit of the present invention having such a configuration is as follows. 6 is a timing chart for explaining the operation.

H1, H2 H1, latched by byte latch 1
The H2 byte is given to the AIS detection code detector 2, the first AIS cancellation code detector 4 and the second AIS cancellation code detector 5, respectively. When the H1 and H2 bytes latched by the H1 and H2 byte latch 1 contain the AIS detection code shown in Fig. 6 (a), the output signal of the AIS detection code detector 2 is " When 1 ”includes the AIS cancellation code in the normal mode which is the first mode, the output signal of the first AIS cancellation code detector 4 is set to“ 1 ”and AIS cancellation in the concatenation mode which is the second mode When the code is included, the output signal of the second AIS cancellation code detector 5 becomes "1".

By the way, if the AIS is released now, in other words, the output signal of the SR flip-flop 8 is "
If it is "0", the select signal SE given to the detection / cancellation selector 3 is "0", so the SR flip-flop 8 selects the output signal of the AIS detection code detector 2. Then, if the H1 and H2 bytes latched by H1 and H2 byte latch 1 contain the AIS detection code,
It is detected and detected by the AIS detection code detector 2.
It is given to the detection / release protection circuit 7 through the release selector 3. If this state continues for three clocks of the protection clock PCK (not shown), as shown in FIGS. 6 (d), (e), (f), the Q of each D flip-flop 71, 72, 73 is Since all the terminal outputs become "1", the output of the AND gate 74 also becomes "1" as shown in FIG. 6 (g). As a result, the SR flip-flop 8 is set and its output signal,
That is, the AIS detection result shown in FIG. 6 (c) becomes "1" and AIS is detected.

On the other hand, assuming that the AIS is being output as described above, in other words, if the output signal of the SR flip-flop 8 is "1", the select signal given to the detection / cancellation selector 3 is selected. Since the signal SE is "1", the SR flip-flop 8 selects the output signal of the mode selector 6. Further, assuming that the normal mode is set, the mode selector 6 selects the output signal of the first AIS cancellation code detector 4 because the mode signal MODE given to the mode selector 6 is "1". Output to the detection / cancellation selector 3. In this state, if the H1 and H2 bytes latched by the H1 and H2 byte latch 1 contain the AIS release code in the normal mode as shown in Fig. 6 (a), it is the first AIS release code. It is detected by the code detector 4 and given to the detection / release protection circuit 7 through the mode selector 6 and the detection / release selector 3. If this state continues for three clocks of the protection clock PCK (not shown), as shown in FIGS. 6 (h), (i), and (j), each D flip-flop 71, 72, 73 All Q terminal outputs ”
Since it becomes 1 ", the output of the AND gate 75 also becomes" 1 "as shown in Fig. 6 (k). This resets the SR flip-flop 8 and its output signal, that is, Fig. 6 (c).
The AIS detection result shown in is 0 and the AIS is released.

If the concatenation mode is set, the mode signal given to the mode selector 6
Since MODE is "0", the mode selector 6 is the second AIS
The output signal of the release code detector 5 is selected and output to the detection / release selector 3. In this state, the H1 and H2 bytes latched by H1 and H2 bytes are AIS in concatenation mode.
When the release code is included, it is detected by the second AIS release code detector 5 and given to the detection / release protection circuit 7 through the mode selector 6 and the detection / release selector 3. The following operation is the same as the operation in the normal mode described above.

[0057]

As described above in detail, according to the present invention, one detection / release protection circuit can detect and release AIS with three protection stages regardless of the mode.
It is possible to reduce the number of gates of the LSI that configures the device, so that it is possible to incorporate other functions on the LSI and reduce the cost.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a configuration example of a network of a digital transmission system targeted by the present invention.

FIG. 2 is a schematic diagram showing the structure of a SONET STS-12 (12 multiplexed) frame format.

FIG. 3 is a block diagram showing a conventional configuration of an AIS detection circuit.

FIG. 4 is a block diagram showing a principle configuration of an AIS detection circuit of the present invention.

FIG. 5 is a block diagram showing a configuration of an embodiment of an AIS detection circuit of the present invention.

FIG. 6 is a timing chart for explaining the operation of one embodiment of the AIS detection circuit of the present invention.

[Explanation of symbols]

 2 AIS detection code detector 4 1st AIS release code detector 5 2nd AIS release code detector 6 Mode selection means (mode selector) 7 Detection / release protection means (detection / release protection circuit) 8 Detection / release detection means ( SR flip-flop) AIS Failure notification signal H1, H2 Byte including failure notification signal

Claims (1)

Claims: 1. A failure notification signal that reports the occurrence of a failure specified for each of a plurality of modes is displayed in a specific area (H1, H2) in a predetermined number of consecutive frames of an input signal. When it is included, a failure detection signal (AIS) is output, and the cancellation signal that notifies the cancellation of the failure occurrence specified for each of the multiple modes is a specific area (H1) in a predetermined number of consecutive frames of the input signal. , H2) in the failure notification signal detection circuit that cancels the output of the failure detection signal (AIS), a plurality of signal detections that detect the failure notification signal and the cancellation signal specified for each of the plurality of modes. Means (2, 4, 5) and mode selection means (6) for validating any of the detection results of these signal detecting means (2, 4, 5) according to the mode set at that time, Mode selection means (6) Means (7) for judging whether or not the detection result of the signal detecting means (2, 4, 5) selected by the above-mentioned predetermined number is continuous, and the failure detection signal (according to the judgment result of the means (7) ( (AIS)
A failure notification signal detection circuit, comprising: a detection / cancellation detection means (8) for outputting and releasing.