JPH0536284A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the power consumption without flowing an extra selection bit current by turning ON only the transfer Tr in which the electric potential of a column selecting signal is H out of the 1 whole column of the memory cell circuit selected by a word line. CONSTITUTION:When an electric potential VWL of a word line WL is H and a column selecting signal VYO is H, a Tr 17 is ON, the VWL is impressed to gates G1 and G4 of transfer Tr13 and Tr14 and the Tr13 and 14 are ON. The signal VYO is H and gate Tr18 and Tr19 are also ON. Bit lines BL and BLB and data buses DB and DBB are also conducted, and the data of the memory cell are written and read from the BL and BLB through the DB and DBB. When the VWL is H and the VYO is L, the Tr17 becomes OFF, the Tr13 and 14 are OFF, the Tr18 and 19 are OFF, BL, BLB, DB and DBB are not conducted, and the Tr13 and 14 are discharged to a GND. When the VWL and VYO are L, the electric potential of the gates G1 and G4 of the Tr13 and 14 are also discharged to the GND.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art As a memory cell circuit of a conventional semiconductor memory device, for example, there is a high resistance load type memory cell circuit shown in FIG. 2, in which a potential VWL of a word line WL selected by a row decoder is set. Gate terminals G10 and G of the transfer transistors Tr23 and Tr24 of the memory cell circuit
13 and switches the conduction between the memory cell and the bit lines BL and BLB. The potential VWL of the word line WL is
When the potential VY0 of the column selection signal Y0 is High and the column selection gates Tr27 and Tr28 are in the ON state,
The data of the memory cell is the data from the bit lines BL and BLB.
A write or read operation is performed through the tabas DB and DBB. In addition, the potential VWL of the word line WL is Hi
The potential VY0 of the column selection signal Y0 is Low at gh or Low
At this time, the column selection gates Tr27 and Tr28 are turned off, and the bit lines BL, BLB and the data buses DB, DB.
B had a circuit that was in a non-conductive state.

[0003]

However, in the above-mentioned prior art, the word line WL selected by the row decoder is transferred over the entire memory cell circuit in all memory cell groups or divided memory cell blocks. Turn on the transistor and turn on the column selection signal Y
When the potential VY0 of 0 is High, the column selection gates Tr27, Tr
28 becomes an ON state, selects a memory cell, and a write or read operation is performed from the bit lines BL and BLB through the data buses DB and DBB. Therefore, the transfer transistors of the memory cell circuits which are not selected by the column selection signal Y0 are turned on when the word line WL selects all of the memory cells or one of the divided memory cell blocks.
When the transfer transistor of the memory cell circuit not selected by the column selection signal Y0 is turned on, the conventional circuit shown in FIG. 2 is assumed that the potential at the intersection C is High and the potential at the intersection D is Low. Since the potential at the intersection C is High, the memory cell transistor Tr26 is turned on.
Then, the selected bit line current flows through the path of the power supply VDD, the load transistor Tr22, the transfer transistor Tr24, the memory cell transistor Tr26 and the GND (ground).

Assuming that a block of all memory cells is divided into 16 blocks in a RAM (random access memory) having a capacity of 256 Kbits as shown in FIG. There is a decoder circuit, the m-th column of the block selected by the column selection signal Y0 is selected, and the n-th row selected by the row decoder circuit is selected, whereby one memory is formed. The cell is selected. However, the word line WL selected by the row decoder circuit turns on all the transfer transistors in one column, so that the load transistor Tr22, like the conventional circuit shown in FIG.
The selected bit line current flows through the memory cell circuits of 128 columns through the transfer transistor Tr24 and the memory cell transistor Tr26. The selected bit line current is 100 μA to 150 μ per memory cell.
If a current of A flows, and data is read from one memory cell, an extra selected bit line current of 127 columns flows, and the order reaches several tens of mA.

Therefore, the present invention solves such a problem, and an object thereof is to turn on only the word line WL and the transfer transistor selected by the column selection signal Y0 and turn on the column selection signal Y0. By turning off the transfer transistor of the memory cell circuit which is not selected by, the extra selected bit line current is not passed and the current consumption is reduced.

[0006]

In a semiconductor memory device having a memory cell having a transfer transistor for transmitting memory cell data, a gate terminal is a column selection signal, a first conductive electrode is a row selection signal, and a second selection electrode is a second selection signal. A first transistor whose conductive electrodes are respectively connected to the gate terminals of the transfer transistors of the individual memory cell circuits or a plurality of memory cell circuits, and a load for discharging the gate terminal potential of the transfer transistors. It is characterized by being composed of a transistor or a load resistor.

[0007]

According to the above configuration of the present invention, the potential VY0 of the column selection signal Y0 is High and the potential VWL of the word line WL is
When High, the first transistor is turned on and the transfer transistor is also turned on. When the potential VY0 of the column selection signal Y0 is low and the potential VWL of the word line WL is high, the first transistor is turned off, and the gate terminal potential of the transfer transistor is GND (ground) by the load transistor or the load resistor. ) Is discharged.

[0008]

1 is a memory cell circuit according to an embodiment of the present invention, in which a gate terminal G of a first transistor Tr17 is provided.
7 is connected to the column selection signal Y0, the drain terminal D9 is connected to the word line WL, and the source terminal S8 is connected to the gate terminals G of the transfer transistors Tr13 and Tr14.
1 and G4. In addition, the first transistor T
A load transistor or load resistor is connected between the source terminal S8 of r17 and GND (ground). With this circuit configuration, the following operation is performed.

(1) The potential VWL of the word line WL is High
When the potential VY0 of the column selection signal Y0 is High, the first transistor Tr17 is turned on, and the potential VWL of the word line WL is applied to the gate terminals G1 and G4 of the transfer transistors Tr13 and Tr14. And Tr14 are in the ON state,
Since the potential VY0 of the column selection signal Y0 is High, the column selection gate transistors Tr18 and Tr19 are also turned on, and the memory cells, the bit lines BL, BLB and the data bus D
Each of B and DBB becomes conductive, and the data of the memory cell is deselected.
The data is from the bit lines BL, BLB to the data bus DB, DB.
Through B, data write and read operations are performed.

(2) The potential VWL of the word line WL is High
When the potential VY0 of the column selection signal Y0 is Low, the first transistor Tr17 is turned off, and the potential VWL of the word line WL is changed to the transfer transistor Tr1.
3 and Tr14 are not applied to the gate terminals G1 and G4, the transfer transistors Tr13 and Tr14 are in the OFF state, and the potential VY0 of the column selection signal Y0 is Low, so the column selection gate transistors Tr18 and Tr19 are also O.
In the FF state, the memory cell, the bit lines BL, BLB and the data buses DB, DBB are turned off. The potentials at the gate terminals G1 and G4 of the transfer transistors Tr13 and Tr14 are discharged to GND (ground) by the load transistor or load resistance.

(3) The potential VWL of the word line WL is low
When the potential VY0 of the column selection signal Y0 is Low at (2)
Similarly, the first transistor Tr17 is in the OFF state, the transfer transistors Tr13 and Tr14 are also in the OFF state, and the column selection gate transistors Tr18 and Tr14 are also in the OFF state.
19 is also turned off, the memory cell and the bit line BL,
BLB and the data buses DB and DBB are turned off, and the potentials at the gate terminals G1 and G4 of the transfer transistors Tr13 and Tr14 are discharged to GND (ground) by the load transistors or load resistors.

In the conventional circuit shown in FIG. 2, the transfer transistors Tr23 and Tr24 are turned on in the state of (2), and even in the memory cell circuit not selected by the column selection signal Y0, the power supply VDD and the load transistor T
Although the selection bit line current flows through the route of r22, transfer transistor Tr24, memory cell transistor Tr26, and GND (ground), in the circuit of the present invention in FIG. 1, the potential of the word line WL is High and the column selection signal Y0 Since the transfer transistors Tr13 and Tr14 are turned on only when the potential is High, if one data is read, the extra selected bit line current for 127 columns can be reduced.

As shown in the embodiment of FIG. 1, the transfer transistor of each memory cell circuit is connected to the column selection signal Y0.
Assuming that one column of the temporarily divided memory cell block is unified into 128 columns by controlling with, the 4 Mbits are divided into 64, and one block is 512 rows * 128 columns, 1
6M bits are divided into 128, and 1 block is 1024 rows *
Since there are 128 columns, the memory cell must be divided into many blocks, which increases the chip area of the row decoder circuit and the column decoder circuit. On the contrary, if the number of blocks is reduced, the number of columns increases and the current consumption increases. But,
In the embodiment of FIG. 1, by configuring the first transistor Tr17 as an N-type transistor, it can be configured in the same WELL as the transistor of the memory cell, and the load resistor R13 is configured as a second layer with polysilicon or the like to reduce the area. Can be reduced, so that the chip area can be suppressed and the power consumption can be reduced. Further, it is particularly advantageous for a 1-bit or 4-bit RAM (random access memory).

Therefore, the transfer transistors Tr13 and Tr14 are turned on only when the word line WL and the column selection signal Y0 are High, so that the transfer transistors Tr13 and Tr14 are turned on, except for the selected memory cell circuit. Since the selected bit line current does not flow into the device, the current consumption is reduced.

[0015]

According to the invention described above, the transfer transistors are word lines selected by the row decoder in the word lines WL wired for all memory cell groups or divided memory cell blocks. Not all columns are turned on by WL, but only the transfer transistors selected by the two signals of word line WL and column selection signal Y0 are turned on.
Therefore, the extra selected bit line current due to the transfer transistors in all the columns being turned on by the word line WL does not flow, and the current consumption is reduced.

[Brief description of drawings]

FIG. 1 is a memory cell circuit diagram showing an embodiment of the present invention.

FIG. 2 is a memory cell circuit diagram of a conventional circuit.

FIG. 3 is a memory cell block diagram of a RAM (random access memory) having a capacity of 256 Kbits.

[Explanation of symbols]

Tr11, Tr12, Tr21, Tr22: Load transistors Tr13, Tr14, Tr23, Tr24: Transfer transistors Tr15, Tr16, Tr25, Tr26: Memory cell transistors Tr17: Switch transistors Tr18, Tr19, Tr27, Tr28: Column selection gate transistors R11 , R12, R21, R22: High load resistance R13: Gate potential discharge load resistance of transfer Tr G1, G4, G7, G10, G13: Gate terminal S2, S5, S8, S11, S14: Source terminal D3, D6, D9, D13, D15: Drain terminals A, B, C, D: Potential at each intersection WL: Word line Y0: Column selection signal BL, BLB: Bit line, bit line (bar) DB, DBB : Data bus, data bus Space (bar) VDD: power supply voltage block 1-16: memory cell block E: row decoder circuit

Claims (1)

1. A semiconductor memory device having a memory cell having a transfer transistor for transmitting memory cell data, wherein a gate terminal is a column selection signal and a first conductive electrode is a row selection signal. To discharge the gate terminal potential of the transfer transistor and the first transistor whose second conductive electrode is connected to the gate terminal of the transfer transistor of the individual memory cell circuit or the plurality of memory cell circuits, respectively. A semiconductor memory device comprising the load transistor or the load resistor of.