JPH0535656A - Data retrieving system - Google Patents

Abstract

PURPOSE:To shorten the retrieving time of data in a computer system having a DMA controller. CONSTITUTION:To a computer system, the hardware constituted of a CPU I/F 8, a DMA I/F 9, a CPU I/F 10, a retrieving data register group 11, a comparator group 12, an FIFO buffer 13, an AND gate 14, a coincidence address stack control part 15, a retrieving data number register 16, a frequency comparator 17, and a coincidence address stack 18 is added, a CPU sets the retrieving data and the number of the times of the request of the retrieving data to the retrieving data number register 16, a DMA controller transfers the data of the designated area on a main memory to the FIFO buffer 13, the data of the retrieving data register group 11 and the FIFO buffer 13 are simultaneously compared with plural data by the comparator group 12 and the address of the series of the data coincident with the retrieving data and the number are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data retrieval system on a main memory in a computer system having a direct memory access (hereinafter referred to as "DMA") controller.

[0002]

2. Description of the Related Art A conventional data retrieval procedure is shown in FIG. When retrieving data or character strings composed of multiple bytes in main memory in a conventional computer system, a program reads the data in main memory byte by byte.
This is done by sequentially comparing the data to be retrieved and the data to be retrieved byte by byte. FIG. 3 shows retrieval data (D0, D1, D2 ... Dn-1) consisting of n bytes in the range from addresses a0 to a1 on the main memory by the above program.
Is a flow chart showing the operation for searching up to M times and storing the head address in the main memory having the matching data in the main memory starting from the address s0.

In the figure, IX, IY, IZ and IZa are index registers of the CPU in the computer, and each has the following meaning, and IX indicates the address currently being searched. IY is the address of IX, the first byte D of data
When 0 matches, it indicates addresses IX + 1 to IX + n-1 for comparing the remaining D1 to Dn-1. IZ indicates an address on the main memory for storing the head address of the address having the matching data as a result of the search. IZa represents the number of data matching the search results.

R0 is a general-purpose register of the CPU and indicates in the flow chart which byte number of D1 to Dn-1 is currently being compared. First, IX, IZ, IZa
Is set to the initial value a0, s0,0 (step ST
1). Steps ST2 to ST4 are the main loop of this program, and while incrementing the value of IX, it is checked whether or not it matches the first byte D0 of the search data (step ST2). If they do not match, IX is incremented (step ST3), and IX
Reaches the end value a1 of the address, this loop ends (step ST4).

If they match, the contents of 1 to n-1 bytes are read out byte by byte and compared. Initial values are set in IY and r0 (step ST5). When IY, r0 is incremented (step ST6) and the comparison of 1 to n-1 bytes is completed (step ST7), it is assumed that the search data is found and IX shows the value of IX at that time. The data is stored in the position and IZ and IZa are incremented (b is the bit number of the bit of the r0th one data converted into bytes) (step ST9). If data different from the search data appears before r0 reaches n-1, the process exits this loop and returns to the main loop of steps ST2 to ST4 (step ST8).

If the value of IZa is larger than the set value M, the search is interrupted (step ST10). If it is equal to or less than M, the search for the next address is started (step ST1).
1). As described above, this flow ends when the search in the range of a0 to a1 ends or when M data matches are found. Where IZa is the number of matching data found and is (s0) to (s0 + IZa-
1) The head address of the data is stored in the address.

[0007]

However, the number of times ac of access to the main memory in the above-described method has a value represented by the equation (1), which is the theoretical minimum value a1−
a0 + 1 or more times. ac = (a1−a0 + 1) · (1 + hr · nr). ． ． ． ． (1) ac: Main memory access count a1-a0: Main memory range address to be searched. hr: Probability that the 0th byte matches, but does not match any of 1 to n. Average of positions that do not match when nr: hr (1 ≦ nr
<N) Further, since the method is based on the program, the CPU takes time because it fetches the code of the program in addition to the main memory access for searching. Moreover, there is a problem that other processing cannot be performed during the search.

The present invention has been made in view of the above points, and in order to solve the above problems and prevent an increase in the number of accesses to the main memory during data retrieval, a DMA function and a first-in-first-out (hereinafter referred to as " The purpose is to minimize the number of accesses to the main memory and to perform data retrieval at high speed by providing hardware by combining a buffer and a multi-byte comparator (referred to as "FIFO"). ..

[0009]

In order to solve the above problems, the present invention is directed to a computer system having a DMA controller as shown in FIG. 1, which includes a search data register group for setting search data and a main memory. FIFO buffer for reading and storing a series of data, and data for both
Group of comparators for comparing data at the same time, a match address stack control unit for finding the match count and match address, a match address stack for storing match addresses, a search data number register for setting the request count of search data, and a count When a hardware composed of a comparator is provided and the data consisting of a plurality of bytes is searched, the data is fetched from the main memory by the DMA access and the data is FIF'd.
It is provided with a function of storing the data in the O buffer and comparing the data of a plurality of bytes in the FIFO buffer with the search data at the same time.

[0010]

In the present invention, comparison of data of a plurality of bytes is performed.
Since it can be simultaneously performed by hardware, the loop of steps ST5 to ST8 of the flowchart of FIG.
It can be reduced to 0-a1 + 1. Also, since the data is accessed by the DMA controller, the CPU
You can afford time.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a block diagram showing the configuration of a computer system to which the data search method of the present invention is applied. As shown in the figure, this computer system comprises a CPU 1, a DMA controller 2, a main memory 3 and an additional hardware 4 added by the present invention. Address bus 5, data bus 6, DMA I / F signal 7, CPU I / F signal 8, DM
It is connected by the AC I / F signal 9a.

For data retrieval, the additional hardware 4 added by the present invention by the CPU 1 by the CPU I / F signal 8 is used.
Set the data to be searched for, the maximum number of search data, and DMA
The address range to be searched is set in the DMA controller 2 by the CI / F signal 9a, and the additional hardware 4 is activated by the CPU I / F signal 8. The activated additional hardware 4 is the DMA I / F signal 7
To request data from the DMA controller 2. D
The MA controller 2 gives an address to the main memory device 3 by the address bus 5, and when the main memory device 3 outputs a value of data corresponding to the address, the DMA I / F signal 7 is sent to the additional hardware 4 as the data. -Tell that you are out.

The additional hardware 4 takes in the value of the data from the main storage device 3, compares it with the search data, and stores the address on the address bus 5 when the data matches. When the search is completed, the additional hardware 4 causes the CPUI
The CPU 1 is notified by the / F signal 8. The retrieval result is C by reading the value of the address stored in the additional hardware 4 through the address bus 5.
It is given to PU1.

FIG. 1 is a block diagram showing the internal structure of the additional hardware 4 of the present invention shown in FIG. The additional hardware 4 is DMA I / F9, CPU I / F10, search data.
Data register group 11, comparator group 12, FIFO buffer 13, AND gate 14 for all outputs of comparator group 12, match address stack control section 15 in the control section of match address stack 18, search data number register 16 and a frequency comparator 17.

The CPU I / F 10 sets the search data register group 11 and the search data number register 16 by the CPU I / F 10. The retrieved data register group 11 stores the retrieved data. The search data register group 11 is composed of a plurality of registers consisting of search data 19 and valid bits 20. Search data for which the valid bit 20 is not set is not a target for comparison. Therefore, it is possible to search for a character string of arbitrary length that includes a character that is not to be compared on the way. When activated, the DMA I / F 9 controls the DMA request response, and the data from the memory is stored in the FIFO buffer 13. The FIFO buffer 13 operates as a FIFO, and data flows from top to bottom as indicated by arrows. The data protruding from the bottom is discarded. The data in the FIFO buffer 13 is compared by the comparator group 12 with the search data 19 in which the valid bit 20 in the search data register group 11 is set every time one data is read. .. This comparison is simultaneously performed on all the data in the FIFO buffer 13.

The output of the comparator group 12 is ANDed through the AND gate 14, and when all the data match, it is transmitted to the matching address stack control unit 15. The coincidence address stack control unit 15 has a register indicating the number of coincidences of all the data, and in response to a signal from the AND gate 14, the address at that time is placed at a position in the coincidence address stack 18 corresponding to the value of the register. The address value (address of the final data) on the bus is recorded. The value in the register is compared with the search data number register 16 by the frequency comparator 17, and the search is terminated when a match is found or the match address stack 18 is completely used. If neither of these is the case, the operation is terminated by stopping the DMA controller.

FIG. 4 shows a flow chart in the case where the search by this method is performed by a program. As can be seen from FIG. 4, the comparison of a plurality of data is step ST2.
Since it is performed in one step of 2, a high-speed search is performed by a simple loop as compared with the conventional method shown in FIG. Flow chart loop ST2, ST5, ST6, ST of FIG.
The steps 7 and ST8 are performed simultaneously by hardware, and as can be seen, the number of memory accesses is a1 -a0 +1 a minimum. Needless to say, the program method cannot simultaneously compare a plurality of pieces of data, so that hardware is required to realize this flow.

[0018]

As described in detail above, according to the present invention, the following effects are expected. (1) Since the comparison of data of a plurality of bytes can be performed simultaneously by hardware, the number of memory accesses by the conventional programming method is reduced {(a1 -a0 + 1) (1 + hr.n
It can be reduced from r) to (a1−a0 + 1)} times.

(2) Further, since the DMA function is used, the time required for the CPU to fetch the instruction code of the program becomes unnecessary, and the CPU can perform other processing during data retrieval. There is an advantage that you can.

[Brief description of drawings]

FIG. 1 is an additional hardware block diagram according to the present invention.

FIG. 2 is a system block diagram according to the present invention.

FIG. 3 is a flowchart of data retrieval by a prior art program.

FIG. 4 is a flowchart when the method of the present invention is replaced with a program.

[Explanation of symbols]

 1 CPU 2 DMA controller 3 Main memory 4 Additional hardware 5 Address bus 6 Data bus 7 DMA I / F signal 8 CPUI / F 9 DMAI / F 9a DMAI / F signal 10 CPUI / F 11 Search data register Group 12 Comparator group 13 FIFO buffer 14 AND gate 15 Match address stack control unit 16 Search data number register 17 Count comparator 18 Match address stack 19 Search data 20 Effective bit

Claims (1)

Claims: 1. CPU, direct memory access (D
(MA) In a data retrieval method of a computer system having a controller and a main memory, a retrieval data register group for setting retrieval data and a series of target data is read from the main memory. , A first-in first-out (FIFO) buffer for storing, a group of comparators for simultaneously comparing the data of the both, a match address stack control unit for obtaining the number of matches and a match address, a match address stack for storing the match address, retrieval A hardware comprising a search data number register for setting the number of requests for data and a frequency comparator for comparing the number of matches is provided, and the CPU determines the number of requests for the search data and the search data. And the DMA controller causes the data in the designated area on the main memory to flow to the FIFO buffer, The search data register group and the data of the FIFO buffer are simultaneously compared by the comparator group to obtain a plurality of data, and the address and the number of a series of data matching the search data are obtained. A data retrieval method characterized in that