JPH0535603A - Collating method for rom constitution - Google Patents

Collating method for rom constitution

Info

Publication number
JPH0535603A
JPH0535603A JP18654891A JP18654891A JPH0535603A JP H0535603 A JPH0535603 A JP H0535603A JP 18654891 A JP18654891 A JP 18654891A JP 18654891 A JP18654891 A JP 18654891A JP H0535603 A JPH0535603 A JP H0535603A
Authority
JP
Japan
Prior art keywords
rom
cpu
stored
roms
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18654891A
Other languages
Japanese (ja)
Other versions
JP3141165B2 (en
Inventor
Makoto Suzuki
鈴木  誠
Toshiaki Nagasawa
敏明 長沢
Shigeo Kobayashi
茂男 小林
Minoru Furubayashi
実 古林
Hidenori Koga
英範 古賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honda Motor Co Ltd
Original Assignee
Honda Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd filed Critical Honda Motor Co Ltd
Priority to JP18654891A priority Critical patent/JP3141165B2/en
Publication of JPH0535603A publication Critical patent/JPH0535603A/en
Application granted granted Critical
Publication of JP3141165B2 publication Critical patent/JP3141165B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

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  • Stored Programmes (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To automatically judge whether the ROM constitution is normal or not before the control is executed. CONSTITUTION:In a multi-CPU system which is constituted so that a first CPU 11, a second CPU 12 and a third CPU 13 are connected through a first RAM 21 and a second RAM 22 and interlocked mutually, and also, a first ROM 31, a second ROM 32 and a third ROM 33 are set to each CPU 11, 12 and 13, serial discrimination numbers (1, 2, 3) which increase successively, and collation data (1-2-3) are stored in each ROM 31, 32 and 33, and a third ROM 33 in which the maximum identification number 3 is stored, respectively, and in the case comparison data in which the discrimination numbers are arranged in accordance with an actual array of the ROMs does not coincide with collation data, it is judged that the ROM constitution is abnormal. In a new fourth ROM 34 change with a second ROM 32, identification number 4 and collation data (1-4-3) are stored, and a collation is executed, based thereon.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数個のCPUを有す
るマルチCPUシステムのROM構成が正常か否かを照
合するROM構成の照合方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM configuration collating method for collating a ROM configuration of a multi-CPU system having a plurality of CPUs.

【0002】[0002]

【従来の技術】複数種類の制御を同時に平行して行う場
合には、各制御毎にCPUを設け、各々の制御を専用の
CPUで行うと共に、各CPUを相互に連結し各制御を
互いに連動して行うマルチCPUシステムが実用化され
ている。このようなマルチCPUシステムでは、各制御
内容をプログラムとしてROMに予め記憶しておき、該
ROMを各CPUに各々セットするように構成されてい
る。そして、上記制御内容を変更する場合には、該変更
する制御を行うCPUにセットされているROMを、新
たなプログラムが記憶されている別のROMと交換する
ことにより行う。
2. Description of the Related Art When a plurality of types of control are performed in parallel at the same time, a CPU is provided for each control, each control is performed by a dedicated CPU, and each CPU is connected to each other to interlock each control. The multi-CPU system which is carried out is put into practical use. In such a multi-CPU system, each control content is stored in advance in the ROM as a program, and the ROM is set in each CPU. When changing the control contents, the ROM set in the CPU that performs the changing control is replaced with another ROM in which a new program is stored.

【0003】[0003]

【発明が解決しようとする課題】上記ROMの変更に際
し、誤って、制御内容を変更したいCPUにセットされ
ているROM以外のものと新たなプログラムが記憶され
ているROMとを交換した場合には、実際に制御を実行
し、誤ってセットされたROMのプログラムに基づく制
御が行われ、ROMの誤交換による不具合が発生するま
ではこのようなROM構成の異常を発見しにくいという
問題があった。
When the above ROM is changed, if a ROM other than the ROM set in the CPU whose control contents are to be changed is mistakenly replaced with a ROM storing a new program. However, there is a problem that it is difficult to find such an abnormality in the ROM configuration until the control is actually executed and the control is performed based on the program of the ROM that is erroneously set, and a problem occurs due to the erroneous replacement of the ROM. ..

【0004】そこで本発明は、上記の問題点に鑑み、マ
ルチCPUシステムのROM構成を、実際に制御を実行
する前に自動的に正常か否かを判断するROM構成の照
合方法を提供することを目的とする。
In view of the above problems, the present invention provides a method for checking the ROM configuration of a multi-CPU system, which automatically determines whether or not the ROM configuration is normal before actually executing control. With the goal.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に本発明は、所定の順序で相互に連結された複数個のC
PUの各々にセットされる、予めプログラムが記憶され
たROMの構成が正常か否かを判断するROM構成の照
合方法において、上記プログラムと共に、各ROMに順
次増加する一連の識別番号を記憶させ、かつ、最大識別
番号を記憶させるROMに、各ROMの識別番号を該各
ROMをセットすべき各CPUの連結順位に従った順位
に該各ROMの識別番号が位置するように並べた数列を
照合データとして記憶させておき、各CPUに実際にセ
ットされた各ROMの識別番号を読み取って、これら識
別番号を該各ROMがセットされた各CPUの連結順位
に従った順位に該各ROMの識別番号が位置するように
並べた数列からなる比較データを作成し、この比較デー
タと照合データとを比較し、両者が一致した場合にRO
M構成が正常であると判断することを特徴とする。
To achieve the above object, the present invention provides a plurality of Cs interconnected in a predetermined order.
In a ROM configuration collation method for determining whether or not the configuration of a ROM in which a program is stored, which is set in each PU, is normal, a series of sequentially increasing identification numbers is stored in each ROM together with the program, In addition, collating a number sequence in which the identification number of each ROM is stored in the ROM for storing the maximum identification number so that the identification number of each ROM is located in the order according to the connection order of the CPUs to which each ROM should be set. It is stored as data, the identification number of each ROM actually set in each CPU is read, and these identification numbers are identified in order of the connection order of each CPU in which each ROM is set. Comparing comparison data consisting of a number sequence arranged so that numbers are positioned, comparing the comparison data with collation data, and if both match, RO
It is characterized by judging that the M configuration is normal.

【0006】[0006]

【作用】各ROMに、プログラムと共に順次増加する一
連の識別番号を記憶させておき、これら各ROMを本来
セットされる各CPUの連結順位に従った順位に該各R
OMの識別番号が位置するように並べた数列を照合デー
タとして予め所定のROMに記憶させておく。
In each ROM, a series of identification numbers, which sequentially increase with the program, are stored, and each R is placed in an order according to the connection order of each CPU that is originally set.
A number sequence arranged so that the identification number of the OM is located is stored in advance in a predetermined ROM as collation data.

【0007】一方、実際にセットされた各ROMの識別
番号を読み取って、実際に該各ROMがセットされた各
CPUの連結順位に従った順位に該各ROMの識別番号
が位置するように並べた数列からなる比較データを作成
する。
On the other hand, the identification numbers of the ROMs actually set are read and arranged so that the identification numbers of the ROMs are located in the order according to the connection order of the CPUs in which the ROMs are actually set. Create comparison data consisting of a sequence of numbers.

【0008】これらROMの内、たとえ一部のものでも
セットされるべきCPU以外のものにセットされていれ
ば、照合データと比較データとが一致しないので、両者
を比較することによりROM構成の異常が検知される。
If some of these ROMs are set in a CPU other than the CPU to be set, the collation data and the comparison data do not match. Therefore, by comparing the two, the ROM configuration is abnormal. Is detected.

【0009】また、比較データを最大識別番号が記憶さ
れるROMに記憶させることにより、バージョンアップ
等によりROMを交換する場合には最新のROMの識別
番号が最大識別番号になり、ROM交換後の新たなRO
M構成を該最新のROMに記憶させることにより、照合
データがROM交換に伴う新たな構成に対応するものに
更新される。
Further, by storing the comparison data in the ROM in which the maximum identification number is stored, when the ROM is replaced by a version upgrade or the like, the identification number of the latest ROM becomes the maximum identification number. New RO
By storing the M configuration in the latest ROM, the collation data is updated to correspond to the new configuration accompanying the ROM replacement.

【0010】[0010]

【実施例】本発明の実施例について以下に図を用いて説
明する。図において、11は第1CPU、12は第2C
PU、13は第3CPUを示し、該各CPU11・12
・13は個々に各々の制御を行う。ところで、これらC
PUの内、第1CPU11と第2CPU12とは共通の
第1RAM21を介して接続され、第2CPU12と第
3CPU13とは同じく共通の第2RAM22を介して
接続され、各CPU11・12・13の制御が相互に連
動するように構成されている。そして、該各CPU11
・12・13による制御の内容は各CPU11・12・
13の各々にセットされている第1ROM31・第2R
OM32・第3ROM33にプログラムとして記憶され
ている。これらROM31・32・33へプログラムを
記憶させるには専用の記憶装置を用いなければならず、
従って、各ROM31・32・33は予め他の場所でプ
ログラムを記憶された後、各CPU11・12・13が
設置されている場所に運ばれ対応するCPUにセットさ
れる。
Embodiments of the present invention will be described below with reference to the drawings. In the figure, 11 is the first CPU and 12 is the second CPU.
PU and 13 are third CPUs, and the CPUs 11 and 12 are
・ 13 performs each control individually. By the way, these C
Among the PUs, the first CPU 11 and the second CPU 12 are connected via a common first RAM 21, the second CPU 12 and the third CPU 13 are connected via a common second RAM 22, and the control of each CPU 11, 12, 13 is mutually performed. It is configured to work together. Then, each CPU 11
・ The contents of control by 12 ・ 13 are for each CPU 11 ・ 12.
First ROM 31 and second R set in each of 13
It is stored as a program in the OM 32 and the third ROM 33. In order to store the programs in these ROMs 31, 32 and 33, a dedicated storage device must be used,
Therefore, each ROM 31, 32, 33 is stored in a program in another place in advance, and then is carried to the place where each CPU 11, 12, 13 is installed and set in the corresponding CPU.

【0011】ところで、各ROM31・32・33にプ
ログラムを記憶させる際に、順次増加する一連の識別番
号をプログラムと共に記憶させ、更に、最大識別番号が
記憶されるROM、本実施例の場合には最大識別番号で
ある3が記憶される第3ROM33に照合データを記憶
させておく。該照合データとは、各ROM31・32・
33の正規の配列状態を示すもので、図1では各ROM
31・32・33が正規の状態にセットされていれば、
各識別番号は左から順に1・2・3となるので、第3R
OM33には予め1−2−3という照合データを記憶さ
せておく。尚、図1において、各ROM31・32・3
3の上段に識別番号を、下段に照合データを示した。
By the way, when a program is stored in each of the ROMs 31, 32, and 33, a series of sequentially increasing identification numbers is stored together with the program, and further, the ROM in which the maximum identification number is stored, in the case of this embodiment, The collation data is stored in the third ROM 33 in which the maximum identification number of 3 is stored. The collation data means each ROM 31, 32,
33 shows a regular array state of 33. In FIG.
If 31, 32, 33 are set to the normal state,
Since the respective identification numbers are 1, 2 and 3 from the left, the 3rd R
The collation data 1-2-3 is stored in advance in the OM 33. In FIG. 1, each ROM 31, 32, 3
The identification number is shown in the upper part of 3 and the matching data is shown in the lower part.

【0012】次に、各CPU11・12・13による制
御を開始する前に、図2に示す照合フローを実行する。
ところで本実施例の場合、該照合フローはCPU11で
実行するようにプログラムしているので、該照合フロー
が実行されると、まずステップS1にて、ROM33の
識別番号である3が一旦RAM22に転送され、CPU
12は該RAM22に転送された3とROM32の識別
番号である2とからなる数列2−3を作成しこれをRA
M21へ転送する。次にCPU11は該数列2−3を読
み出し、ROM31の識別番号である1をこれに付加し
数列1−2−3とし、これを比較データN1としてRA
M21に格納する。次のステップS2では、各ROM3
1・32・33に記憶されている識別番号の内、最大識
別番号のROM、すなわち第3ROM33に記憶されて
いる照合データN2=1−2−3をRAM21に転送す
る。そして、ステップS3にて上記N1とN2とを比較
し、両者が一致していればステップS4に進み、ROM
構成は正常であると判断する。一方、各ROMをセット
する際に誤って、例えば第2ROM32と第3ROM3
3とを相互に取り違えてセットした場合には、比較デー
タはN1=1−3−2となり、照合データであるN2=1−
2−3と一致せず、よってこの場合にはステップS5へ
進み、ROM構成が異常であると判断する。
Next, the collation flow shown in FIG. 2 is executed before the control by the CPUs 11, 12, and 13 is started.
By the way, in the case of the present embodiment, since the collation flow is programmed to be executed by the CPU 11, when the collation flow is executed, first, in step S1, the identification number 3 of the ROM 33 is temporarily transferred to the RAM 22. And CPU
12 creates a sequence 2-3 consisting of 3 transferred to the RAM 22 and 2 which is the identification number of the ROM 32 and RA
Transfer to M21. Next, the CPU 11 reads out the sequence 2-3, adds 1 which is the identification number of the ROM 31 to the sequence 1-2-3, and sets this as the comparison data N1 and RA
Store in M21. In the next step S2, each ROM 3
Of the identification numbers stored in 1, 32, and 33, the verification data N2 = 1-2-3 stored in the ROM having the largest identification number, that is, the third ROM 33, is transferred to the RAM 21. Then, in step S3, the above N1 and N2 are compared, and if they match, the process proceeds to step S4 and the ROM
Judge that the configuration is normal. On the other hand, when setting each ROM, for example, the second ROM 32 and the third ROM 3 are erroneously
When 3 and 3 are mistakenly set, the comparison data becomes N1 = 1-3-2, and the comparison data N2 = 1-
Therefore, in this case, the process proceeds to step S5, and it is determined that the ROM configuration is abnormal.

【0013】次に、各ROMが正常にセットされている
状態から、バージョンアップ等により一部制御内容を変
更する一例として、第2ROM32を新たな第4ROM
34に交換する場合について説明する。該第4ROM3
4には新たなプログラムと共に、識別番号4と照合デー
タ1−4−3とを記憶させておく。従って、正規に交換
が行われると、比較データはN1=1−4−3となり、ま
た該第4ROM34の識別番号が最大になるので照合デ
ータは該第4ROM34に記憶されているN2=1−4−
3となり、両者は一致するが、誤って、例えば第3RO
M33と第4ROM34とを交換すると、比較データは
N1=1−2−4となり照合データであるN2=1−4−3
と一致しないのでROM構成が異常であると判断し、R
OM交換の誤りを発見することができる。
Next, the second ROM 32 is replaced with a new fourth ROM as an example of partially changing the control contents by version upgrade or the like from the state where each ROM is normally set.
The case of exchanging with 34 will be described. The fourth ROM3
The identification number 4 and the collation data 1-4-3 are stored in No. 4 together with the new program. Therefore, when the exchange is properly performed, the comparison data becomes N1 = 1-4-3, and the identification number of the fourth ROM 34 becomes maximum, so that the verification data is stored in the fourth ROM 34 as N2 = 1-4. −
3 and both match, but erroneously, for example, the third RO
When the M33 and the fourth ROM 34 are exchanged, the comparison data becomes N1 = 1-2-4 and the verification data N2 = 1-4-3.
It is judged that the ROM configuration is abnormal because it does not match
Errors in OM exchange can be found.

【0014】[0014]

【発明の効果】以上の説明から明らかなように、本発明
は、マルチCPUシステムの各CPUにセットされるR
OMの構成が正常であるか否かを、制御を実行する前に
自動的に判断することができる。
As is apparent from the above description, according to the present invention, the R set in each CPU of the multi-CPU system.
Whether or not the configuration of the OM is normal can be automatically judged before executing the control.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明が適用されるマルチCPUシステム
の一例を示す図
FIG. 1 is a diagram showing an example of a multi-CPU system to which the present invention is applied.

【図2】 照合の処理内容を示すフロー図FIG. 2 is a flow chart showing the contents of collation processing.

【符号の説明】[Explanation of symbols]

11 第1CPU 12 第2CPU 13 第3CPU 31 第1ROM 32 第2ROM 33 第3ROM 34 第4ROM 11 1st CPU 12 2nd CPU 13 3rd CPU 31 1st ROM 32 2nd ROM 33 3rd ROM 34 4th ROM

───────────────────────────────────────────────────── フロントページの続き (72)発明者 古林 実 埼玉県狭山市新狭山1丁目10番地1 ホン ダエンジニアリング株式会社内 (72)発明者 古賀 英範 埼玉県狭山市新狭山1丁目10番地1 ホン ダエンジニアリング株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Minoru Kobayashi 1-10-1 Shin-Sayama, Sayama-shi, Saitama Prefecture, Honda Engineering Co., Ltd. (72) Hidenori Koga 1-10-1 Shin-Sayama, Sayama City, Saitama Prefecture Within Da Engineering Co., Ltd.

Claims (1)

【特許請求の範囲】 【請求項1】 所定の順序で相互に連結された複数個
のCPUの各々にセットされる、予めプログラムが記憶
されたROMの構成が正常か否かを判断するROM構成
の照合方法において、上記プログラムと共に、各ROM
に順次増加する一連の識別番号を記憶させ、かつ、最大
識別番号を記憶させるROMに、各ROMの識別番号を
該各ROMをセットすべき各CPUの連結順位に従った
順位に該各ROMの識別番号が位置するように並べた数
列を照合データとして記憶させておき、各CPUに実際
にセットされた各ROMの識別番号を読み取って、これ
ら識別番号を該各ROMがセットされた各CPUの連結
順位に従った順位に該各ROMの識別番号が位置するよ
うに並べた数列からなる比較データを作成し、この比較
データと照合データとを比較し、両者が一致した場合に
ROM構成が正常であると判断することを特徴とするR
OM構成の照合方法。
Claim: What is claimed is: 1. A ROM configuration for determining whether or not the configuration of a ROM, in which a program is stored in advance, which is set in each of a plurality of CPUs connected to each other in a predetermined order, is normal. In the verification method of, each ROM together with the above program
In the ROM for storing a series of sequentially increasing identification numbers and for storing the maximum identification number, the identification numbers of the ROMs are arranged in the order of the connection order of the CPUs in which the ROMs should be set. A sequence of numbers arranged so that the identification numbers are located is stored as collation data, the identification numbers of the ROMs actually set in the respective CPUs are read, and these identification numbers are stored in the respective CPUs in which the respective ROMs are set. Comparing comparison data composed of a number sequence arranged so that the identification numbers of the ROMs are located in the order according to the concatenation order, comparing the comparison data with the collation data, and when both match, the ROM configuration is normal. R characterized by determining that
OM configuration matching method.
JP18654891A 1991-07-25 1991-07-25 Verification method of ROM configuration Expired - Fee Related JP3141165B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18654891A JP3141165B2 (en) 1991-07-25 1991-07-25 Verification method of ROM configuration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18654891A JP3141165B2 (en) 1991-07-25 1991-07-25 Verification method of ROM configuration

Publications (2)

Publication Number Publication Date
JPH0535603A true JPH0535603A (en) 1993-02-12
JP3141165B2 JP3141165B2 (en) 2001-03-05

Family

ID=16190440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18654891A Expired - Fee Related JP3141165B2 (en) 1991-07-25 1991-07-25 Verification method of ROM configuration

Country Status (1)

Country Link
JP (1) JP3141165B2 (en)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7612430B2 (en) 2000-06-14 2009-11-03 Infineon Technologies Ag Silicon bipolar transistor, circuit arrangement and method for producing a silicon bipolar transistor

Also Published As

Publication number Publication date
JP3141165B2 (en) 2001-03-05

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