JP2614677B2 - Write control method for storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the reliability and performance of an information processing system in which it is necessary to achieve both high reliability and high performance.

[0002]

2. Description of the Related Art An interleave method is known as a technique for improving the effective speed of a storage device. this is,
As shown in FIG. 5, the storage device is divided into independently operable modules called banks (BN), and storage is controlled by operating in parallel for all banks (BN). For example, each bank is divided main memory into four banks (BN) as in FIG. 5 (BN) is that composed of two ^14-word.
The lower 16 bits of the address information from the CPU indicate the bank (BN), and the upper 14 bits indicate the address in each bank (BN). If the upper 14-bit address is sent to the memory address register of each bank (BN) at the same time, all the banks (BN) operate in parallel and can access the contents of consecutive addresses within one storage cycle time. Speed is obtained. Such a technique of distributing addresses among the banks (BN) is called interleaving.

By the way, when an update history (log data) of a database system or the like is stored in a storage device, if write control is performed by a conventional interleave method, if a machine failure occurs during a write access, for example, up to where the data is. I can't tell if it's right or not right. In particular, if the log data itself is not known, recovery of the database may not be possible.

As a means for confirming that the log data is correct, as shown in FIG. 3, a header (D1) having the same contents before and after the log data (body (D2)) is used.
And the tailor (D3), do not write the body (D2) until the header (D1) is written, and do not write the tailor (D3) until the body (D2) is written. Is performed, and when the header (D1) and the tailor (D3) match, the data is confirmed to be correct.

This control involves writing a header (D1),
It is composed of three instructions of writing a body (D2) and writing a tailor (D3), and these are written according to the three instructions under the interleave method.

In this case, essentially, the writing of the body (D2) is possible only after the writing of the header (D1) is completed, and the writing of the tailor (D3) is started only after the writing of the body (D2) is completed. Writing is possible.

[0007]

If such a sequence is not guaranteed and the header (D1) is written, the body (D
If the process of writing 2) and the process of writing the tailor (D3) are write-controlled by three instructions under the interleave method, the following problem occurs.

That is, in the interleave system, all the banks (BN) shown in FIG.
According to these instructions, write control of recording the header (D1), recording the body (D2), and recording the tailor (D3) is performed in parallel in all the banks (BN).

In this case, the memory access of the three instructions is basically guaranteed, but the guarantee is only assured as the execution order of the instructions in the CPU, but the hardware, that is, the internal state of the memory, is not guaranteed. However, the writing order is not guaranteed.

That is, the writing of the header (D1), the writing of the body (D2), and the writing of the tailor (D3) are performed by interleaving to speed up the memory access.
The result is that they are processed separately in parallel regardless of whether or not the other writes have been completed correctly.

Therefore, during the parallel processing, the header (D
Although the writing of 1) and the writing of the tailor (D3) were performed correctly, there is a case where a writing error to the bank (BN) may occur when the bodies are written in parallel corresponding to them. In spite of the fact that there is originally incorrect data, the header (D1) and the tailor (D3) match, so that the result is that the data is recognized as correct.

Therefore, write a header (D1), write a body (D2), and write a tailor (D3).
Two instructions must be executed in their order, waiting for each to complete.

On the other hand, access to the storage device generally takes a much longer time than a normal instruction because of various checks and activation processes until the actual data transfer operation is started. This time is required each time a command is issued to the storage device.

Therefore, the header (D1) and the body (D
2) If the writing of the tailor (D3) is executed by three instructions, the result is that the central processing unit (CPU) is restrained for a long time.

The present invention solves the above-mentioned problems of the storage control method under the conventional interleave method, and ensures the data write assurance and speeds up the write processing. Make it an issue.

[0016]

The present invention employs the following means to solve the above-mentioned problems. Data is written to the storage device (1) divided into a plurality of banks (BN) in an interleaved manner, and before and after a body (D2) as data to be originally written, a header (D1) and a tailor having the same contents are written. (D3) is added, and the body (D2) is checked when the header (D1) matches the tailor (D3).
In the storage control method which guarantees the validity of the bank, the header (D1) is written to the bank (BN), the body (D2) is written to the bank (BN), and the bank (BN) of the tailor (D3) is written. ) Is written by one instruction, and at the time of writing, the writing of each data is to be interleaved, but is not to be interleaved among the three writings, and is performed over time. .

That is, conventionally, writing to the bank (BN) of the header (D1), writing to the bank (BN) of the body (D2), and writing to the bank (BN) of the tailor (D3) are performed. Header (D1) write command, body (D2) write command, tailor (D
3) In contrast to the three instructions of the write instruction, the present invention provides a header (D1), a body (D2),
The writing of the tailor (D3) to the storage device (1) is performed in accordance with one instruction, and at this time, the writing of the header (D1), the writing of the body (D2), and the writing of the tailer (D3) are performed individually. Although parallel processing by interleaving may be performed, parallel processing between the header (D1), the body (D2), and the tailor (D3) is stopped, and the header (D1), the body (D2), and the tailor (D3) are sequentially executed. A writing process is performed.

More specifically, as shown in the principle diagram of FIG.
According to the present invention, a write command generating means (2) for sending one write command to write a header (D1), a body (D2), and a tailor (D3) to a storage device (1); D1), body (D
2) a data identification means (3) for distinguishing the tailor (D3), and a header (D1) and a body (D2) by the data identification means (3) according to a write command from the write command generation means (2). And write control means (4) for controlling the writing to the storage device (1) with reference to the distinction between the tailor (D3), and the write control means (4) completes the writing of the header (D1). Stop writing the body (D2) and tailor (D3) until
After the writing of the header (D1) is completed, the writing of the body (D2) is started, and the writing of the tailor (D3) is stopped. After the writing of the body (D2) is completed, the writing of the tailor (D3) is performed. In writing, at least writing of the body (D2) is performed by an interleave method.

[0019]

First, one write command to write the header (D1), the body (D2) and the tailer (D3) to the storage device (1) is sent from the write command generating means (2). The write command generating means (2) is usually borne by a central processing unit (CPU).

In the present invention, the header (D1) and the body (D
2) Since the write command of the tailor (D3) is one, various checks and activation processes required for the write control until the actual data transfer operation is started are required only once.

At the time of writing, a header (D1) and a tailor (D3) having the same contents are added before and after the body (D2) as data to be originally written. The header (D1), body (D2), tailor (D
Since the write processing of 3) is performed, the processing target is the header (D1), body (D2), tailor (D
3) are collectively handled, but when writing, the data identification means (3) uses the header (D1) and the body (D1).
2) The tailor (D3) is distinguished, and according to this distinction, the header (D1), the body (D2), and the tailor (D3).
Are written in this order, and are mutually interleaved, that is, the writing of the header (D1) and the writing of the body (D1).
The writing of 2) and the writing of the tailor (D3) are not performed simultaneously in parallel.

That is, the writing of the body (D2) and the tailor (D3) is stopped by the writing control means (4) until the writing of the header (D1) is completed, and the body (D2) is written after the writing of the header (D1) is completed. , The writing of the tailor (D3) is stopped, and the writing of the tailor (D3) is performed after the writing of the body (D2) is completed.

As a result, the header (D1) and the tailor (D
The case where writing of 3) succeeds but writing of body (D2) fails does not occur. That is, the header (D
Despite the fact that 1) and the tailor (D3) match (the write guarantee has been obtained), there is no longer a state in which an error exists in the contents of the body (D2).

By the way, the write command from the central processing unit (CPU) as the write command generating means (2)
This is performed by sending a specific hardware instruction code, a transfer address, and a transfer data length to the storage device (1).

Therefore, in order to constitute the data identification means (3), a data length holding means (11) for holding the data length of data to be written in the storage device (1), and a first and last one of a writing unit. It is conceivable to provide a detecting means (41) for detecting that the vehicle is on the near side. However, this detecting means (41) is composed of a header (D1) and a tailor (D3).
Are established with the minimum write unit length.

The transmitted data length {which indicates the sum of the length of the header (D1), the length of the body (D2), and the length of the tailor (D3)} is represented by the data length holding means (11). ). In view of the data length held in the data length holding means (11), if the head of the writing unit is detected first, it can be identified that the head corresponds to the header (D1) and the end is the tailor (D3). .

Therefore, while writing the header (D1), the writing of the body (D2) and the tailor (D3) is made to wait until the writing is completed, and at the same time, the data length held by the data length holding means (11) is reduced. Header (D
1) Subtract the amount corresponding to the length. Next, after the writing of the header (D1) is completed, the writing of the body (D2) is started.
Wait for the writing of 3). In the meantime, an amount corresponding to the length of the body (D2) is subtracted from the data length held in the data length holding means (11) in accordance with the writing of the body (D2). Then, at the stage where the detection means (41) detects that it is just before the last of the write unit, the end of writing of the body (D2) is known, so that writing of the tailor (D3) is started last.

The data length holding means (11) can be realized by, for example, a length counter (11).
1) is determined from the value of the counter (11), and whether the transfer data to be written or currently being written is the header (D1), the body (D2), or the tailor (D
3) It can be embodied by the data type detecting means (41) for identifying the kind.

In addition, a header (D1), a tailor (D
Header (D1) and tailor (D3) directly from the contents of 3)
Can be identified to control the writing order. The above method is preferably implemented in an environment of a direct memory access method. That is, in the direct memory access method, the central processing unit (CPU)
And a write control means (4) (access control section (4)) which is independent from the central processing unit (CPU), and performs a write command received from the central processing unit (CPU) independently of the processing of the central processing unit (CPU). Therefore, the present invention is optimal when the write processing of the header (D1), the body (D2), and the tailer (D3) is collectively performed by one instruction, and the central processing unit (CPU) is effectively used during the processing. Can be achieved.

The storage device to be controlled in the present invention can be exemplified by a main storage device in addition to an extended storage device. These are storage hierarchies that can be directly accessed from the write control means.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 2, the device of this embodiment includes a central processing unit (CPU), a main storage device 31, and an extended storage device 1 (system storage).

The central processing unit (CPU) sends a write command, and the write command is accompanied by a specific hardware command code, a start address, and a transfer length. The transfer length refers to the length of transfer data to be written, and here has a transfer unit of 8 bytes. That is, as shown in FIG. 3, the data transferred in this embodiment is composed of a header (D1), a body (D2), and a tailor (D3), each of which has a data length of 8 bytes for the header (D1). It is defined that body (D2) = 8 × n bytes and tailor (D3) = 8 bytes.

Next, the extended storage device 1 is located as a storage hierarchy between the main storage device and an auxiliary storage device such as a magnetic disk device, and is used to buffer a difference in access time between the two. The extended storage device 1 according to the present embodiment includes an access control unit 4 having a length counter 11, a memory array unit 51 as an extended storage device in a narrow sense, and a data queue 5.
2. It has an access pipeline 53.

The access control unit 4 having the length counter 11 is a so-called direct memory access (D
MA), in addition to the length counter 11, an address register for specifying the address of the main memory;
The length counter 11 and the address register are updated each time an input / output operation of one word (here, an 8-bit transfer unit) is completed, so that the main memory is continuously stored independently of the central processing unit (CPU). Area and the memory array unit 51
And data transfer between them. Writing to the memory array unit 51 is performed by an interleave method.

The access control unit 4 determines whether the transfer data to be written or the data currently being written is the header (D1) or the body (D2) from the value of the counter 11 of the length counter 11,
3) A data type detecting means 41 for identifying the type is provided. The data type detecting means 3 is composed of the data type detecting means 41 and the length counter 11.

That is, the length counter 11 counts the data length, and the data type detecting means 41 determines that the data being written is a header (D
1) Whether it is a body (D2) or a tailor (D3). That is, the data length of the data transferred in this embodiment is as follows: header (D1) = 8 bytes, body (D1)
2) Since 8 × n bytes and tailor (D3) = 8 bytes are defined, the length counter 11 uses 8 bytes as the minimum unit of counting, and counts 1 when 8 bytes are read.

When the access control unit 4 receives a write command from the central processing unit (CPU), the access control unit 4 sets the transfer length (X bytes) sent from the central processing unit (CPU) to 8 Is set in the length counter 11.

Since the header (D1) is defined as 8 bytes, the body (D2) is defined as 8 × n bytes, and the tailor (D3) is defined as 8 bytes, it corresponds to the first count value “1” of the data. The write data to be written can be identified as the header (D1). During the writing of the body (D2), the counter 11 is decremented by one each time 8 bytes are written. When the value of the counter 11 becomes "1", it is confirmed that the writing of the body (D2) has been completed. While the last unwritten data is tailored (D3)
Can be identified.

Further, based on the data identification result by the data type detecting means 41, the access control section 4 sends an interlock signal for stopping data writing and a cancel signal for releasing the writing stop to the access pipeline. A write control unit 42 for sending the data to the write control unit 53 is provided. The write control unit 42 monitors the memory array unit 51 and detects certain machine check conditions that cause a write error. The monitoring information is constantly received as a machine check report from the memory array unit 51, and the machine check report is sent to the central processing unit (C
PU).

The memory array 51 includes a plurality of banks (B
N) and used for so-called interleaving. The data queue 52 is a data buffer register and temporarily holds data to be transferred from the main storage to the memory array unit 51.

The access pipeline 53 connects the data queue 52 and the memory array unit 51 and performs writing to the memory array unit 51 by so-called pipeline processing. Then, the writing process can be stopped and restarted in response to the interlock signal and a cancel signal for canceling the writing stop.

Hereinafter, an operation example of the apparatus of this embodiment will be described. First, a write instruction from the central processing unit (CPU) is performed by sending a specific hardware instruction code, a start address, and a transfer length to the extended storage. This instruction is sent to the access control unit 4 of the extended storage device 1. First, the transfer length transmitted at a predetermined timing is set in the length counter 11.

Here, when a write command is issued, the central processing unit (CPU) places a header (D1) having the same contents and a tailor (D) before and after data to be a body (D2).
3) is given in a length of 8 bytes. This header (D1)
And the contents of the tailor (D3) are updated to new contents for each write command.

Here, it is assumed that the data length of the body (D2) is 24 bytes. Therefore, the total data length is 40
40/8 = 5 bytes because the transfer unit is 8 bytes
Is set in the length counter 11 as an initial value.

First, as shown in FIG. 4, since the first write unit is the header (D1), the write control unit 42 sends an interlock signal to the access pipeline 53,
The write access of the body (D2) is stopped.

At this time, the value of the length counter 11 is decremented by "1", and the value of the counter 11 becomes "4".
When the header (D1) is written into the first bank (BN) of the memory array unit 51, a write finish signal indicating the end of the writing is returned from the memory array unit 51 to the access control unit 4.

Upon receiving the write finish signal, the write control unit 42 sends an interlock cancel signal to the access pipeline 53. Then, as shown in FIGS. 4-1, -2, and -3, the writing of the body (D2) is started, the writing process is performed in parallel for each writing unit of 8 bytes, and at the same time, the length counter 11 is written for each writing unit. Is subtracted by one,
The counter value becomes “1”.

At this time, since the access of each write unit is performed in parallel by the interleave mechanism, the write access is speeded up. When the content of the length counter 11 becomes "1", an interlock signal for stopping the subsequent access is sent from the write control unit 42 to the access pipeline 53 again, and the write access of the tailor (D3) is stopped. Then, upon receiving a write finish signal indicating that all writing of the body (D2) to the memory array unit 51 is completed, the write control unit 42 sends an interlock cancel signal to the access pipeline 53.

Then, as shown in FIG. 4, the tailor (D
The writing of 3) is performed. If a machine check condition is detected during the write access of the header (D1), the body (D2), and the tailer (D3), the write processing is interrupted at that point and the machine check is performed on the central processing unit (CPU). An interrupt is reported, or the central processing unit (CPU) invokes the machine's recovery program. When this interrupt occurs, during the write process,
The unprocessed write unit waiting for writing is cleared.

When the writing of the header (D1), the body (D2) and the tailer (D3) is completed, a write processing completion report is sent from the access control unit 4 to the central processing unit (CPU). Receives this and sends the next write command to the access control unit 4.

As described above, the header (D1) and the body (D
2) Each write of the tailor (D3) is performed by one write command from the central processing unit (CPU), and the header (D1), the body (D2), and the tailer (D3) are sequentially written in this order. . Therefore, the header (D
1) Only writing of tailor (D3) is performed in order,
The situation where the writing of the body (D2) fails does not occur. In writing individual data, parallel processing by interleaving is performed. However, as described above, since the header (D1) and the tailor (D3) are the minimum write units, there is no meaning in parallel processing. Since at least the writing of the body (D2) is performed in parallel processing for each writing unit (for each bank (BN)), the processing speed is increased.

By the way, access to the extended storage device 1 generally takes a much longer time than a normal instruction because of various checks and activation processing until the actual data transfer operation is started. is there. This time is required each time an instruction to the extended storage is issued.

Therefore, the header (D1) and the body (D
2) If the writing of the tailor (D3) is executed by three instructions, the result is that the central processing unit (CPU) is restrained for a long time. On the other hand, in the above example, the header (D1),
The writing of a series of data of the body (D2) and the tailor (D3) can be performed by one instruction, and the access can be speeded up by the parallel processing of the interleaving.

[0054]

According to the present invention, the validity of data writing based on the coincidence between the header and the tailor can be surely confirmed. In addition, the speeding up of processing for interleaving is not hindered. Write header, body and tailor
Since a single instruction can be used instead of one instruction, a series of writing processes can be performed quickly and the processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 shows an embodiment of the present invention.

FIG. 3 is a configuration diagram of transfer data.

FIG. 4 is a diagram showing write control according to the present invention;

FIG. 5 illustrates interleaving.

[Explanation of symbols]

 (CPU) Central processing unit (BN) Bank (D1) Header (D2) Body (D3) Tailor 1 (51) Storage device (extended storage device) 2 Write command generation unit 3 Data identification unit 4 Write control unit (Access control unit) 11) Data length holding means (length counter) 31 Main storage device 41 Data type detecting means 42 Write control unit 51 Memory array unit, 52 Data queue 53 Access pipeline

Claims (6)

(57) [Claims] 1. A method of writing data to a storage device (1) divided into a plurality of banks (BN) by an interleave method, and a header having the same contents before and after a body (D2) as data to be written. (D1) and tailor (D3) are added, and header (D1) and tailor (D3) are added.
In a storage control method that guarantees the validity of the body (D2) by checking the match of the above, a write instruction instructing to write the header (D1), the body (D2), and the tailor (D3) to the storage device (1) with one instruction Command generation means (2) for sending out the data, data identification means (3) for distinguishing a header (D1), body (D2), and tailor (D3) in data to be written; and the write command generation means (2) In accordance with the write command from the header (D) by the data identification means (3).
1) a writing control means (4) for controlling writing to the storage device (1) with reference to the distinction between the body (D2) and the tailor (D3). The writing control means (4) Until the writing of (D1) is completed, the body (D2) and the tailor (D3)
Is stopped, the writing of the body (D2) is started after the writing of the header (D1) is completed, and the writing of the tailor (D3) is stopped.
After the end of the writing of 2), the tailor (D3) is written, and at least the body (D
A writing control method for a storage device, wherein the writing in 2) is performed by an interleave method. 2. The header (D1) and the tailor (D3) each have a data length with the width of one bank as a minimum write unit, and the data identification means (3) is provided in a storage device (1). A data length holding means (11) for holding a data length of data to be written; and a detecting means (41) for detecting that the data is one immediately before the beginning and the end of the writing unit. ) Stores the data length that is the sum of the lengths of the header (D1), body (D2), and tailor (D3) to be written, and the detecting means (41) stores the data length holding means (1).
In view of the data length held in 1), the head of the writing unit is identified as the header (D1), and the last 1 of the writing unit is identified.
By detecting the last position, the last is determined to be the tailor (D3), and the writing control means (4) sets the detection means (41)
The writing of the body (D2) and the tailor (D3) is stopped until the writing of the header (D1) is completed, and the writing of the body (D2) is started after the writing of the header (D1) is completed, with reference to the detection result of. With the tailor (D
2. The write control method for a storage device according to claim 1, wherein the write operation of the storage device is stopped, and the write operation of the tailor is performed after the write operation of the body is completed. 3. The data length holding means (11) holds, as an initial value, a value obtained by dividing a data length by a minimum writing unit, and the detection means (41) holds the data length holding means (1).
The write control means (4) discriminates the header (D1), the body (D2), and the tailor (D3) based on the value held in 1).
While referring to the detection result of (1), the writing of the subsequent data (body (D2) and tailor (D3)) is stopped until the data writing of the first writing unit (header (D1)) is completed. Is completed, the value held in the data length holding means (11) is decremented by "1". Then, after the writing of the header (D1) is completed, the writing of the body (D2) is started and the interleave method is used. Write and body (D2)
Each time the data writing of the writing unit is completed during the writing of the data, the value held in the data length holding means (11) is subtracted by "1", and the value held in the data length holding means (11) is subtracted. 3. The storage device according to claim 2, wherein the writing is stopped when the value becomes "1", and after the writing of the body (D2) is confirmed to be completed, the writing of the tailor (D3) is started. Write control method. 4. The data length holding means (11) comprises a length counter (11) comprising a register, and the detection means (41) comprises a length counter (1).
4. The storage device according to claim 3, wherein whether the data to be written is a header (D1), a body (D2), or a tailor (D3) is determined from the value of 1). Write control method. 5. The write control method for a storage device according to claim 1, wherein said storage device (1) is an extended storage device (1). 6. The write command generating means (2) is constituted by a central processing unit (CPU), and the write control means (4) is formed independently of the central processing unit (CPU), 6. The write control method for a storage device according to claim 1, wherein an access method is realized.