JPH0535526A - Target program debugging system - Google Patents

Abstract

PURPOSE:To attain a target program debugging system of high efficiency by providing debug interruption generating bit to an executing instruction operand of a debugged program end turning on end off control the corresponding bit with the debug control processing CONSTITUTION:A host computer 1 includes an instruction execution control mechanism 20 and 8 debug interruption generating mechanism 30 together with a debugged program 10 stored in 8 main program, end a debug control processor 40. Each instruction of the program 10 consists of an instruction code (OP code) and an operand which partly holds a debug interruption generating bit. A means which can set the ON/OFF states of a debug bit sets the debug bit of the operand in the ON/OFF states to the corresponding instruction when the debug information is acquired. Then a means which informs a debug control program of the generation of a debug interruption. Thus the debug control is attained without reproducing the program 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for debugging a target program, and more particularly to a target program debug method for executing debugging on a host computer without creating a program to be debugged for debugging.

[0002]

2. Description of the Related Art In a conventional debugging method using a host computer, an execution program after debugging is completed is recreated because a debug designation is made when creating an execution program for a program to be debugged. Alternatively, for the target address of the program to be debugged, the relevant instruction is replaced with an indefinite instruction code to intentionally generate an exception, and then the original instruction is executed on behalf of the debug control program.

[0003]

In the above-mentioned conventional debugging method, it is necessary to specify debug for the target program to be debugged at the time of creating the execution format program (at the time of compiling), and create the execution program again after the completion of debugging. It requires time and effort such as reworking. Alternatively, the execution instruction is replaced with an indefinite instruction, and the instruction execution is performed by the debug control program, so that there is a problem that the efficiency at the time of debugging is low.

An object of the present invention is to provide a target program debugging method which solves the above-mentioned problems and which does not require the execution of instruction execution by rewriting an indefinite instruction without recreating a debugged program.

[0005]

According to the debugging method of the present invention, when a program to be debugged is debugged in a host computer having a debug function of a target program, an interrupt for debugging is added to an operand of each instruction for executing the program. The debug control program has a mechanism to provide a debug bit to generate, and when the debug control program acquires the debug information at the target instruction or target address of the program to be debugged, the debug bit of the operand for the corresponding instruction is necessary. And a means for setting ON / OFF and a means for notifying the debug control program of the occurrence of a debug interrupt after the execution of the instruction when the instruction with the debug bit turned on is executed by the means for setting the ON / OFF. The target program It is characterized in that without also controlling the debugging efficiently to fix.

[0006]

The means for setting the debug bit on / off in the target program debugging method of the present invention is to set the debug bit of the operand to the instruction at the time of acquiring debug information to generate a debug interrupt. Is notified to the debug control program and the instruction execution end is notified and restored, so that debug control can be performed without recreating the program to be debugged.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is an overall configuration diagram of a target program debug system showing an embodiment of the present invention.

FIG. 2 is a diagram showing an example of the debugged program instruction format of the present invention.

FIG. 3 is a flow chart of the debug information setting process of the present invention.

FIG. 4 is a flow chart of the debug information search process of the present invention.

FIG. 5 is a flow chart of processing of the debug information restoration processing of the present invention.

In FIG. 1, the host computer 1 includes an instruction execution control mechanism 20 and a debug interrupt generation mechanism 30.
And includes a program to be debugged 10 and a debug control process 40 on the main memory. As shown in FIG. 2, each instruction of the debugged program 10 is composed of an instruction code (OP code) and an operand, and a debug interrupt generation bit is held in a part of the operand.

The operation of the embodiment of the debugging method of the program to be debugged 10 will be described below in order with reference to FIGS. 3, 4 and 5. (1) Debug information setting will be described with reference to FIG.

In the debug information setting process of the debug control process 40, in order to collect the debug information necessary for the program to be debugged 10, the target instruction (or address) is acquired.
, The target address information group is acquired in advance to set the interrupt display for debugging (step ST5).
0). In the debug information setting process (for example, as a parameter of the debug control process 40), the debug interrupt generation bit of the operand of the corresponding instruction is turned on according to the acquired target address (step ST51).

This makes it possible to collect debug information during instruction execution. (2) Debug Information Retrieval Process Referring to FIG. 4, after the debug information is set, execution of the program to be debugged 10 is started. The instruction execution control mechanism 20 reads the instruction expanded in the main memory and executes the instruction (step ST60).

After the instruction is executed, if the debug interrupt generation bit is set (turned on) in the operand of the instruction (step ST61), the debug interrupt generation mechanism 30
Control is passed to the debug information search process of the debug control process 40 (step ST62). In the debug information search process, search, display, and content change are performed according to the debug parameters of the program to be debugged 10 held by the debug control process 40 such as register information and memory information at the time of interruption (step ST63).

Thereafter, the execution of the program to be debugged is restarted by returning to the point of time when the interrupt to the program to be debugged occurs. (3) Debug Information Restoration Processing Referring to FIG. 5, when the execution of the debugged program 10 is terminated (step ST70), the debugged program 1 is selected from the target address information group held by the debug control processing 40.
The instruction of which the debug interrupt generation display of 0 is turned on is approached, and the debug interrupt generation bit of the instruction is turned off (step ST71).

As a result, the debug interrupt occurrence display set in the debug information setting process is restored to the off state,
After that, the debug interrupt does not occur when the debugged program is executed.

[0020]

As described above, according to the present invention, a debug interrupt occurrence display is provided in the execution instruction itself, and this is turned on / off.
By turning it off, it is not necessary to recreate the program to be debugged, and it is not necessary to shoulder the instruction execution by rewriting it to an indefinite instruction in the debug control processing, so the effect that efficient debugging can be achieved is there.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a target program debug system showing an embodiment of the present invention.

FIG. 2 is a diagram showing an instruction format example of a program to be debugged according to the present invention.

FIG. 3 is a flow chart of processing of a debug information setting processing of the present invention.

FIG. 4 is a flow chart of a debug information search process of the present invention.

FIG. 5 is a flow chart of a debug information restoration process of the present invention.

[Explanation of symbols]

 1 host computer 10 debugged program 20 instruction execution control mechanism 30 debug interrupt generation mechanism 40 debug control processing.

Claims (1)

[Claims] 1. A host computer having a debug function for a target program, when debugging a program to be debugged, has a mechanism for providing a debug bit for generating an interrupt for debugging in an operand of each instruction for executing the program, In the debug control program, when acquiring debug information at the target instruction or target address of the program to be debugged, means for setting the debug bit of the operand for the relevant instruction to ON / OFF as necessary, When executing an instruction in which the debug bit is turned on by the means that can be set to ON / OFF, it has means for notifying the debug control program of the occurrence of a debug interrupt after execution of the instruction, and controlling the debugging of the target program. Characterized target program Debug system.