JPH053546A - Image reader and image information processor provided with the same - Google Patents

Abstract

PURPOSE:To completely eliminate a difference in signal level generated by dispersion in the offset voltages of plural image sensors by removing the offset voltage of a buffer amplifier for signal output. CONSTITUTION:SW are inputted to the gates of MOS transistors(Tr) 66 and 67 at a sensor chip 1 and simultaneously, a phiRES is inputted to the gate of an MOS Tr 62. Since a horizontal output line 61 is reset according to a phiRES 1 by a Tr 62 each time the Tr 66 is turned on and one picture element signal is outputted, signals from a picture element 21 to a picture element 31 of the sensor chip 1 are successively read through a buffer amplifier 64 to a signal output line 65. Simultaneously, the Tr 67 is turned on, and a reset voltage VRES is outputted through a buffer amplifier 65 to a reference line output 9. Since the buffer amplifiers 64 and 65 are produced in the same sensor chip, the offset voltage is equal. Therefore, the offset voltage is eliminated in a signal outputted from a differential amplifier 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus for reading image information using a multi-chip type image sensor composed of a plurality of image sensors and an image information processing apparatus equipped with the image reading apparatus. .

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing a configuration of a conventional multi-chip type image sensor. In the figure, 101
Numerals to 106 are sensor chips constituting a multi-chip image sensor, and 107 is a module substrate on which each sensor chip is mounted. The output of each sensor chip is output to the output line 108, and is output to the outside from the output terminal 111 via the buffer amplifier 110. FIG. 12 is a diagram showing the internal configuration of each sensor chip, 21 to 31 are pixels for photoelectrically converting incident light, and 41 to 51 are switches for selecting an output signal from the signals obtained by the pixels. Is. Further, 61 is a horizontal output line for outputting each pixel signal,
62 is a MOS transistor for resetting the horizontal output line, 64 is a buffer amplifier, and 66 is a MOS transistor for selecting a sensor chip.

Next, the operation of reading pixel signals from the multichip image sensor will be described with reference to the time chart shown in FIG. First, a high-level SW is applied to the gate of the MOS transistor 66 in the sensor chip 101.
1 is input, and each pixel signal of the sensor chip 101 is sequentially output to the output line 108. At this time, φRES1 that is at a high level is input to the gate of the MOS transistor 62 during the signal output of each pixel, and the horizontal output line 61 is reset every time one pixel signal is output. As a result, signals are sequentially read from the pixel 21 to the pixel 31 of the sensor chip 101, and when the last signal is read, SW1 is inverted to the low level, SW2 rises to the high level, and the MOS transistor in the sensor chip 102 is turned on. It is input to the gate of 66. Further, since φRES2 is input to the gate of the MOS transistor 62 in the sensor chip 102, the signals of each pixel of the sensor chip 102 are sequentially read in the same manner. Thereafter, the signals of the pixels of the sensor chips 103 to 106 are similarly read out, and as a result, the pixel signals of the entire sensor chip are read out to the output terminal 111 as shown as out 'in the figure.

[0004]

However, in the above-mentioned conventional image sensor, the buffer amplifier 64 of each sensor chip has an offset voltage, and the offset voltage varies from one sensor chip to another. Therefore, as indicated by out 'in FIG. 13, there is a problem that the output signal of each sensor chip has a step due to the variation of the offset voltage, and the S / N of the image sensor is lowered.

The present invention has been made in order to solve such a problem, and its purpose is to completely eliminate the step of the signal level caused by the variation of the offset voltage of a plurality of image sensors, and An object of the present invention is to provide an image reading apparatus having an improved S / N of a sensor and an image information processing apparatus including the image reading apparatus.

[0006]

SUMMARY OF THE INVENTION The object of the present invention is to provide an image reading apparatus having a multi-chip type image sensor including a plurality of image sensors, the signal output provided to each of the plurality of image sensors. And a means for removing the offset voltage of the buffer amplifier for use in the image sensor, so that the level difference of the output signal between the image sensors is removed.

[0007]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of an image reading apparatus of the present invention, and FIG. 2 is a circuit diagram showing the internal configuration of each sensor chip. 1 and 2, the same parts as those of the conventional device are designated by the same reference numerals, and the description thereof will be omitted in this embodiment. In the figure, 1 to 6 are sensor chips of an image sensor, respectively. Here, a multi-chip type image sensor is composed of six sensor chips. Each sensor chip is mounted on the module substrate 7. Further, 8 is a signal output line for outputting a signal of each pixel, 9 is a reference output line for outputting a reference signal, and a pixel signal and a reference signal from each sensor chip are paired to these two output lines. Is output. The pixel signal and the reference signal output to the signal output line 8 and the reference output line 9 are input to the two input terminals of the differential amplifier 10, and the pixel signal and the reference signal are differentiated to output from the output terminal 11 to the outside. Is output to. As shown in FIG. 2, a buffer amplifier 65 for outputting a reference signal and a MOS transistor 67 for selecting a sensor chip are provided inside each sensor chip. The MOS transistor 67 is the aforementioned MOS
The transistor 66 has a common gate, and the two transistors are simultaneously turned on and off. The reset voltage V _RES is output to the input of the buffer amplifier 65, and this voltage is output to the negative input terminal of the differential amplifier 10 via the buffer amplifier 65. The other structure of the sensor chip is the same as the conventional one shown in FIG.

Next, the operation of this embodiment will be described with reference to FIG. Note that the subject has uniform brightness over the entire screen. First, SW1 is input to the gates of the MOS transistors 66 and 67 of the sensor chip 1, and at the same time, φRES1 is input to the gate of the MOS transistor 62 of the sensor chip 1. As a result, the MOS transistor 66 is turned on, and the horizontal output line 61 is reset each time the MOS transistor 62 outputs one pixel signal by φRES1.
The signals from 1 to the pixel 31 are sequentially read out to the signal output line 8. At the same time, the MOS transistor 67 is turned on,
The reset voltage V _RES is output to the reference output line 9. Therefore, the pixel signal read to the signal output line 8 is output to the in-phase input of the differential amplifier, and the reset voltage V _RES of the reference output line 9 is output to the differential input. In this case, the signal read out to the signal output line 8 is output via the buffer amplifier 64 and therefore includes the offset voltage thereof, and the other reset voltage is also included in the buffer amplifier 6.
Since it is output via 5, it contains the same offset voltage. Since the buffer amplifiers 64 and 65 are manufactured in the same sensor chip, the offset voltage is the same. Therefore, the offset voltage is removed from the signal output from the differential amplifier 10, and only the signal corresponding to the original incident light can be read. When all the pixel signals of the sensor chip 1 are read out, SW2 is input to the gates of the MOS transistors 66 and 67 of the next sensor chip 2, and the pixel signal of the sensor chip 2 is reset to the signal output line 8 as described above. The voltage is output to each reference output line 9. As a result, a signal in which the offset voltage of the buffer amplifier is removed from the output of the differential amplifier 10 can be obtained as in the above. Hereinafter, similarly, the sensor chips 3 to 6 are sequentially selected by the signal SW for selecting the sensor chips, and the signal from which the offset voltage is removed is output for each sensor chip. FIG. 3 shows the signal of each sensor chip read out to the signal output line 8. As is clear from the figure, the sensor read signal is changed to the sensor due to the variation of the offset voltage of the buffer amplifier 64 of each sensor chip. It can be seen that there is a step between the chips. On the other hand, the reference output line 9
It can be seen that the reference voltage output to the same has the same step as shown in FIG. Therefore, the differential amplifier 1
The signal output from 0 has the offset voltage of the buffer amplifier removed for each individual sensor chip as shown as a differential output in the figure, and the step difference in the signal between the chips can be completely removed.

FIG. 4 is a block diagram showing another embodiment of the present invention. In this embodiment, the sensor chips 1 to 6 have the same structure as that shown in FIG. In FIG.
Reference numeral 70 is a signal output line for reading out signals from the odd-numbered sensor chips, and 71 is a signal output line for reading out signals from the odd-numbered sensor chips. Therefore, the odd-numbered sensor chips 1,
The signals of 3, 5 are read out on the signal output line 70, and the signals of the even-numbered sensor chips 2, 4, 6 are read out on the signal output line 71, respectively. 72 and 73 are clamp capacitors corresponding to the signal output lines 70 and 71, respectively, and 74 and 75 are M for clamping the signal output lines 70 and 71 to the clamp potential V _CL.
It is an OS transistor. Reference numerals 76 and 77 are buffer amplifiers for outputting the signals read out to the respective signal output lines, and 78 and 79 are MOS transistors for selectively outputting the outputs of the buffer amplifiers 76 and 77.

Next, the operation of this embodiment will be described with reference to FIG. First, the signal of the sensor chip 1 is first read. In this reading, φ to the gate of the MOS transistor 62 is read before the signal of the first bit is read, that is, before the signal of the leading pixel 21 shown in FIG. 12 is read.
SW to the gate of RES1 and MOS transistor 66
1 is turned on. As a result, the sum of the reset voltage V _RES and the offset voltage V _OFF1 of the buffer amplifier 64 (V _RES + V _OFF1 ) is output to the signal output line 70 (see FIG. 12). At this time, as shown in FIG. 5, φCLO (high level) is input to the gate of the MOS transistor 74 and the MOS transistor 74 is turned on, so that the input voltage of the buffer amplifier 76 is clamped to the clamp voltage V _CL . After that, since φCLO is turned off and φRES1 is input to the MOS transistor 62, the horizontal output line 61 is reset every time one pixel signal is output,
The signals of the pixels of the sensor chip 1 are sequentially read out to the signal output line 70. In this case, since the input of the buffer amplifier 76 is in a floating state and SW0 (high level) is input to the gate of the MOS transistor 78, an output signal including the offset voltage of the buffer amplifier 78 is output to the output terminal 11. It This output signal V _OUT is expressed by the following equation.

V _OUT = V _CL + V _SIG + V _OFF0 (1) where V _CL is the clamp voltage, V _SIG is the pixel signal level,
V _OFF0 is the offset voltage of the buffer amplifier 78.

On the other hand, when the reading of the sensor chip 1 approaches the end, the MOS transistor 62 of the sensor chip 2
ΦRES2 and SW2 of the MOS transistor 66 are turned on, and the sum of the reset voltage V _RES and the offset voltage V _OFF2 of the buffer amplifier 64 is output to the signal output line 71. At this time, since φCLE is turned on, the MOS transistor 75 is turned on, and the buffer amplifier 77 is turned on as described above.
Is clamped to the clamp voltage V _CL . When the reading of the signal from the sensor chip 1 is completed, SW1 and φRES
1 is turned off, and the MOS transistor 6 of the sensor chip 2
2 is applied to φ2, and the pixel signals of the sensor chip 2 are sequentially read out to the signal output line 71. At this time, SW0
Turns off and SWE turns on to turn on the MOS transistor 79, so that the pixel signal of the sensor chip 2 is output to the outside via the buffer amplifier 77. Buffer amplifier 7
When the offset voltage of 7 is V _OFFE , the output signal V _OUT output from the output terminal 11 is expressed by the following equation.

V _OUT = V _CL + V _SIG + V _OFFE (2) where V _CL is a clamp voltage and V _SIG is a pixel signal of the sensor chip 2.

When the signal reading of the sensor chip 2 approaches the end, the input voltage of the buffer amplifier 76 is clamped by the same operation as described above, and the signal reading of the next odd-numbered sensor chip 3 is prepared. Then, when all the signals of the sensor chip 2 are output, the reading of the signals of the sensor chip 3 is started, and as the end is approached, the input voltage of the buffer amplifier 76 of the next even-numbered sensor chip 4 is clamped. . Similarly, before reading each sensor chip, the input voltage of the corresponding buffer amplifier is clamped to a constant voltage, and the odd-numbered sensor chip and the even-numbered sensor chip are next. The chips are read out alternately. In this case, the output voltage does not include the offset voltage of the buffer amplifier 64 in the sensor chip as shown in the equations (1) and (2). That is, the buffer amplifiers 76, 7 are forced to be read before the signal is read
Since the input of 7 is clamped to a constant voltage, the offset voltage in the sensor chip does not appear in the output voltage.
As indicated by UT, the step difference of the output signal caused by the variation in the offset voltage of the sensor chip can be completely removed. The buffer amplifiers 76 and 77
Of the difference in the offset voltage, the output signal | V _OFF0
There is a level difference of −V _OFFE │, but this can be made extremely small, so there is no problem.

FIG. 6 is a block diagram showing still another embodiment of the present invention. In the figure, 80 is a memory for storing the offset voltage of the buffer amplifier of each sensor chip,
Reference numeral 81 indicates the memory 8 based on the signals read from each sensor chip.
The differential amplifier subtracts the offset voltage stored in 0. The structure of the sensor chip in this embodiment is the same as that shown in FIG. Further, here, an example in which an image sensor is configured by four sensor chips is shown.

Next, the operation will be described with reference to FIG. First, a start pulse SP for instructing the sensor chip 1 and the memory 80 to read out a signal and a clock pulse CLK for synchronizing when the output signal of the image sensor is read out.
Is entered. Then, SW1 input to the gate of the MOS transistor 66 in the sensor chip 1 and φRES1 input to the gate of the MOS transistor 62 simultaneously rise to the high level for a predetermined time. As a result, the offset voltage of the buffer amplifier 64 is output from the sensor chip 1 to the signal output line and stored in the memory 80. When this is completed, SW2 and φRES2 rise to the high level, and the buffer amplifier 64 of the sensor chip 2 is driven as described above.
Offset voltage is stored in the memory 80. Hereinafter, similarly, the offset voltages of the sensor chip 3 and the sensor chip 4 are sequentially stored in the memory 80, and when the storage of all the offset voltages is completed, SW1 becomes high level to read the signal of the sensor chip 1, and φRES1 becomes Turn on,
Each is given to the MOS transistor of the sensor chip 1. As a result, the signals of the respective pixels of the sensor chip 1 are sequentially read out and input to the in-phase terminal of the differential amplifier 81 as in the above-described embodiment. On the other hand, the offset voltage of the sensor chip 1 stored in the memory 80 is input to the differential terminal of the differential amplifier 81, and the differential amplifier 81 outputs a signal obtained by subtracting the offset voltage from the sensor output. Sensor chip 1
When the signal of the last pixel is output, the sensor chip 1 outputs the end pulse 1E to the next sensor chip 2 and the memory 80, and the signal reading of the sensor chip 2 is instructed. This instruction causes SW2 to go high, and φRES
2 is turned on, the M in the sensor chip 2 is the same as above.
The OS transistor is driven, and the signal of each pixel of the sensor chip 2 is sequentially read. The memory 80 also outputs the offset voltage of the sensor chip 2 in response to the end pulse 1E, and the differential amplifier 81 outputs a signal obtained by subtracting the offset voltage from the output signal of the sensor chip 2. Hereinafter, similarly, every time the signal reading of one sensor chip is completed, an end pulse is output to the next sensor chip, and the signals of the sensor chip 3 and the sensor chip 4 are sequentially read. Further, since the offset voltage corresponding to the sensor chip is output from the memory 80, the differential amplifier 81 outputs a signal from which the offset voltage is removed for each sensor chip. As a result, it is possible to completely eliminate the signal step due to the variation in the offset voltage of the buffer amplifier of each sensor chip, as indicated by OUT in FIG.

FIG. 8 shows a further improved example of the embodiment shown in FIG.
This is an example in which SP and CLK are input to the counter 82, and the offset voltage corresponding to the sensor chip is read from the offset voltage stored in the memory 80 according to the instruction of the counter 82. In this embodiment, since it is not necessary to extract the end pulse from each image sensor, the structure of each sensor can be simplified accordingly.

FIG. 9 is an equivalent circuit diagram corresponding to one pixel of the above-described embodiment. PS is a bipolar transistor forming a pixel, SW ₁ is an NMOS transistor as a switch means for resetting by connecting the emitter to the reference voltage source V _ES , and SW ₂ is reset by connecting the base to the reference voltage source V _BB. Is a PMOS transistor as a switching means for switching, SW ₃ is an NMOS transistor as a switching means for signal charge transfer, and CT is a fixed load for generating a signal voltage. The operation will be briefly described below. <Reset Operation> First, a negative pulse voltage is applied to the gate of the PMOS transistor SW ₂ so that the base has the voltage V _BB.
Clamped to. Next, the NMOS transistor SW ₁
A positive pulse voltage is applied to the gate of the emitter to connect the emitter to the voltage source V _ES , a current flows between the base and the emitter, and photogenerated carriers remaining in the base disappear. <Storage Operation> Both the NMOS transistors SW ₁ and SW ₃ are turned off, both the emitter and the base are floated, and the storage operation is started. <Read Operation> Next, a positive pulse voltage is applied to the gate of the NMOS transistor SW ₃ to turn it on, the emitter and the capacitor CT are connected, and the signal voltage is read to the capacitor CT. The basic structure of such an image sensor is described in U.S. Pat. No. 4,686, issued to the inventors Omi and Tanaka.
No. 554 or the like describes a charge storage type high-sensitivity, low-noise photoelectric conversion device in which an emitter of a bipolar transistor is connected to an output circuit including a capacitive load. [Other Embodiments] In the first, second and third embodiments described above, the charge storage / amplification type image sensor using the bipolar transistor has been described. However, the present invention uses a photodiode as a light receiving portion and a MOS switch. Also, it can be preferably applied to a sensor of a type that transfers a signal charge by a charge coupled device (CCD) or the like. The image sensor as shown in FIG. 1 is a contact type image in which a housing formed of Al or the like is integrally assembled with a light source such as an LED array or an imaging optical system such as a short-focus imaging element array. Configure a sensor unit.

FIG. 10 shows a sensor unit 20 according to this example.
An example of a facsimile having a communication function as an image information processing apparatus configured by using 0 will be shown. Here, 202 is a feeding roller as a feeding means for feeding the original PP toward the reading position, and 204 is a separating piece for surely separating and feeding the original PP one by one. Reference numeral 206 is provided at the reading position with respect to the sensor unit 200,
The platen roller serves as a conveying unit that regulates the surface to be read of P and conveys the document PP. In the illustrated example, P is a recording medium in the form of a roll paper, and the image information read by the sensor unit 200 or the image information transmitted from the outside in the case of a facsimile machine or the like is reproduced here. Reference numeral 210 denotes a recording head as recording means for performing the image formation, which includes a thermal head,
Various types such as an inkjet recording head can be used. The recording head may be of a serial type or a line type. Reference numeral 212 denotes a platen roller as a conveying unit that conveys the recording medium P to the recording position of the recording head 210 and regulates the recording surface thereof.

Reference numeral 220 denotes an operation panel provided with a switch for accepting an operation input as an input / output means, a message, and a display section for notifying the state of the apparatus. Reference numeral 230 denotes a system control board as a control unit, which includes a control unit (controller) that controls each unit, a drive circuit (driver) for the photoelectric conversion element, a processing unit (processor) for image information, a transmission / reception unit, and the like. 240 is a power supply for the apparatus.

As the recording means used in the image information processing apparatus of the present invention, those whose typical constitutions and principles are disclosed in, for example, US Pat. Nos. 4,723,129 and 4,740,796 are preferable. According to this method, at least one of the electrothermal converters arranged corresponding to the sheet or liquid path holding the liquid (ink) gives a rapid temperature rise corresponding to the recorded information and exceeding the nucleate boiling. By applying a drive signal, heat energy is generated in the electrothermal converter, causing film boiling on the heat-acting surface of the recording head, and as a result, there is a one-to-one correspondence with the drive signal to generate bubbles in the liquid (ink). It is effective because it can be formed. The liquid (ink) is ejected through the ejection openings by the growth and contraction of the bubbles to form at least one droplet. Furthermore, as a full line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording device,
A combination of a plurality of recording heads as disclosed in the above specification may be used to satisfy the length or as a single recording head integrally formed.

In addition, the ink can be attached to a replaceable chip type recording head that can be electrically connected to the apparatus main body and can be supplied with ink from the apparatus main body by being mounted on the apparatus main body or the recording head itself. The present invention is also effective when a cartridge type recording head in which a tank is integrally provided is used.

[0023]

As described above, according to the present invention, it is possible to completely eliminate the step difference in the signal between the image sensors which is caused by the variation in the offset voltage of each image sensor, and the S / N ratio of the image sensor is reduced. There is an effect that it can be remarkably improved as compared with the conventional one.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an image reading apparatus of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of the image sensor of the embodiment of FIG.

FIG. 3 is a time chart showing the operation of the embodiment of FIG.

FIG. 4 is a configuration diagram showing another embodiment of the image reading apparatus of the present invention.

5 is a time chart showing the operation of the embodiment of FIG.

FIG. 6 is a configuration diagram showing still another embodiment of the image reading apparatus of the present invention.

FIG. 7 is a time chart showing the operation of the embodiment of FIG.

FIG. 8 is a configuration diagram showing an example in which the embodiment of FIG. 6 is further improved.

FIG. 9 is an equivalent circuit diagram showing a circuit corresponding to one pixel of the image sensor.

FIG. 10 is a configuration diagram showing an embodiment of an image information processing apparatus of the present invention.

FIG. 11 is a configuration diagram showing a conventional multi-chip image sensor.

12 is a circuit diagram showing an internal configuration of the image sensor of FIG.

FIG. 13 is a time chart showing the operation of the conventional sensor of FIG.

[Explanation of symbols]

1-6 Sensor chip (image sensor) 8 signal output line 9 Reference output line 10,81 differential amplifier 21 to 31 pixels 62, 66, 67, 74, 75 MOS transistors 64,65,76,77 buffer amplifier 80 memory 200 sensor unit 202 Feed roller 206 Platen roller 210 recording head

Claims (6)

[Claims] 1. An image reading apparatus provided with a multi-chip type image sensor including a plurality of image sensors, further comprising means for removing an offset voltage of a signal output buffer amplifier provided in each of the plurality of image sensors. An image reading device characterized in that a level difference of an output signal between image sensors is removed. 2. The removing means has a buffer amplifier for reading a reference signal to each image sensor, and a reference signal output from the buffer amplifier and a signal output from each image sensor. 2. The image reading apparatus according to claim 1, wherein the offset voltage of the signal output buffer amplifier is removed by taking the difference between the signals output via the buffer amplifier. 3. The removing means includes means for alternately reading out signals of a plurality of image sensors at odd-numbered and even-numbered signals, and a buffer amplifier for outputting the odd-numbered and even-numbered sensor signals, respectively. The offset voltage of the signal output buffer amplifier in the image sensor is removed by clamping the input voltage of the buffer amplifier to a constant voltage before reading the signal of the corresponding image sensor. Image reading device. 4. The removing unit has a memory for storing an offset voltage of a signal output buffer amplifier of each image sensor, and when the signal of the image sensor is read, a corresponding offset voltage is read from the memory, 2. The image reading apparatus according to claim 1, wherein the offset voltage of the signal output buffer amplifier is removed by taking the difference from the signal of FIG. 5. The image reading apparatus according to claim 1, document holding means for holding a document carrying image information at a reading position by the image reading apparatus, and image information read by the image reading apparatus. An image information processing apparatus provided with an image reading device, which comprises: a recording unit for recording 6. The image information processing apparatus having an image reading apparatus according to claim 5, wherein the recording means is a recording head that records by ejecting ink by using thermal energy.