JPH05347628A - Ring form lan - Google Patents

Abstract

PURPOSE:To arrange phases of each of line data read by a slave station independently of the connection state of plural slave stations. CONSTITUTION:The ring form LAN consists of a master station generating a frame and repeating a recovered frame and of slave stations relaying the frame. A frame generated by the master station has a data new/old flag (m flag) in a slot, the master station has a function of setting the m-flag in the case of repeating the frame, and a slave station 306 uses an m-flag reset means 404 to reset the m-flag at data write. Moreover, an m-flag monitor 401, a selection gate 402 and a delay device 403 implement delay quantity control of output data in response to the m-flag thereby arranging the phases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ring LAN for performing digital data communication by time division multiplexing using a ring data transmission medium.

[0002]

2. Description of the Related Art A LAN for electronic musical instruments has been considered in which a plurality of electronic musical instruments are connected to a ring type transmission medium to perform mixing and the like. Data communicated on such a LAN for electronic musical instruments include setup information, performance information, audio sampling signals, and the like. Time-division multiplex LAN (TDMA) is a method that enables simultaneous communication of these data.
A hybrid LAN using a time division multiplex LAN is known. The former is a typical circuit switching method, and a common sampling clock can be transmitted in a network by a clock expressed in a frame period. The latter is a typical method of a multimedia LAN considering two uses of circuit switching / packet switching. By using this method, the management of circuit switching slots is performed by packet switching L.
It can be easily controlled by the AN.

TDMA only provides multiple lines of constant speed. The data of each line on one frame is
It may be an old sample time depending on the ring connection status. This situation will be specifically described with reference to FIG. As shown in FIG. 11 (a), a master station 1 having a sampling clock source for frame generation is connected to a node N1, a recording device 2 is connected to a node N2, and a node N is connected.
It is assumed that playback devices 3 and 4 are connected to 3 and N5 to form a network. The recording device 2, the reproducing device 3, and 4 are slave stations that drop / insert frame data. Now, the audio data CH1 and CH2 are written and transmitted to the lines to which the two reproducing devices 3 and 4 are assigned, the main station 1 repeats the frame while rewriting the time, and the recording device 2 reads the respective line data. The operation of recording shall be performed. The data transfer direction of the network is as indicated by the arrow.

In the connection state of FIG. 11 (a), the frame read by the recording device 2 has its time updated by the main station 1. Therefore, as shown in FIG. 11 (b), the data CH1 and CH2 are recorded.
Both are data that are delayed in the orbit, and there is no problem in the same phase. When the recording device 2 is connected to the node N6, both the data CH1 and CH2 are the data at the current time.
In this case as well, there is no problem as it is in the same phase. However, the situation is different when the recording device 2 is connected to the node N4 between the reproducing devices 3 and 4 as shown by the broken line in FIG. In this case, the frame data read by the recording device 2 is the data C from the reproducing device 3 as shown in FIG.
While H1 is the data at the current time, the data CH2 from the reproducing device 4 on the same frame is the old data which was delayed at the previous cycle and was written at the previous time. It should be noted that the position on the network where the recording device 2 is connected is not determined in advance. In this way, depending on the connection state of the slave station, the fact that data with a round-trip delay and data without a delay are mixed means that, for example, in high-performance applications such as studio applications, when aligning the phases between lines or in sample units. This is a problem when performing start / stop control.

[0005]

As described above, in the conventional ring type LAN, there is a possibility that data having a round-trip delay in the frame and data not having the same in the frame may coexist depending on the connection state of the node, resulting in phase shift. It becomes a problem. An object of the present invention is to provide a ring-type LAN in which line data read by slave stations are phase-aligned regardless of the connection state of a plurality of slave stations.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a ring type L is composed of a sole master station for generating frames and repeating collected frames, and a slave station for relaying the frames.
The frame generated by the master station in the AN is a data old / old flag (that is, a round-trip delay mark bit) in the slot
In addition, the master station has the function of setting the data old / new flag when repeating the frame, and the slave station has the function of resetting the data old / old flag when writing data to the assigned slot. It is characterized by having.

[0007]

According to the present invention, the slave station for reading data can determine the phase shift of each line data on the frame by referring to the data old and new flags.
Then, by controlling the delay amount of each line data on the basis of this determination result, it is possible to obtain outputs having the same phase.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a frame format in a ring LAN according to an embodiment of the present invention. In this system,
There are two types of frame formats, a data frame used for normal data communication and a PURGE frame used for maintenance when a failure occurs. As shown in the figure, the data frame includes a preamble (PA), a start delimiter (STD), a frame control (CTL), a usage status (USE), a data part (DATA), a frame check sequence (FCS), and an end data. Limiter (EDD)
It is composed of

The preamble (PA) is a bit used for synchronization with an input clock, correction of discontinuity due to frequency jitter, and the like. This pattern also appears in the gap between frames. The start delimiter (STD) indicates the beginning of the frame. The time when the start delimiter (STD) is received is the sampling time. The frame control (CTL) is a part set by the master station for frame control. As shown in FIG. 1, the frame type (Ftype),
It is composed of a frame ID (Fid) and an R / W flag. The frame type (Ftype) is DATA frame and P
Used to identify the URGE frame. Frame ID
(Fid) is a cyclic number attached to the DATA frame and represents the time measured by the clock φs. This is overridden by the PURGE frame. The R / W flag is used by the master station to instruct the slave station to read (R) or write (W), and substantially 2 frames are set.
It is used to orbit and align the phase of the read data at the slave station.

The usage status (USE) is a portion set by the main station for frame control, and is a template (for 16 slots) indicating allocation of each slot. Slot allocation includes the following. Packet slot (P-slot) Time-series data slot (R-slot) A slot for time-series data. The data format in the slot may be anything such as AES / ebu. By inputting a start / stop control signal here, start / stop control can be performed in sample units. Time-series data writing slot (R / W-slot) Used for dividing one line into a writing slot and a reading slot for phase alignment. Two consecutive samples for loading samples at the same time on one frame
It is the preceding slot of the slots. By inputting a start / stop control signal here, start / stop control can be performed in sample units. It is a slot which is paired with the time-series data writing slot (R / W-slot) on the time-series data reading slot (R / R-slot) and which follows the slot. R / W-slo in which the frame goes around the ring and is written in each slave station.
The contents of t are copied to this slot by the master station. Slot for time series data addition with mixing function (M
R / W-slot) This is a preceding slot of two consecutive slots for mixing time-series data on the network. Each slave station adds its own data to this content after performing necessary scaling. The data format in the slot in this case is, for example, AES / ebu. However, another format may be used as long as the addition can be easily performed. This slot follows the addition slot (MR / W-slot) on the time-series data reading slot (MR / R-slot) with a mixing function. The frame goes around the ring, and the contents of the MR / W-slot added at each slave station are copied to this slot by the master station.

Not all of the above slots are needed at the same time. In order to achieve the phase alignment of the time-series data, in this embodiment, a data old / old flag (m flag) is provided, and the delay amount control is performed based on the determination result of this m flag. Further, when the frame is circulated twice for one sampling period, that is, the writing orbit and the reading orbit, the m flag is not necessary. Also, 1 for one channel
It is also possible to allocate a writing slot and a reading slot separately in the frame and align the phases by the data copy operation of the main station. In that case, two consecutive slots are divided into a writing slot and a reading slot as in A method is used. Further, when performing mixing on the network, slot allocation such as, becomes necessary. These details will be described later.

The data part (DATA) is composed of 16 slots. As shown in FIG. 1, each slot has a data existence flag (f flag), data (data),
It is composed of a data old / old flag (m flag). The data new / old flag (m flag) is a flag indicating a round-trip delay used for phase alignment. This data old / new flag (m flag) is reset when the slave station writes data, and the master station sets it. It is possible to determine whether the data is data that is delayed by a revolution or the current data with respect to the time indicated by the frame ID (Fid), based on the data old and new flags “0” and “1”. In addition, so that the slots are evenly arranged on the frame,
For example, 16 slots are divided into two subslots of 8 bits each, 16 subslots for the lower 8 bits are arranged in the first half of the frame, and 16 subslots for the upper 8 bits are arranged in the latter half of the frame. It may be arranged. The frame sequence (FCS) is a CRC error check code for the entire data part. The end delimiter (EDD) indicates the end of the frame.

The PURGE frame is, as shown at the bottom of FIG. 1, the data portion (DATA) in the DATA frame.
There is no such thing.

The main configurations of the master station and the slave stations are as shown in FIGS. 2 and 3, respectively. In the case of this embodiment, the data transmission medium is an optical fiber, and the photoelectric conversion devices 201, 202, 3 are provided in the data input / output units of the master station and the slave stations.
01 and 302 are provided. The packet switching unit has the same configuration as the master station and the slave station and performs the same operation. That is, the input signal to the node input to the packet signal separation devices 203 and 303 is the template (USE) here.
The packet slot (P-slot described above according to the contents of
) The above signal is dropped, and the circuit switching units 206, 3
It is handed over to 06. The signal on the dropped packet slot (P-slot) is sent to the packet LAN controllers 204, 30 via a bit FIFO (not shown).
Put in 4 and the output from here is still a bit FIFO
A packet signal multiplexer 205 via a (not shown)
It is put in 305. Packet signal multiplexer 205,
In 305, the packet LAN controllers 204, 30
The signal sent from No. 4 is inserted into the packet slot (P-slot) of the signal passed from the circuit switching units 206 and 306, and output to the next node.

The circuit switching unit 206 of the main station has a slot monitor 207, a delay FIFO buffer 208, a default frame generator 209, a frame generator 211, a preamble generator 217, and a selection gate 216. The slot monitoring device 207 receives the input DAT
The slot of the A frame is monitored and the template (US
Depending on the contents of E), (a) the data old / old flag (m flag) is set to "1", (b) the R / W flag is inverted, (c) the time series data writing slot (R / W) -slo
t) is the time-series data reading slot (R / R-s
(d) Time-series data writing slot with a mixing function (MR / W-slot) that is copied to a lot).
R-slot) and then reset, that is, time-series data writing slot with mixing function (MR / W-s)
This is a part for selectively performing one of the processes such as writing an AES / ebu 0 level signal to the lot). Delay F
The IFO buffer 208 is a buffer that temporarily stores data for adjusting the ring circulation time so that the data is output from the slot monitoring device 207 every 20 μsec, for example.

The default frame generation device 209 is a device for generating the first frame, and is the frame generation device 2
Reference numeral 11 is a device for repeating the collected frames. The frame generation device 211 is composed of a clock counter 212 for obtaining a sampling clock φs and a frame ID (Fid) representing the current time, a selection gate 213, a template generation unit 214, and a time stamp unit 215. That is, the frame generation device 211 uses the selection gate 2
When the delay FIFO buffer 208 has not yet started storing data according to 13, the frame generated by the default frame generator 209 is taken out, and thereafter the delay FIFO is generated at the timing of the sampling clock φs.
Fetch frames from buffer 208. Then, the current slot usage status is checked by the template generation unit 214
Write to E and write the current time to Fid. The frame thus generated by the frame generator 211 is transferred to the next node via the selection gate 216 and the packet multiplexer 205. If there is no frame signal,
The preamble generator 217 is selected by the selection gate 216.
The preamble pattern generated by is selected and output.

The circuit switching unit 306 of the slave station is, as shown in FIG. 3, a time-series data slot (R-slot) reading device 307, and the time-series data read by the time-series data is transmitted in a time division manner. An output device 308, a time-series data slot (R-slot) writing device 310, a plurality of data input devices 309 for sequentially sending time-series data to be transmitted thereto, a timing generation device 311, and a phase alignment processing device 312. It A computer, an electronic musical instrument or the like is connected to the data output device 308 and the data input device 309 as terminals. The input DATA frame is passed in parallel to the reading device 307, the writing device 310, and the timing generation device 311. The timing generation device 311 uses the slot position timing in the frame for these devices to operate and the data output device 308.
And D / A timing for converting digital data into analog data, and A / D timing for converting analog data into digital data are generated by the data input device 309 and passed to each device. D / A timing is
The STD position of the data frame, that is, the sample output timing from the circuit switching unit 306, and the A / D timing is the EDD position of the data frame, that is, the circuit switching unit 306.
Is the sample input timing to. The phase alignment processing device 312 is a part that performs necessary processing by monitoring the m flag and the R / W flag in order to align the phases of the data with the round trip delay and the data without the round trip delay, the details of which will be described later. ..

The above description is an outline of the basic configuration and operation of the ring LAN according to the embodiment of the present invention. Next, the method (first method) of phase alignment of each line data according to this embodiment will be specifically described. In the first method, the delay amount of each line data is controlled by using the data old / new flag (m flag) described above. Figure 3 in this case
The functional configuration of the circuit switching unit 306 of the slave station shown in FIG. That is, the slot writing device 310
Then, an m flag resetting means 404 for resetting the m flag (m = 0) at the same time when writing the data from the data input device 309 is provided. Further, an m flag monitoring device 401 is provided at the output section of the slot reading device 307, and a selection gate 402 controlled by this is provided, so that it remains unchanged when m = 1 and 1 sample when m = 0. It is configured to send data to the data output device 308 via a delay circuit 403 that provides a delay of minutes. On the other hand, the main station has a function of setting the m flag of a frame passing through it (m = 1). This is performed by the slot monitoring device 207 of the main station in FIG.

The phase alignment achieved by this method will be described below with reference to FIG. Now, it is assumed that the recording device 2 which is one of the slave stations is connected to the node N4 as shown by the broken line. The frame generated or repeated by the master station 1 is transferred to the node N3, and the data CH1 is written in the slot allocated by the reproducing apparatus 3 there. At this time, m =
The m flag set to 1 is reset. When this frame is transferred to the node N4 and this slot data CH1 is read by the recording device 2, since m = 0, a one sample time delay is given. Further, the same frame is transferred to the node N5, and the data CH2 is written in the slot assigned to it by the reproducing apparatus 4. In this case as well, a reset of m = 0 is similarly performed.
And this frame returns to the main station 1 and the time is updated,
At the same time, the m flags of all slots are set to 1 and sent out. When this is transferred to the node N4 and the recording device 2 reads the slot data CH2, since m = 1, no delay is given. In this way, in this method, other line data is delayed and output in accordance with the line data having a circuit delay. Therefore, the output phases of the respective line data are the same regardless of the connection state of the master station and the slave station.

The second method for phase alignment is a method in which the DATA frame is rotated twice within the sample period using the R / W flag described above. The functional configuration of the circuit switching unit 306 of the slave station shown in FIG. 3 in this case is functionally as shown in FIG. That is, the R / W flag monitoring device 5
01 is provided and R / W = 0, the writing device 31
When only 0 is activated and R / W = 1, the reading device 30
Only 7 are activated. On the other hand, the main station has a function of rotating the DATA frame twice in one sample period and inverting the R / W flag of the DATA frame passing therethrough. The R / W flag inversion is shown in FIG.
Is performed by the slot monitoring device 207 of the master station.

The phase alignment according to the second method will be specifically described with reference to FIG. When the DATA frame generated by the master station 1 and set with the time and R / W = 0 is sent out, the playback devices 3 and 4 which are slave stations transmit the data CH1 and CH2 to the slots assigned to the frames, respectively. Write. In this first round of frames, only writing is permitted, and the recording device 2 cannot read anywhere. That DA
The TA frame is collected by the main station 1, inverted to R / W = 1, and transmitted again. In the second frame round, the slave station can only read, and the recording device 2 can read each slot data CH1 and CH2. That is, in this method, as shown in FIG. 6, the DATA frame is rotated twice during one sample period (20 μsec), and the write cycle and the read cycle are divided, so that the data between the line data on the same DATA frame is separated. There is no phase shift in.

The third method for phase alignment is a method in which the data transmission medium itself is duplicated to form a double ring type or a double bus type. The basic idea of dividing data writing and data reading is the same as the second method. FIG. 7 shows a network configuration example according to the third method.
Shown in (a) and (b). FIG. 8 shows the main station 70 used for these.
1 and the slave station 702. The main station 701 is provided with a frame generator 711, a transmission medium terminating unit 712, and a through path 713 for simply passing a data frame, and has a four-terminal configuration of A, B, C, and D.
In the slave station 702, the slot writing device 721 and the slot reading device 722 each have an input / output terminal.
It has a four-terminal configuration of b, c, and d.

FIG. 7A shows such a master station 701 and slave stations 7
This is an example of a double ring type using 02. Main station 701
The frame generated and transmitted by the transmission medium 703a
Is transmitted, and the writing device 721 of each slave station 702 sequentially writes data to the assigned slot. D was written around the network
The ATA frame is sent to the transmission medium 703b through the through path 713 of the master station 701. This transmission medium 70
In 3b, only the slot reading device 722 of each slave station 702 is connected in a ring shape, and the DATA frame of the second round is read by the slot reading device 722 in each slave station 702 as needed. The DATA frame that makes two rounds terminates at the master station 701.

According to this method, data is written in the first round of the DATA frame and read out in the second round, so that there is no phase shift between data on the same frame. In the above-mentioned second method in which one transmission medium makes two turns, the sampling frequency is doubled, whereas in this method in which the transmission medium itself is duplicated, the write operation in the first transmission medium 730a is performed. And the second transmission medium 730b
It is not necessary to increase the sampling frequency because the read operation can be performed in parallel. Further, according to this method in which the DATA frame is terminated at the main station and the frame repeat operation is not performed, since the main station can output the DATA frame by the drifting method, the above-mentioned ring circulation time adjustment becomes unnecessary. In addition, the influence of line jitter can be suppressed.

FIG. 7B shows the same master station 701 and slave station 70.
This is an example in which 2 is used to form a double bus type. In this case, the transmission medium 703a on the outward path of the DATA frame sent from the master station 701 is connected only to the writing device 721 of the slave station 702, and the transmission medium 703b on the inbound path is connected only to the reading device 722 of the slave station 702. In the slave station 702 farthest from the main station 701, the output terminal of the writing device 721 and the input terminal of the reading device 722 are short-circuited, and in the main station 701, the output terminal of the through path 713 is short-circuited to the terminal terminal. Also in this method, since writing is performed in the forward path and reading is performed in the backward path, there is no phase shift of data on the same DATA frame. Further, it is not necessary to increase the sampling frequency, and the same effect as that of the method of FIG. 7A can be obtained. Further, according to this method, the same operation can be obtained regardless of the connection positions of the master station 701 and the slave station 702, and thus there is an advantage that the connection positions of the respective stations can be freely set.

The fourth technique for phase alignment is DATA.
One line is divided into a writing slot and a reading slot on the frame. This is the time-series data writing slot R / W-slot and the time-series data reading slot R / R-slot described above, and two consecutive slots for writing the preceding slot are allocated to one line. The frame structure in this case is shown in FIG. At the main station, the DATA frame with the time attached is transmitted, and the DATA frame collected by going around the ring is
The contents of the write slot R / W-slot are copied to the read slot R / R-slot and the same frame is transmitted again. The slave station writes data in the write slot R / W-slot and reads data in the read slot R / R-slot. In this method, the DATA portion of the frame is doubled as compared with the conventional methods, and the frame length is increased accordingly. However, only the DATA portion is doubled, which is shorter than the second method described above in which one sampling period includes two frames including a preamble and the like. This method also separates writing from reading and eliminates the phase shift of each slot data on the frame. Also in this method, since the data write operation and the data read operation can be performed in parallel, it is not necessary to increase the sampling frequency.

Next, an embodiment of a LAN with a mixing function will be described. In most cases, the audio LAN will be a mixture of signals from several sound sources. Commonly known as a LAN for electronic musical instruments, channels are assigned corresponding to a plurality of sound sources, and the data transferred through these channels are read out and mixed by a mixer. However, it is not always necessary to provide a channel corresponding to each sound source if the individual data processing is not performed simply by mixing. In this embodiment, a plurality of data are mixed on the network by a method of sequentially adding data to a shared slot. In this case, as the method of reading and writing data, any of the above-described second method to fourth method can be used, but here, the case of using the fourth method will be described.

The DATA frame structure is as shown in FIG. 10 (a). This is basically the same as the frame structure shown in FIG. 9, with two consecutive slots as one line, the preceding slot as a time series data addition slot MR / W-slot with a mixing function, and the subsequent slots as Slot for reading time series data with mixing function MR / R-slo
I have t. Then, this one line is shared by a plurality of slave stations. When repeating the collected frame, the main station copies the contents of the addition slot MR / W-slot to the reading slot MR / R-slot and resets it. The functional configuration of the slave station is shown in FIG. 10 (b). In the slot addition / writing device 802, a common addition slot MR for the frame sent from the previous slave station is used.
/ W-slot is changed based on the data of its own station and added and written. The scaling unit 803 is a unit that multiplies the data of its own station by a coefficient. Actually, as shown in FIG. 3, data from a plurality of input devices are similarly time-divisionally added. Then, in the required slave station, the reader 801 goes around the ring once, and the addition and writing is performed in each slave station. This is the content of the read slot MR / R-slot copied by the master station, that is, mixed. Read the data. In addition, L with this mixing function
In the AN, it is preferable that the data expressed in binary is used so that the data is sequentially flowed to the network from the lower bit (LSB). This is because, in this case, when performing the addition writing, the operations can be sequentially performed in the bit arrival order, so that the time delay is reduced.

According to this method, by connecting a plurality of sound sources, effectors and the like to perform mixing on the network, it is not necessary to connect a separate mixer, and the required number of lines (the number of channels) can be effectively increased. Can be suppressed.

[0030]

As described above, in the ring type LAN according to the present invention, by providing the data old / new flag in the slot and controlling the delay amount based on the data old / old flag, it is possible to obtain an output having a uniform phase.

[Brief description of drawings]

FIG. 1 is a diagram showing a frame structure used in an embodiment of the present invention.

FIG. 2 is a diagram showing a main part configuration of a main station of the embodiment.

FIG. 3 is a diagram showing a main configuration of a slave station of the embodiment.

FIG. 4 is a diagram showing a functional configuration of a slave station when the first method of phase alignment is used.

FIG. 5 is a diagram showing a functional configuration of a slave station when the second method of phase alignment is used.

FIG. 6 is a diagram showing a DATA frame when the second method is used.

FIG. 7 is a diagram showing a network configuration when a third method of phase alignment is used.

FIG. 8 is a diagram showing a functional configuration of a master station and a slave station when the third method is used.

FIG. 9 is a diagram showing a frame structure when the fourth method of phase alignment is used.

FIG. 10 is a diagram for explaining an embodiment of a LAN with a mixing function.

FIG. 11 is a diagram for explaining a problem of a conventional ring LAN.

[Explanation of symbols]

201, 202, 301, 302 ... Photoelectric conversion device, 20
3, 303 ... Packet signal separation device, 204, 304 ...
Packet LAN controller, 205, 305 ... Packet signal multiplexer, 206 ... Main station circuit switching unit, 207 ...
Slot monitoring device, 208 ... Delay FIFO buffer, 2
09 ... Default frame generation device, 211 ... Frame generation device, 212 ... Clock counter, 213, 216 ... Selection gate, 214 ... Template generation device, 215 ... Time stamp device, 217 ... Preamble generation device, 3
06 ... slave station line switching unit, 307 ... slot reading device,
308 ... Data output device, 309 ... Data input device, 3
10 ... Slot writing device, 311 ... Timing generation device, 401 ... m flag monitoring device, 402 ... Selection gate,
403 ... Delay device, 404 ... m flag resetting means, 5
01 ... R / W flag monitoring device.

Claims (2)

[Claims] 1. A frame having a data new / old flag indicating a time delay in a data slot is generated and a recovered frame is repeated, and the frame is relayed to a main station which sets the data new / old flag at the time of repeat, A ring LAN, wherein a plurality of slave stations that reset the data old and new flags when writing data to the assigned slot are connected to a ring data transmission medium. 2. A LAN in which a master station for generating frames and repeating collected frames and a plurality of slave stations for relaying frames are connected to a ring-type data transmission medium, each master station comprising: Means for generating a frame having a data old / new flag indicating a time delay of data in the data slot,
And a slot monitoring means for setting the data new / old flag at the time of repeating the frame, the slave station monitors the data new / old flag at the time of reading slot data, and controls the data delay amount according to the result. And a means for resetting the data old / new flag when writing slot data.