JPH05347600A - Demodulating device for spread spectrum system - Google Patents

Demodulating device for spread spectrum system

Info

Publication number
JPH05347600A
JPH05347600A JP17768292A JP17768292A JPH05347600A JP H05347600 A JPH05347600 A JP H05347600A JP 17768292 A JP17768292 A JP 17768292A JP 17768292 A JP17768292 A JP 17768292A JP H05347600 A JPH05347600 A JP H05347600A
Authority
JP
Japan
Prior art keywords
clock signal
output
circuit
signal
demodulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17768292A
Other languages
Japanese (ja)
Other versions
JP2650572B2 (en
Inventor
Yukinobu Ishigaki
行信 石垣
Takahisa Matsumoto
卓久 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP17768292A priority Critical patent/JP2650572B2/en
Publication of JPH05347600A publication Critical patent/JPH05347600A/en
Application granted granted Critical
Publication of JP2650572B2 publication Critical patent/JP2650572B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To provide a spread spectrum SS demodulating device which can stably perform an angle demodulation with high S/N. CONSTITUTION:An inverse spread demodulating circuit 10 is provided to apply the inverse spread demodulation to the SS modulated wave for acquisition of an angle modulated wave together with a phase locked loop type angle demodulating circuit 13 which demodulates the angle modulated wave, a frequency divider 20 which applies the 1/N frequency division to the output of a VCO 17 included in the circuit 13 to obtain a clock signal, a PNG 18 which produces a demodulating spread code based on the clock signal to supply the spread code to the circuit 10, a clock signal generator 21 which produces a synchronous catching clock signal between the carrier frequency and a spread code clock signal, a switch circuit Sw which selects by switching between the synchronous catching clock signal and the spread code generating clock signal, a synchronism detecting circuit 23 which detects a synchronous catching point with the demodulation signal outputted from the circuit 13, and a synchronous catching signal generating part 33 which produces a synchronous catching signal with use of the output of a synchronism detecting circuit, the synchronous catching clock signal, and the spread code generating clock signal.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、1次変調用のキャリヤ
周波数と拡散符号用のクロック信号とが、互いに同期関
係にある同期型SS(スペクトル拡散)方式における復
調装置に係り、特に、同期捕捉を正確,確実に行えるよ
うに改良した復調装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator in a synchronous SS (spread spectrum) system in which a carrier frequency for primary modulation and a clock signal for a spread code are in a synchronous relationship with each other, and more particularly to a synchronous device. The present invention relates to a demodulator improved so that the acquisition can be performed accurately and surely.

【0002】[0002]

【技術的背景】最近のSS通信において、SS技術によ
る多元接続法を用いた移動体通信が実用域に達して来て
いる。周知の如く、電波資源は有限なので、周波数を有
効に利用する必要がある。その点、SS信号は広い周波
数帯域に拡散されて、変調波のパワースペクトル密度が
非常に小さいので、他の通信電波等に与える影響は小さ
く、既存の通信周波数帯での混用が可能になるため、そ
の面での効用が大きく、原理的に周波数利用効率の向上
に寄与できるものである。かかる理由により、SS方式
による無線通信も身近になりつつあり、今後、車両等に
搭載しての移動体間通信応用など、その将来性や発展性
を大きく嘱望されている。
TECHNICAL BACKGROUND In recent SS communication, mobile communication using a multiple access method by SS technology has reached a practical range. As is well known, since radio resources are limited, it is necessary to effectively use frequencies. In that respect, the SS signal is spread over a wide frequency band, and the power spectrum density of the modulated wave is very small, so that it has little influence on other communication radio waves and the like, and can be mixed in existing communication frequency bands. In that respect, the utility is great, and in principle, it can contribute to the improvement of frequency utilization efficiency. For this reason, wireless communication by the SS system is becoming more and more familiar, and in the future, there is great demand for its future potential and development such as application of communication between mobile bodies mounted on vehicles and the like.

【0003】[0003]

【従来の技術】SS無線通信において、受信における同
期捕捉と同期保持は基本的に必要なものであり、今まで
に種々の同期捕捉方法や保持方法が提案され実用化され
ている。その中で、変調時の1次変調である角度変調の
キャリヤ周波数と2次変調であるSS変調に用いられる
拡散符号用クロック信号とに、同期関係を持たせてSS
変調を行う同期型SS変調,復調方式も、受信後の復調
動作において回路構成を多少なりとも簡素化できる方式
として知られている。係るSS無線装置(通信機)につ
いて、図1等に示した先願の例を参照しながら説明す
る。
2. Description of the Related Art In SS wireless communication, synchronization acquisition and synchronization holding in reception are basically required, and various synchronization acquisition methods and holding methods have been proposed and put into practical use. Among them, the carrier frequency of the angle modulation which is the primary modulation at the time of modulation and the spread code clock signal used for the SS modulation which is the secondary modulation are synchronized with each other by the SS
The synchronous SS modulation and demodulation method for performing modulation is also known as a method that can simplify the circuit configuration to some extent in the demodulation operation after reception. The SS wireless device (communication device) will be described with reference to the example of the prior application shown in FIG.

【0004】先ず、図1にブロック構成を示す送信部1
においては、入力端子In1 より音声や情報等の信号S(t)
が角度変調回路25に供給され、ここで角度変調が行わ
れて角度変調信号f(t) を出力する。角度変調出力信号
f(t) は周波数f0 をキャリヤ周波数とする変調波で、
拡散変調用乗算器3とN分の1の分周を行う分周器4に
供給されている。この分周器4は、周波数fM (=
0 )のキャリヤ周波数を、拡散帯域幅Bを与える拡散
符号用クロック信号周波数fC にまで分周により下げる
ものである。
First, a transmitter 1 whose block configuration is shown in FIG.
, The signal S (t) such as voice or information is input from the input terminal In1.
Is supplied to the angle modulation circuit 25, where the angle modulation is performed and the angle modulation signal f (t) is output. The angle-modulated output signal f (t) is a modulation wave whose frequency f 0 is the carrier frequency,
It is supplied to the spreading modulation multiplier 3 and the frequency divider 4 that performs 1 / N frequency division. This frequency divider 4 has a frequency f M (=
The carrier frequency of f 0 ) is reduced by frequency division to the spread code clock signal frequency f C which gives the spread bandwidth B.

【0005】周波数fM と周波数fC との間には、fM
>fC なる関係がある。分周により得られたクロック信
号C(t)は拡散符号発生器(PNG)5に供給されて、そ
の出力として拡散変調用の拡散符号P(t)を得ている。角
度変調出力f(t) は、入力信号により周波数(又は位
相)偏移△fを与えられて出力されているが、その偏移
分△fは分周によりN分の1に下がるため、分周した角
度変調出力をクロック信号として用いても何等問題は生
じない。このようにして得られた拡散符号P(t)はLPF
(ローパスフィルタ)6を介して拡散変調用の乗算器3
に供給され、ここで上記角度変調信号f(t) との乗算に
よる拡散変調が行われ、その出力として同期型SS変調
波f(t)P(t) が得られ、送信アンテナ7より出力され
る。
Between the frequency f M and the frequency f C , f M
> F C. The clock signal C (t) obtained by the frequency division is supplied to the spread code generator (PNG) 5, and the spread code P (t) for spread modulation is obtained as its output. The angle-modulated output f (t) is output with the frequency (or phase) deviation Δf given by the input signal, and the deviation Δf is reduced to 1 / N by frequency division. There is no problem even if the angle-modulated output obtained by the rotation is used as the clock signal. The spread code P (t) thus obtained is the LPF
Multiplier 3 for spread modulation via (low-pass filter) 6
, Where spread spectrum modulation is performed by multiplication with the angle modulated signal f (t), and a synchronous SS modulated wave f (t) P (t) is obtained as its output, which is output from the transmitting antenna 7. It

【0006】このようにして、同期型SS変調波は送信
部1より電波となって、空気等の媒体を介して、他機の
受信部22へと伝送される。即ち、1台のSS無線通信
機は、図1に示した送信部1と図2に示す受信部22と
で構成され、アンテナ7,8は1本で兼務されている。
次に、受信部22の構成及び動作について、図2のブロ
ック構成図及び図3の信号波形図を併せ参照して説明す
る。
In this way, the synchronous SS modulated wave becomes a radio wave from the transmitting section 1 and is transmitted to the receiving section 22 of another device through a medium such as air. That is, one SS wireless communication device is composed of the transmitting unit 1 shown in FIG. 1 and the receiving unit 22 shown in FIG. 2, and the antennas 7 and 8 also serve as one antenna.
Next, the configuration and operation of the receiver 22 will be described with reference to the block diagram of FIG. 2 and the signal waveform diagram of FIG.

【0007】受信アンテナ8により受信された同期型S
S変調波f(t)P(t) には、第3者からの妨害波等のノイ
ズ成分n(t) が含まれているので、これを極力排除する
ために、BPF(バンドパスフィルタ)9により、SS
変調波f(t)P(t) のメインローブ以外の周波数成分を除
去してから、逆拡散復調用の乗算器10に供給する。
Synchronous S received by the receiving antenna 8
Since the S-modulated wave f (t) P (t) contains a noise component n (t) such as an interfering wave from a third party, in order to eliminate it as much as possible, a BPF (bandpass filter) is used. 9 by SS
The frequency components other than the main lobe of the modulated wave f (t) P (t) are removed and then supplied to the multiplier 10 for despread demodulation.

【0008】21は同期捕捉用のクロック信号を発生さ
せるクロック信号発生器であり、この同期捕捉用クロッ
ク信号C0 (t) をスイッチ回路Swを介してPNG18に
供給することにより同期捕捉用拡散符号ρ(t) を生成し
ており、この拡散符号ρ(t)をLPF19を介して上記
乗算器10に出力している。
Reference numeral 21 is a clock signal generator for generating a clock signal for synchronization acquisition. The synchronization acquisition clock signal C 0 (t) is supplied to the PNG 18 through the switch circuit Sw to thereby generate a synchronization acquisition spread code. ρ (t) is generated, and this spread code ρ (t) is output to the multiplier 10 via the LPF 19.

【0009】同期捕捉用クロック信号C0 (t) の周波数
fιは、正規のクロック信号C(t)の周波数fcに比較し
て僅かに異なるようにしている。これにより、乗算器1
0の出力は{f(t)P(t)+n(t)}ρ(t) となる。かかる乗
算出力は、BPF11にて逆拡散出力の周波数帯域以外
の周波数成分を除去され、図3(A) に示すような信号波
形となった後、リミターアンプ12を介して、位相同期
ループ型角度復調回路13を構成する位相比較器14に
供給される。
The frequency fι of the synchronization acquisition clock signal C 0 (t) is made slightly different from the frequency fc of the regular clock signal C (t). As a result, the multiplier 1
The output of 0 is {f (t) P (t) + n (t)} ρ (t). The multiplication output has frequency components other than the frequency band of the despreading output removed by the BPF 11 and has a signal waveform as shown in FIG. 3 (A). It is supplied to the phase comparator 14 which constitutes the demodulation circuit 13.

【0010】位相比較器14には、電圧制御発振器(V
CO)17からの角度変調波成分に同期したジッタの伴
ったVCO出力が供給されるので、ここで上記リミター
アンプ12出力との位相比較が行われ、増幅器15で適
宜増幅されて、図3(B) に示す如き波形の出力信号とな
る。この図から明らかなように、相関点T0 では雑音が
極度に下がるため同期検出が可能となる。相関点の周期
は、拡散符号周期数をnビットとすると、n/(fC
fι)で定まる時間Tpとなる。
The phase comparator 14 includes a voltage controlled oscillator (V
Since the VCO output accompanied by the jitter synchronized with the angle-modulated wave component from the CO) 17 is supplied, the phase comparison with the output of the limiter amplifier 12 is performed here, and it is amplified appropriately by the amplifier 15, and then, as shown in FIG. The output signal has a waveform as shown in B). As is clear from this figure, noise is extremely reduced at the correlation point T 0 , so that synchronization detection is possible. The period of the correlation point is n / (f C −, where the number of spreading code periods is n bits.
The time Tp is determined by fι).

【0011】かかる増幅器15(角度復調回路13)か
らの出力は、LPF24を介して端子Out より出力され
ると共に、同期検出回路23に供給される。同期検出回
路23では、図3(C) に示すような同期検出制御電圧を
生成してスイッチ回路Swに供給している。この図3(C)
においては、T0'は同期捕捉が行われていない状態を示
し、同期捕捉点tS 以降は同期が取れた状態を示してい
る。
The output from the amplifier 15 (angle demodulation circuit 13) is output from the terminal Out via the LPF 24 and is also supplied to the synchronization detection circuit 23. The synchronization detection circuit 23 generates a synchronization detection control voltage as shown in FIG. 3 (C) and supplies it to the switch circuit Sw. This Figure 3 (C)
In the figure, T 0 ' indicates a state in which synchronization acquisition is not performed, and indicates a state in which synchronization is achieved after the synchronization acquisition point t S.

【0012】一方、VCO17の出力は分周器20にも
供給され、ここでN分の1に分周してクロック信号C'
(t) を得ている。クロック信号C'(t) はジッタを含んで
おり、スイッチ回路Swにおいて同期検出回路23からの
同期検出制御電圧により切替えられて、PNG(拡散符
号発生器)18に供給される。PNG18で生成される
逆拡散復調用の拡散符号P'(t) は、BPF9からの入力
SS変調波の位相にほぼ一致しているが、ジッタの影響
及びその時のタイミングにより僅かな位相差が生じる。
このようにして僅かな位相差を含んだまま逆拡散復調が
行われ、位相同期ループ13によりSS同期の保持動作
が持続されることになる。
On the other hand, the output of the VCO 17 is also supplied to the frequency divider 20, where it is divided into 1 / N and the clock signal C '.
I'm getting (t). The clock signal C ′ (t) contains jitter, is switched by the synchronization detection control voltage from the synchronization detection circuit 23 in the switch circuit Sw, and is supplied to the PNG (spread code generator) 18. The spread code P '(t) for despread demodulation generated by the PNG 18 substantially matches the phase of the input SS modulated wave from the BPF 9, but a slight phase difference occurs due to the influence of jitter and the timing at that time. ..
In this way, the despreading demodulation is performed with a slight phase difference included, and the phase-locked loop 13 keeps the SS synchronization holding operation.

【0013】[0013]

【発明が解決しようとする課題】上記の従来のスペクト
ル拡散方式における同期捕捉装置は、同期捕捉動作時
に、クロック信号C0 (t) よりC'(t) に切替わるが、C'
(t) はジッタを伴っており、そのジッタの影響により切
替えタイミングにおいて僅かな位相差が生じるという欠
点がある。この位相差がその時のタイミングによりばら
つくと、そのばらつきに対応して自己相関特性が劣化
し、角度復調出力内に拡散符号成分が雑音となって生じ
る問題が発生する。この雑音はクロック周波数を拡散符
号の周期で割った値の周波数を主成分としているため、
クロック周波数や拡散符号周期の値の設定等から復調情
報周波数帯域内に雑音が生じるという問題があった。
The above-mentioned conventional synchronization acquisition device in the spread spectrum system switches from the clock signal C 0 (t) to C ′ (t) during the acquisition operation, but C ′ (t).
(t) is accompanied by jitter, and there is a drawback that a slight phase difference occurs at the switching timing due to the influence of the jitter. If this phase difference varies depending on the timing at that time, the autocorrelation characteristic deteriorates corresponding to the variation, and there arises a problem that the spread code component becomes noise in the angle demodulation output. The main component of this noise is the frequency of the clock frequency divided by the period of the spreading code.
There is a problem that noise is generated in the demodulation information frequency band due to the setting of the clock frequency and the value of the spread code period.

【0014】[0014]

【課題を解決するための手段】本発明は上記課題を解決
するために、SS変調波を逆拡散復調して角度変調波を
得る逆拡散復調回路と、角度変調波の復調を行う位相同
期ループ型角度復調回路と、この復調回路内のVCO(1
7)出力を1/Nに分周してクロック信号を得る分周器と、
クロック信号を基に復調用拡散符号を生成して逆拡散復
調回路に供給するPNGと、キャリヤ周波数と拡散符号
用クロック信号との同期捕捉用クロック信号を発生する
クロック信号発生器と、同期捕捉用クロック信号と上記
拡散符号生成用クロック信号とを切替え選択するスイッ
チ回路と、上記角度復調回路より出力される復調信号に
て同期捕捉点を検出する同期検出回路と、同期検出回路
出力と上記同期捕捉用クロック信号と上記拡散符号生成
用クロック信号とを用いて同期捕捉信号を生成する同期
捕捉信号生成部等を備えて構成したものである。
In order to solve the above problems, the present invention provides a despread demodulation circuit for despreading demodulating an SS modulated wave to obtain an angle modulated wave, and a phase locked loop for demodulating the angle modulated wave. Type angle demodulation circuit and VCO (1
7) A divider that divides the output by 1 / N to obtain a clock signal,
A PNG that generates a spreading code for demodulation based on the clock signal and supplies it to the despreading demodulation circuit, a clock signal generator that generates a clock signal for synchronizing the carrier frequency and the clock signal for the spreading code, and a synchronization capturing A switch circuit for switching and selecting a clock signal and the spread code generating clock signal, a synchronization detection circuit for detecting a synchronization acquisition point in the demodulation signal output from the angle demodulation circuit, a synchronization detection circuit output and the synchronization acquisition And a synchronization acquisition signal generation unit for generating a synchronization acquisition signal using the spread clock generation clock signal and the spread code generation clock signal.

【0015】また、同期捕捉信号生成部は、上記拡散符
号生成用クロック信号と同期捕捉用クロック信号とを論
理和演算して両信号の位相一致出力を検出する第1の A
NDゲートと、この ANDゲートの出力を波形整形する整形
回路と、上記同期検出回路出力より相関ピーク点に一致
するインパルス出力を得て上記整形回路の出力との論理
和演算を行う第2のAND(又はNAND)ゲートと、上記同期
検出出力を遅延させる時間遅延回路と、遅延して得られ
た遅延同期検出出力と上記第2のAND(又はNAND)ゲート
出力によりドライブされて上記スイッチ回路切替用の同
期捕捉信号を出力するRSフリップフロップとを備えて
構成している。即ち、本発明は前記SS無線装置(通信
機)における受信部(復調装置)の改良発明である。
Further, the synchronization acquisition signal generation section performs a logical sum operation of the spread code generation clock signal and the synchronization acquisition clock signal to detect a phase coincident output of both signals.
ND gate, a shaping circuit that shapes the output of this AND gate, and a second AND that performs an OR operation with the output of the shaping circuit by obtaining an impulse output that matches the correlation peak point from the output of the synchronization detection circuit. (Or NAND) gate, a time delay circuit for delaying the synchronization detection output, a delayed synchronization detection output obtained by delaying, and the second AND (or NAND) gate output for switching the switch circuit And an RS flip-flop that outputs the synchronization acquisition signal of. That is, the present invention is an improvement invention of the receiving unit (demodulation device) in the SS wireless device (communication device).

【0016】[0016]

【実施例】本発明のスペクトル拡散方式における復調装
置(以下「SS復調装置」とも記述する)の一実施例に
ついて、図4のブロック構成図及び図5の信号波形図
(タイミングチャート)を併せ参照しながら説明する。
図4中、26は ANDゲート、27は整形回路、28は時
間遅延回路、29はEX−ORゲート、30はNANDゲート、
31はインバータ、32はRSフリップフロップであ
り、以上の各回路により同期捕捉信号生成部33が構成
されている。なお、時間遅延回路28は、入力信号に対
して立上り部分は遅延させず、立下り時点だけを所定時
間遅延させる特性を有する。その他、この図において図
2に示した従来装置22と同一構成部分には同一符号を
付してその詳細な説明を省略する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the block diagram of FIG. 4 and the signal waveform diagram (timing chart) of FIG. 5, for an embodiment of the demodulation device (hereinafter also referred to as “SS demodulation device”) in the spread spectrum system of the present invention. While explaining.
In FIG. 4, 26 is an AND gate, 27 is a shaping circuit, 28 is a time delay circuit, 29 is an EX-OR gate, 30 is a NAND gate,
Reference numeral 31 is an inverter, 32 is an RS flip-flop, and the above-mentioned circuits form a synchronization acquisition signal generation unit 33. The time delay circuit 28 has a characteristic that the rising portion is not delayed with respect to the input signal, and only the falling time is delayed for a predetermined time. In addition, in this figure, the same components as those of the conventional device 22 shown in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

【0017】SS復調装置2のクロック信号発生器21
からスイッチ回路Swを介してPNG18に供給される同
期捕捉用クロックC0 (t) は、図5(A) に示すようなイ
ンパルス状に整形された信号であり、分周器20より出
力されるクロック信号C'(t)も図5(B) に示すインパル
ス状に整形された信号である。この両方のクロック信号
を ANDゲート26で ANDをとる(論理和演算する)と、
その出力は同図(C) に示すものとなる。即ち、分周器2
0より出力されているクロック信号C'(t) にはジッタが
含まれていても、両方のクロック信号の位相一致点が瞬
時的に存在するため、ゲート26出力は図5(C) 示のよ
うになるわけである。
Clock signal generator 21 of SS demodulator 2
The synchronization acquisition clock C 0 (t) supplied to the PNG 18 from the switch circuit Sw is a signal shaped into an impulse as shown in FIG. 5 (A), and is output from the frequency divider 20. The clock signal C '(t) is also an impulse-shaped signal shown in FIG. 5 (B). If both of these clock signals are ANDed by the AND gate 26 (OR operation),
The output is shown in Fig. 6 (C). That is, the frequency divider 2
Even if the clock signal C '(t) output from 0 contains jitter, the output point of the gate 26 is shown in Fig. 5 (C) because the phase matching point of both clock signals instantaneously exists. It will be like this.

【0018】このゲート出力は、クロック信号C0 (t)
の周波数fιとクロック信号C'(t)の周波数fC'との差
の周波数の逆数の時間間隔で生じるが、正確にはジッタ
による瞬時的な揺れが付加されるものとして得られる
{同図(D) のT2 の時間}。得られたゲート出力を更に
整形回路27で波形整形すると、その整形出力は同図
(D)に示すような矩形波になる。
The gate output is the clock signal C 0 (t).
Difference occurs at the time interval of the inverse of the frequency, precisely in {figure obtained as the instantaneous shaking due to the jitter is added is the 'frequency f C of the (t)' Frequency fι the clock signal C (D) T 2 time}. When the waveform of the obtained gate output is further shaped by the shaping circuit 27, the shaping output is shown in FIG.
It becomes a rectangular wave as shown in (D).

【0019】次の図5(E) は、前記図3(C) に対応する
同期検出回路23の同期検出制御電圧である。即ち、時
刻t1 からt3 の期間T0'のL(Low)レベルの期間と、
時刻t4 以降のLレベルの期間が同期検出時間となって
いる。この同期検出制御電圧は時間遅延回路28を通過
すると、その出力は図5(F) に示すものとなる。即ち、
時刻t1 より時刻t2 の期間が遅れてLレベルになり、
時刻t3 でH(High)レベルに復帰する動作となる。
The next FIG. 5 (E) shows the sync detection control voltage of the sync detection circuit 23 corresponding to FIG. 3 (C). That is, an L (Low) level period of time T 0 ′ from time t 1 to t 3 ,
The L-level period after time t 4 is the synchronization detection time. When this synchronization detection control voltage passes through the time delay circuit 28, its output becomes as shown in FIG. 5 (F). That is,
The period of time t 2 is delayed from time t 1 and becomes L level,
At time t 3 , the operation returns to H (High) level.

【0020】時間遅延回路28の入力と出力とをEX−OR
ゲート29に供給してゲート出力をとる(排他的論理和
演算をする)と、その出力は図5(G) に示すものとな
り、そのHレベルの部分のセンターが相関点のピーク
{図3(A) におけるピーク点}に一致させている。この
EX−ORゲート出力{同図(G) 参照}と整形回路出力{同
図(D) 参照}は同期捕捉にとって最も重要な検出信号と
なっており、この両方のAND{図4の構成例では回路動作
上NANDを使用}をとることにより、両信号の一致時に得
られる出力は、真の同期検出制御電圧(同期捕捉信号)
の基となる。
EX-OR the input and output of the time delay circuit 28.
When the gate output is supplied to the gate 29 (exclusive OR operation is performed), the output becomes as shown in FIG. 5 (G), and the center of the H level portion is the peak of the correlation point {FIG. 3 ( Peak point in A)}. this
The EX-OR gate output (see (G) in the figure) and the shaping circuit output (see (D) in the figure) are the most important detection signals for synchronization acquisition. The output obtained when both signals match is the true synchronous detection control voltage (synchronous acquisition signal)
Is the basis of

【0021】図5に示す動作例では、整形回路出力(D)
のT1 期間とEX−OR出力(G) のt1〜t2 期間は一致し
ておらず、NANDゲート30の出力は同図(J) の如く継続
してHレベルとなっており、整形出力(D) のT3 はEX−
OR出力(G) のt4 〜t7 と一致しており、従ってその期
間だけNANDゲート30の出力は同図(H) に示すようにL
レベルとなる。
In the operation example shown in FIG. 5, the shaping circuit output (D)
The T 1 period of the EX-OR output (G) does not coincide with the t 1 -t 2 period, and the output of the NAND gate 30 is continuously at the H level as shown in FIG. Output (D) T 3 is EX−
Coincides with t 4 ~t 7 of OR output (G), therefore as shown in the output drawing of NAND gate 30 (H) by the period L
It becomes a level.

【0022】更に、NANDゲート出力(H) を、時間遅延出
力(F) をインバータ31で位相反転した信号{同図(I)
参照}と共にRSフリップフロップ32に供給すること
により、その出力は同図(J) に示すものとなり、最終的
な同期検出制御電圧としてスイッチ回路Swに供給され
る。これにより、クロック信号はC0 (t) よりC'(t) に
切替えられて拡散符号発生器18に供給され、受信され
たSS変調波の中の拡散符号P(t)に一致する拡散符号P
(t)が得られる。
Further, a signal obtained by inverting the phase of the NAND gate output (H) and the time delay output (F) by the inverter 31 {(I) in the same figure)
By supplying it to the RS flip-flop 32 together with the reference}, its output becomes as shown in FIG. 9 (J), and is supplied to the switch circuit Sw as the final synchronization detection control voltage. As a result, the clock signal is switched from C 0 (t) to C ′ (t) and supplied to the spread code generator 18, and the spread code that matches the spread code P (t) in the received SS modulated wave. P
(t) is obtained.

【0023】これにより、乗算器10では本来の逆拡散
復調動作が達成され、その出力はf(t)P(t)P(t) +P(t)
n(t) となる。周知の如く、拡散符号同士の乗算分であ
るP(t)P(t)はほぼ1となる直流成分であるから、BPF
11の出力はf(t) +N(t)となる。なお、N(t) はP
(t)n(t) の帯域制限された拡散雑音成分で、その雑音
電力は大変小さいため、位相同期ループ型角度復調回路
13のVCO17の出力もジッタが大幅に下がり、位相
同期ループ型角度復調回路13でのSS同期保持も安定
に動作し、LPF24を介して出力端子Out から、ジッ
タ成分を殆ど含まない高品質の復調音声や復調情報が出
力される。
As a result, the original despread demodulation operation is achieved in the multiplier 10, and its output is f (t) P (t) P (t) + P (t).
n (t). As is well known, since P (t) P (t), which is a multiplication of spread codes, is a DC component that is almost 1, the BPF is
The output of 11 is f (t) + N (t). Note that N (t) is P
(t) n (t) is a band-limited spread noise component and its noise power is very small. Therefore, the output of the VCO 17 of the phase-locked loop type angle demodulation circuit 13 also has a greatly reduced jitter, and the phase-locked loop type angle demodulation The SS synchronization hold in the circuit 13 also operates stably, and high-quality demodulated voice and demodulation information containing almost no jitter component are output from the output terminal Out via the LPF 24.

【0024】[0024]

【発明の効果】本発明のSS方式における復調装置によ
れば、クロック信号発生器21,分周器20及び同期検
出回路23からの出力信号を基に論理演算を行いながら
同期検出制御電圧を得ており、VCOで発生するジッタ
により、ジッタの伴ったクロック信号に切替えても、瞬
時的にクロック信号の位相一致点を検出して相関点のセ
ンターと一致させて、得られた同期検出制御電圧により
切替えているので、同期捕捉後は常に最良の位相{入力
SS変調波を逆拡散復調するための生成拡散符号の位
相}に固定され、角度復調出力より洩れる拡散符号成分
は最少となり、S/Nの良好な角度復調が安定に達成さ
れるという優れた特長を有する。
According to the demodulator in the SS system of the present invention, the synchronization detection control voltage is obtained while performing the logical operation based on the output signals from the clock signal generator 21, the frequency divider 20, and the synchronization detection circuit 23. Therefore, even if the clock signal is switched to a jittery signal due to the jitter generated in the VCO, the phase detection point of the clock signal is instantaneously detected and coincides with the center of the correlation point. Since it is switched by, the fixed phase is always fixed to the best phase {the phase of the generated spread code for despread demodulating the input SS modulated wave} after the synchronization acquisition, and the spread code component leaked from the angle demodulation output is minimized. It has an excellent feature that good angle demodulation of N is stably achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来装置,本発明装置に信号を供給するSS変
調装置(送信部)のブロック図。
FIG. 1 is a block diagram of an SS modulator (transmission unit) that supplies a signal to a conventional device and the device of the present invention.

【図2】従来のSS復調装置のブロック構成図。FIG. 2 is a block configuration diagram of a conventional SS demodulation device.

【図3】従来装置の動作説明用信号波形図。FIG. 3 is a signal waveform diagram for explaining the operation of the conventional device.

【図4】本発明のSS復調装置の一実施例を示すブロッ
ク構成図。
FIG. 4 is a block diagram showing an embodiment of an SS demodulation device of the present invention.

【図5】本発明装置の動作説明用信号波形図(タイミン
グチャート)。
FIG. 5 is a signal waveform diagram (timing chart) for explaining the operation of the device of the present invention.

【符号の説明】[Explanation of symbols]

2 スペクトル拡散復調装置 3,10,14 乗算器(位相比較器) 4,20 分周器 5,18 PNG(拡散符号発生器) 6,19,24 LPF(低域濾波器) 7,8 アンテナ 9,11 BPF(帯域濾波器) 12 リミターアンプ 13 位相同期ループ型角度復調回路 15 増幅器 16 ループフィルタ 17 VCO(電圧制御発振器) 21 クロック信号発生器 23 同期検出回路 26 ANDゲート 27 整形回路 28 時間遅延回路 29 EX−ORゲート 30 NANDゲート 31 インバータ 32 RSフリップフロップ 33 同期捕捉信号生成部 Sw スイッチ回路 2 Spread spectrum demodulator 3,10,14 Multiplier (phase comparator) 4,20 Frequency divider 5,18 PNG (spread code generator) 6,19,24 LPF (low-pass filter) 7,8 Antenna 9 , 11 BPF (bandpass filter) 12 Limiter amplifier 13 Phase-locked loop type angle demodulation circuit 15 Amplifier 16 Loop filter 17 VCO (voltage controlled oscillator) 21 Clock signal generator 23 Synchronization detection circuit 26 AND gate 27 Shaping circuit 28 Time delay circuit 29 EX-OR gate 30 NAND gate 31 Inverter 32 RS flip-flop 33 Synchronization acquisition signal generation unit Sw switch circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】オーディオ信号やデータ等の情報信号を変
調するための、1次変調用キャリヤ周波数と拡散符号用
クロック信号とが同期関係にあるスペクトル拡散変調波
を、受信して復調するためのスペクトル拡散方式におけ
る復調装置であって、 受信スペクトル拡散変調波を入力して復調用拡散符号に
より逆拡散復調を行って角度変調波を得る逆拡散復調回
路と、得られた角度変調波を入力して角度復調を行う位
相同期ループ型角度復調回路と、該位相同期ループ型角
度復調回路内の電圧制御発振器より出力される電圧制御
発振出力を1/Nに分周して拡散符号生成用のクロック信
号を得る分周器と、該クロック信号を基に復調用拡散符
号を生成して上記逆拡散復調回路に供給する拡散符号発
生器と、上記キャリヤ周波数と拡散符号用クロック信号
との同期を捕捉するためのクロック信号を発生する同期
捕捉用クロック信号発生器と、該同期捕捉用クロック信
号と上記拡散符号生成用クロック信号とを切替え選択す
るスイッチ回路と、上記位相同期ループ型角度復調回路
より出力される復調信号より同期捕捉点を検出する同期
検出回路と、該同期検出回路出力と上記同期捕捉用クロ
ック信号と上記拡散符号生成用クロック信号とを用いて
同期捕捉信号を生成する同期捕捉信号生成部とを備え、
得られた同期捕捉信号により上記スイッチ回路を切替え
てスペクトル拡散同期捕捉をするよう構成したことを特
徴とする、スペクトル拡散方式における復調装置。
1. A spread spectrum modulated wave for modulating an information signal such as an audio signal or data, in which a carrier frequency for primary modulation and a clock signal for spread code are in a synchronous relationship for receiving and demodulating. A demodulator in a spread spectrum system, in which a received spread spectrum modulated wave is input, a despread demodulation circuit that performs an inverse spread demodulation using a demodulating spread code to obtain an angle modulated wave, and the obtained angle modulated wave are input. Phase-locked loop type angle demodulation circuit for performing angle demodulation and a clock for spreading code generation by dividing the voltage-controlled oscillation output output from the voltage-controlled oscillator in the phase-locked loop type angle demodulation circuit into 1 / N A frequency divider for obtaining a signal, a spreading code generator for generating a spreading code for demodulation based on the clock signal and supplying the code to the despreading demodulation circuit, the carrier frequency and a clock for the spreading code. Synchronization acquisition clock signal generator for generating a clock signal for acquiring synchronization with the signal, a switch circuit for switching and selecting the synchronization acquisition clock signal and the spread code generation clock signal, and the phase locked loop Synchronization detection circuit that detects a synchronization acquisition point from the demodulation signal output from the angle demodulation circuit, and a synchronization acquisition signal using the synchronization detection circuit output, the synchronization acquisition clock signal, and the spread code generation clock signal. And a synchronization acquisition signal generation unit for generating,
A demodulation device in a spread spectrum system, characterized in that the switch circuit is switched by the obtained synchronization acquisition signal to perform spread spectrum synchronization acquisition.
【請求項2】同期捕捉信号生成部は、拡散符号生成用ク
ロック信号と同期捕捉用クロック信号とを論理和演算す
ることにより,両信号の位相一致出力を検出する第1の
ANDゲートと、この ANDゲートの出力を波形整形する整
形回路と、上記同期検出回路出力より相関ピーク点に一
致するインパルス出力を得て上記整形回路の出力との論
理和演算を行う第2のAND(又はNAND)ゲートと、上記同
期検出出力を遅延させる時間遅延回路と、該遅延して得
られた遅延同期検出出力と上記第2のAND(又はNAND)ゲ
ート出力によりドライブされて上記スイッチ回路を切替
えるための同期捕捉信号を出力するRSフリップフロッ
プとを備えて構成したものである、請求項1記載のスペ
クトル拡散方式における復調装置。
2. A synchronization acquisition signal generation section for detecting a phase coincidence output of both signals by performing a logical sum operation of a spread code generation clock signal and a synchronization acquisition clock signal.
AND gate, a shaping circuit for shaping the output of the AND gate, and a second AND for performing an OR operation with the output of the shaping circuit by obtaining an impulse output that coincides with the correlation peak point from the output of the synchronization detection circuit. (Or NAND) gate, a time delay circuit for delaying the synchronization detection output, a delay synchronization detection output obtained by the delay, and the second AND (or NAND) gate output to drive the switch circuit. The demodulation device in the spread spectrum system according to claim 1, comprising an RS flip-flop that outputs a synchronization acquisition signal for switching.
JP17768292A 1992-06-12 1992-06-12 Demodulator in spread spectrum system Expired - Lifetime JP2650572B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17768292A JP2650572B2 (en) 1992-06-12 1992-06-12 Demodulator in spread spectrum system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17768292A JP2650572B2 (en) 1992-06-12 1992-06-12 Demodulator in spread spectrum system

Publications (2)

Publication Number Publication Date
JPH05347600A true JPH05347600A (en) 1993-12-27
JP2650572B2 JP2650572B2 (en) 1997-09-03

Family

ID=16035266

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17768292A Expired - Lifetime JP2650572B2 (en) 1992-06-12 1992-06-12 Demodulator in spread spectrum system

Country Status (1)

Country Link
JP (1) JP2650572B2 (en)

Also Published As

Publication number Publication date
JP2650572B2 (en) 1997-09-03

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