JPH05347600A - Demodulating device for spread spectrum system - Google Patents

Abstract

PURPOSE:To provide a spread spectrum SS demodulating device which can stably perform an angle demodulation with high S/N. CONSTITUTION:An inverse spread demodulating circuit 10 is provided to apply the inverse spread demodulation to the SS modulated wave for acquisition of an angle modulated wave together with a phase locked loop type angle demodulating circuit 13 which demodulates the angle modulated wave, a frequency divider 20 which applies the 1/N frequency division to the output of a VCO 17 included in the circuit 13 to obtain a clock signal, a PNG 18 which produces a demodulating spread code based on the clock signal to supply the spread code to the circuit 10, a clock signal generator 21 which produces a synchronous catching clock signal between the carrier frequency and a spread code clock signal, a switch circuit Sw which selects by switching between the synchronous catching clock signal and the spread code generating clock signal, a synchronism detecting circuit 23 which detects a synchronous catching point with the demodulation signal outputted from the circuit 13, and a synchronous catching signal generating part 33 which produces a synchronous catching signal with use of the output of a synchronism detecting circuit, the synchronous catching clock signal, and the spread code generating clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator in a synchronous SS (spread spectrum) system in which a carrier frequency for primary modulation and a clock signal for a spread code are in a synchronous relationship with each other, and more particularly to a synchronous device. The present invention relates to a demodulator improved so that the acquisition can be performed accurately and surely.

[0002]

TECHNICAL BACKGROUND In recent SS communication, mobile communication using a multiple access method by SS technology has reached a practical range. As is well known, since radio resources are limited, it is necessary to effectively use frequencies. In that respect, the SS signal is spread over a wide frequency band, and the power spectrum density of the modulated wave is very small, so that it has little influence on other communication radio waves and the like, and can be mixed in existing communication frequency bands. In that respect, the utility is great, and in principle, it can contribute to the improvement of frequency utilization efficiency. For this reason, wireless communication by the SS system is becoming more and more familiar, and in the future, there is great demand for its future potential and development such as application of communication between mobile bodies mounted on vehicles and the like.

[0003]

2. Description of the Related Art In SS wireless communication, synchronization acquisition and synchronization holding in reception are basically required, and various synchronization acquisition methods and holding methods have been proposed and put into practical use. Among them, the carrier frequency of the angle modulation which is the primary modulation at the time of modulation and the spread code clock signal used for the SS modulation which is the secondary modulation are synchronized with each other by the SS
The synchronous SS modulation and demodulation method for performing modulation is also known as a method that can simplify the circuit configuration to some extent in the demodulation operation after reception. The SS wireless device (communication device) will be described with reference to the example of the prior application shown in FIG.

First, a transmitter 1 whose block configuration is shown in FIG.
, The signal S (t) such as voice or information is input from the input terminal In1.
Is supplied to the angle modulation circuit 25, where the angle modulation is performed and the angle modulation signal f (t) is output. The angle-modulated output signal f (t) is a modulation wave whose frequency f ₀ is the carrier frequency,
It is supplied to the spreading modulation multiplier 3 and the frequency divider 4 that performs 1 / N frequency division. This frequency divider 4 has a frequency f _M (=
The carrier frequency of f ₀ ) is reduced by frequency division to the spread code clock signal frequency f _C which gives the spread bandwidth B.

Between the frequency f _M and the frequency f _C , f _M
> F _C. The clock signal C (t) obtained by the frequency division is supplied to the spread code generator (PNG) 5, and the spread code P (t) for spread modulation is obtained as its output. The angle-modulated output f (t) is output with the frequency (or phase) deviation Δf given by the input signal, and the deviation Δf is reduced to 1 / N by frequency division. There is no problem even if the angle-modulated output obtained by the rotation is used as the clock signal. The spread code P (t) thus obtained is the LPF
Multiplier 3 for spread modulation via (low-pass filter) 6
, Where spread spectrum modulation is performed by multiplication with the angle modulated signal f (t), and a synchronous SS modulated wave f (t) P (t) is obtained as its output, which is output from the transmitting antenna 7. It

In this way, the synchronous SS modulated wave becomes a radio wave from the transmitting section 1 and is transmitted to the receiving section 22 of another device through a medium such as air. That is, one SS wireless communication device is composed of the transmitting unit 1 shown in FIG. 1 and the receiving unit 22 shown in FIG. 2, and the antennas 7 and 8 also serve as one antenna.
Next, the configuration and operation of the receiver 22 will be described with reference to the block diagram of FIG. 2 and the signal waveform diagram of FIG.

Synchronous S received by the receiving antenna 8
Since the S-modulated wave f (t) P (t) contains a noise component n (t) such as an interfering wave from a third party, in order to eliminate it as much as possible, a BPF (bandpass filter) is used. 9 by SS
The frequency components other than the main lobe of the modulated wave f (t) P (t) are removed and then supplied to the multiplier 10 for despread demodulation.

Reference numeral 21 is a clock signal generator for generating a clock signal for synchronization acquisition. The synchronization acquisition clock signal C ₀ (t) is supplied to the PNG 18 through the switch circuit Sw to thereby generate a synchronization acquisition spread code. ρ (t) is generated, and this spread code ρ (t) is output to the multiplier 10 via the LPF 19.

The frequency fι of the synchronization acquisition clock signal C ₀ (t) is made slightly different from the frequency fc of the regular clock signal C (t). As a result, the multiplier 1
The output of 0 is {f (t) P (t) + n (t)} ρ (t). The multiplication output has frequency components other than the frequency band of the despreading output removed by the BPF 11 and has a signal waveform as shown in FIG. 3 (A). It is supplied to the phase comparator 14 which constitutes the demodulation circuit 13.

The phase comparator 14 includes a voltage controlled oscillator (V
Since the VCO output accompanied by the jitter synchronized with the angle-modulated wave component from the CO) 17 is supplied, the phase comparison with the output of the limiter amplifier 12 is performed here, and it is amplified appropriately by the amplifier 15, and then, as shown in FIG. The output signal has a waveform as shown in B). As is clear from this figure, noise is extremely reduced at the correlation point T ₀ , so that synchronization detection is possible. The period of the correlation point is n / (f _C −, where the number of spreading code periods is n bits.
The time Tp is determined by fι).

The output from the amplifier 15 (angle demodulation circuit 13) is output from the terminal Out via the LPF 24 and is also supplied to the synchronization detection circuit 23. The synchronization detection circuit 23 generates a synchronization detection control voltage as shown in FIG. 3 (C) and supplies it to the switch circuit Sw. This Figure 3 (C)
In the figure, T _{0 '} indicates a state in which synchronization acquisition is not performed, and indicates a state in which synchronization is achieved after the synchronization acquisition point t _S.

On the other hand, the output of the VCO 17 is also supplied to the frequency divider 20, where it is divided into 1 / N and the clock signal C '.
I'm getting (t). The clock signal C ′ (t) contains jitter, is switched by the synchronization detection control voltage from the synchronization detection circuit 23 in the switch circuit Sw, and is supplied to the PNG (spread code generator) 18. The spread code P '(t) for despread demodulation generated by the PNG 18 substantially matches the phase of the input SS modulated wave from the BPF 9, but a slight phase difference occurs due to the influence of jitter and the timing at that time. ..
In this way, the despreading demodulation is performed with a slight phase difference included, and the phase-locked loop 13 keeps the SS synchronization holding operation.

[0013]

The above-mentioned conventional synchronization acquisition device in the spread spectrum system switches from the clock signal C ₀ (t) to C ′ (t) during the acquisition operation, but C ′ (t).
(t) is accompanied by jitter, and there is a drawback that a slight phase difference occurs at the switching timing due to the influence of the jitter. If this phase difference varies depending on the timing at that time, the autocorrelation characteristic deteriorates corresponding to the variation, and there arises a problem that the spread code component becomes noise in the angle demodulation output. The main component of this noise is the frequency of the clock frequency divided by the period of the spreading code.
There is a problem that noise is generated in the demodulation information frequency band due to the setting of the clock frequency and the value of the spread code period.

[0014]

In order to solve the above problems, the present invention provides a despread demodulation circuit for despreading demodulating an SS modulated wave to obtain an angle modulated wave, and a phase locked loop for demodulating the angle modulated wave. Type angle demodulation circuit and VCO (1
7) A divider that divides the output by 1 / N to obtain a clock signal,
A PNG that generates a spreading code for demodulation based on the clock signal and supplies it to the despreading demodulation circuit, a clock signal generator that generates a clock signal for synchronizing the carrier frequency and the clock signal for the spreading code, and a synchronization capturing A switch circuit for switching and selecting a clock signal and the spread code generating clock signal, a synchronization detection circuit for detecting a synchronization acquisition point in the demodulation signal output from the angle demodulation circuit, a synchronization detection circuit output and the synchronization acquisition And a synchronization acquisition signal generation unit for generating a synchronization acquisition signal using the spread clock generation clock signal and the spread code generation clock signal.

Further, the synchronization acquisition signal generation section performs a logical sum operation of the spread code generation clock signal and the synchronization acquisition clock signal to detect a phase coincident output of both signals.
ND gate, a shaping circuit that shapes the output of this AND gate, and a second AND that performs an OR operation with the output of the shaping circuit by obtaining an impulse output that matches the correlation peak point from the output of the synchronization detection circuit. (Or NAND) gate, a time delay circuit for delaying the synchronization detection output, a delayed synchronization detection output obtained by delaying, and the second AND (or NAND) gate output for switching the switch circuit And an RS flip-flop that outputs the synchronization acquisition signal of. That is, the present invention is an improvement invention of the receiving unit (demodulation device) in the SS wireless device (communication device).

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the block diagram of FIG. 4 and the signal waveform diagram (timing chart) of FIG. 5, for an embodiment of the demodulation device (hereinafter also referred to as “SS demodulation device”) in the spread spectrum system of the present invention. While explaining.
In FIG. 4, 26 is an AND gate, 27 is a shaping circuit, 28 is a time delay circuit, 29 is an EX-OR gate, 30 is a NAND gate,
Reference numeral 31 is an inverter, 32 is an RS flip-flop, and the above-mentioned circuits form a synchronization acquisition signal generation unit 33. The time delay circuit 28 has a characteristic that the rising portion is not delayed with respect to the input signal, and only the falling time is delayed for a predetermined time. In addition, in this figure, the same components as those of the conventional device 22 shown in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

Clock signal generator 21 of SS demodulator 2
The synchronization acquisition clock C ₀ (t) supplied to the PNG 18 from the switch circuit Sw is a signal shaped into an impulse as shown in FIG. 5 (A), and is output from the frequency divider 20. The clock signal C '(t) is also an impulse-shaped signal shown in FIG. 5 (B). If both of these clock signals are ANDed by the AND gate 26 (OR operation),
The output is shown in Fig. 6 (C). That is, the frequency divider 2
Even if the clock signal C '(t) output from 0 contains jitter, the output point of the gate 26 is shown in Fig. 5 (C) because the phase matching point of both clock signals instantaneously exists. It will be like this.

The gate output is the clock signal C ₀ (t).
Difference occurs at the time interval of the inverse of the frequency, precisely in {figure obtained as the instantaneous shaking due to the jitter is added is the 'frequency f _C of the _(t)' Frequency fι the clock signal C (D) T ₂ time}. When the waveform of the obtained gate output is further shaped by the shaping circuit 27, the shaping output is shown in FIG.
It becomes a rectangular wave as shown in (D).

The next FIG. 5 (E) shows the sync detection control voltage of the sync detection circuit 23 corresponding to FIG. 3 (C). That is, an L (Low) level period of time T _{0 ′} from time t ₁ to t ₃ ,
The L-level period after time t ₄ is the synchronization detection time. When this synchronization detection control voltage passes through the time delay circuit 28, its output becomes as shown in FIG. 5 (F). That is,
The period of time t ₂ is delayed from time t ₁ and becomes L level,
At time t ₃ , the operation returns to H (High) level.

EX-OR the input and output of the time delay circuit 28.
When the gate output is supplied to the gate 29 (exclusive OR operation is performed), the output becomes as shown in FIG. 5 (G), and the center of the H level portion is the peak of the correlation point {FIG. 3 ( Peak point in A)}. this
The EX-OR gate output (see (G) in the figure) and the shaping circuit output (see (D) in the figure) are the most important detection signals for synchronization acquisition. The output obtained when both signals match is the true synchronous detection control voltage (synchronous acquisition signal)
Is the basis of

In the operation example shown in FIG. 5, the shaping circuit output (D)
The T ₁ period of the EX-OR output (G) does not coincide with the t ₁ -t ₂ period, and the output of the NAND gate 30 is continuously at the H level as shown in FIG. Output (D) T ₃ is EX−
Coincides with t ₄ ~t ₇ of OR output (G), therefore as shown in the output drawing of NAND gate 30 (H) by the period L
It becomes a level.

Further, a signal obtained by inverting the phase of the NAND gate output (H) and the time delay output (F) by the inverter 31 {(I) in the same figure)
By supplying it to the RS flip-flop 32 together with the reference}, its output becomes as shown in FIG. 9 (J), and is supplied to the switch circuit Sw as the final synchronization detection control voltage. As a result, the clock signal is switched from C ₀ (t) to C ′ (t) and supplied to the spread code generator 18, and the spread code that matches the spread code P (t) in the received SS modulated wave. P
(t) is obtained.

As a result, the original despread demodulation operation is achieved in the multiplier 10, and its output is f (t) P (t) P (t) + P (t).
n (t). As is well known, since P (t) P (t), which is a multiplication of spread codes, is a DC component that is almost 1, the BPF is
The output of 11 is f (t) + N (t). Note that N (t) is P
(t) n (t) is a band-limited spread noise component and its noise power is very small. Therefore, the output of the VCO 17 of the phase-locked loop type angle demodulation circuit 13 also has a greatly reduced jitter, and the phase-locked loop type angle demodulation The SS synchronization hold in the circuit 13 also operates stably, and high-quality demodulated voice and demodulation information containing almost no jitter component are output from the output terminal Out via the LPF 24.

[0024]

According to the demodulator in the SS system of the present invention, the synchronization detection control voltage is obtained while performing the logical operation based on the output signals from the clock signal generator 21, the frequency divider 20, and the synchronization detection circuit 23. Therefore, even if the clock signal is switched to a jittery signal due to the jitter generated in the VCO, the phase detection point of the clock signal is instantaneously detected and coincides with the center of the correlation point. Since it is switched by, the fixed phase is always fixed to the best phase {the phase of the generated spread code for despread demodulating the input SS modulated wave} after the synchronization acquisition, and the spread code component leaked from the angle demodulation output is minimized. It has an excellent feature that good angle demodulation of N is stably achieved.

[Brief description of drawings]

FIG. 1 is a block diagram of an SS modulator (transmission unit) that supplies a signal to a conventional device and the device of the present invention.

FIG. 2 is a block configuration diagram of a conventional SS demodulation device.

FIG. 3 is a signal waveform diagram for explaining the operation of the conventional device.

FIG. 4 is a block diagram showing an embodiment of an SS demodulation device of the present invention.

FIG. 5 is a signal waveform diagram (timing chart) for explaining the operation of the device of the present invention.

[Explanation of symbols]

 2 Spread spectrum demodulator 3,10,14 Multiplier (phase comparator) 4,20 Frequency divider 5,18 PNG (spread code generator) 6,19,24 LPF (low-pass filter) 7,8 Antenna 9 , 11 BPF (bandpass filter) 12 Limiter amplifier 13 Phase-locked loop type angle demodulation circuit 15 Amplifier 16 Loop filter 17 VCO (voltage controlled oscillator) 21 Clock signal generator 23 Synchronization detection circuit 26 AND gate 27 Shaping circuit 28 Time delay circuit 29 EX-OR gate 30 NAND gate 31 Inverter 32 RS flip-flop 33 Synchronization acquisition signal generation unit Sw switch circuit

Claims (2)

[Claims] 1. A spread spectrum modulated wave for modulating an information signal such as an audio signal or data, in which a carrier frequency for primary modulation and a clock signal for spread code are in a synchronous relationship for receiving and demodulating. A demodulator in a spread spectrum system, in which a received spread spectrum modulated wave is input, a despread demodulation circuit that performs an inverse spread demodulation using a demodulating spread code to obtain an angle modulated wave, and the obtained angle modulated wave are input. Phase-locked loop type angle demodulation circuit for performing angle demodulation and a clock for spreading code generation by dividing the voltage-controlled oscillation output output from the voltage-controlled oscillator in the phase-locked loop type angle demodulation circuit into 1 / N A frequency divider for obtaining a signal, a spreading code generator for generating a spreading code for demodulation based on the clock signal and supplying the code to the despreading demodulation circuit, the carrier frequency and a clock for the spreading code. Synchronization acquisition clock signal generator for generating a clock signal for acquiring synchronization with the signal, a switch circuit for switching and selecting the synchronization acquisition clock signal and the spread code generation clock signal, and the phase locked loop Synchronization detection circuit that detects a synchronization acquisition point from the demodulation signal output from the angle demodulation circuit, and a synchronization acquisition signal using the synchronization detection circuit output, the synchronization acquisition clock signal, and the spread code generation clock signal. And a synchronization acquisition signal generation unit for generating,
A demodulation device in a spread spectrum system, characterized in that the switch circuit is switched by the obtained synchronization acquisition signal to perform spread spectrum synchronization acquisition. 2. A synchronization acquisition signal generation section for detecting a phase coincidence output of both signals by performing a logical sum operation of a spread code generation clock signal and a synchronization acquisition clock signal.
AND gate, a shaping circuit for shaping the output of the AND gate, and a second AND for performing an OR operation with the output of the shaping circuit by obtaining an impulse output that coincides with the correlation peak point from the output of the synchronization detection circuit. (Or NAND) gate, a time delay circuit for delaying the synchronization detection output, a delay synchronization detection output obtained by the delay, and the second AND (or NAND) gate output to drive the switch circuit. The demodulation device in the spread spectrum system according to claim 1, comprising an RS flip-flop that outputs a synchronization acquisition signal for switching.