JPH05347520A - Variable amplification factor analog amplifier device - Google Patents

Abstract

PURPOSE:To realize the conversion for making high accuracy and a high frequency band in an variable amplification factor analog amplifier device being a gain block. CONSTITUTION:For instance, the digital signal of 4 bits from a CPU is decoded by a decoder DEC1, by which one of analog switches SW1-SW16 for selecting a resistance is selected. Also, the digital signal of 4 bits from the CPU is decoded simultaneously by a decoder DEC2. Also, this device is constituted so that the value of a suitable feedback capacitor is determined by selecting analog switches SW21-SW27 for selecting the feedback capacitor for a feedback capacitance setting part 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification factor variable analog amplification device called a gain block which is suitable for servo control of an optical disk device, for example.

[0002]

2. Description of the Related Art A conventional gain block is shown in FIG.
As shown in, the resistance R and the switch SW are inserted in series between the inverting input terminal and the output terminal of the operational amplifier (OP1), and the number of steps to change the resistance R and the switch SW (for example, 16).
Only the corresponding portion is prepared and configured on a printed circuit board, or as shown in FIG. 5, it is configured by an operational amplifier OP1 and an 8-bit resistance ladder DA converter (DAC).

In any of these gain blocks, an analog signal is input from an analog input terminal and a gain is switched from a digital input terminal.

However, both gain blocks are individual elements, and even if highly accurate resistors are used,
The input capacitance of the operational amplifier is increased by the wiring capacitance connecting each element, the capacitance of the bonding wire portion, etc. Therefore, it is not possible to realize a high gain accuracy and a wide band gain block.

Further, when the latter gain block is to be implemented as an LSI, a large number of analog switches exist in the DAC (256 in the case of an 8-bit DAC).
This will increase the input capacitance of the operational amplifier. Even if the stability of the amplifier can be obtained by inserting the feedback capacitance, a considerably large feedback capacitance is required, which causes a problem that the time constant of the amplifier becomes large (phase error becomes large).

[0006]

As described above, in the related art, variations in resistance accuracy and a large number of switches cause an increase in the input capacitance of an operational amplifier, resulting in deterioration of response time and frequency characteristics. However, there is a drawback that it is difficult to make an LSI. Therefore, the present invention is highly accurate,
It is an object of the present invention to provide a variable amplification factor analog amplifying device that can realize a high band and can reduce the cost of an LSI.

[0007]

In order to achieve the above object, in the variable amplification factor analog amplifying device of the present invention, a plurality of input resistors connected in series and each of the input resistors are selected. A plurality of analog switches provided for the purpose of selection, a selection means for controlling the analog switch to select one of the input resistances, and an amplification factor variable according to the input resistance selected by the selection means. It is composed of an operational amplifier.

Further, in the variable amplification factor analog amplifier device of the present invention, a plurality of input resistors connected in series,
A plurality of analog switches provided to select each of the input resistances, selection means for controlling the analog switches to select one of the input resistances, and the input resistances selected by the selection means. And an deciding means for deciding a feedback capacitance with respect to the amplification factor of the input resistance selected by the selecting means.

Further, in the variable amplification factor analog amplifying device of the present invention, a plurality of input resistors connected in series, a plurality of analog switches provided for selecting each of the input resistors, and the analog switch. Selection means for controlling one of the input resistances by controlling a switch, an operational amplifier having an amplification factor variable according to the input resistance selected by the selection means, and a plurality of feedback capacitors are provided. Switching means for switching the feedback capacitance in conjunction with the selection of the input resistance by the means.

[0010]

According to the present invention, the wiring capacitance between the respective elements and the capacitance of the bonding wire portion due to the LSI can be reduced by the means described above, so that the input capacitance of the operational amplifier can be greatly reduced. It is a thing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic configuration of a gain block according to the present invention.

That is, this gain block has an operational amplifier OP whose voltage at the non-inverting input terminal is + 2.5V.
1. A plurality of serially connected output terminals 12 and analog input terminals 11 of the operational amplifier OP1 (here,
17 resistors for gain setting R1 to R17, each resistor R
Analog switches SW1 to SW16 for resistance selection connected in parallel between the connection points of 1 to R17 and the inverting input terminal of the operational amplifier OP1, and provided between the inverting input terminal of the operational amplifier OP1 and the analog output terminal 12. The feedback capacitance setting unit 13 and the decoder DEC1 for decoding the 4-bit digital input from the CPU (not shown) and selecting one of the resistance selection analog switches SW1 to SW16, and the feedback described above. Capacity setting part 1
It is composed of a decoder DEC2 that determines the feedback capacitance of the H.3.

The feedback capacitance setting section 13 connects, for example, eight feedback capacitors C1 to C8 in parallel, and of the feedback capacitors C1 to C8, the feedback capacitor C
Except for 8, there are seven feedback capacitors C1 to C7 and seven feedback capacitor selecting analog switches SW21 to SW27 which are connected in series, respectively.

Thus, the 4-bit digital signal from the CPU is decoded by the decoder DEC1, and the analog switches SW1 to SW16 for resistance selection are thereby obtained.
Is selected. Further, the 4-bit digital signal from the CPU is simultaneously decoded by the decoder DEC2, whereby the feedback capacitor selecting analog switches SW21 to SW27 of the feedback capacitor setting unit 13 are selected and the appropriate value of the feedback capacitor is determined. It

In this embodiment, each of the analog switches SW1 to SW17 and SW21 to SW27 is composed of an N-channel MOS and a P-channel MOS, and is N-type.
The performance of the analog switch is improved by adjusting the channel width and channel length of the polysilicon gates that form the gates of the channel MOS and the P channel MOS.

With such a configuration, when the LSI is formed, the wiring capacitance connecting the respective elements and the capacitance of the bonding wire portion can be reduced, so that the input capacitance of the operational amplifier can be greatly reduced, and thus the high capacitance can be achieved. It is possible to realize a high-gain gain block with high accuracy.

Moreover, not only the input capacitance of the operational amplifier is reduced, but also the chip area of the LSI can be reduced by making the resistance values uniform and sharing the gain resistance, so that the cost can be reduced.

In particular, since the input capacitance of the operational amplifier cannot be reduced to zero even if the above-mentioned improvements are made, by optimizing the feedback capacitance to be a variable capacitance, the stability of the amplifier is improved and the phase error becomes large. We are trying to improve the accuracy. FIG. 2 shows an example in which the above gain block is applied to a focus servo system of an optical disk drive.

This system is a standard in the axial direction of an optical disk defined by ISO (International Organization for Standardization) [amount of surface runout ± 261.
The following (including the accuracy of the rotary motor turntable): Surface runout acceleration ± 10 m / s ² In the following, at 30 Hz], the focus of the light spot is made to follow within a certain range.

That is, the present focus servo system is an AGC for keeping the amplitude of the focus error signal obtained from the reflected light from the optical disk (not shown) constant.
(Auto gain control) circuit 21, gain blocks 22 and 5dBu for correcting loop gain to a constant value
p amplifier 23, phase lead compensation filter 24, constant current drive circuit 25, focus actuator 26 that drives an objective lens (not shown) in the optical axis direction to keep the distance from the optical disk constant, and subtracter 27, etc. It consists of

In this case, the gain block 22, the amplifier 23, and the phase lead compensation filter 24 are integrated into an LSI. For convenience, photoelectric conversion before IGC and I
The / V conversion and the like are omitted.

When the focus error signal is supplied, the AGC circuit 21 first shifts the level. Then, the output is finely adjusted by a gain block 22 fixed to a certain gain, and then an amplifier 23
The signal is amplified by and is supplied to the constant current drive circuit 25 via the phase lead compensation filter 24. By driving the focus actuator 26 with the output of the drive circuit 25, the objective lens is moved in the optical axis direction.

Here, the drive amount of the actuator 26 is fed back to the subtractor 27 to obtain the difference from the focus error signal, so that the difference is converged, that is, the light spot on the optical disk is always just in focus. Thus, it works so that the output is constant (fixed). FIG. 3 shows an example in which the above gain block is applied to a radial (or tracking) servo system of an optical disk drive.

This system is a standard in the radial direction of the optical disk defined by the above ISO [Eccentricity 70 μmPP or less (including axis deviation between the rotary motor and the disk); Eccentric acceleration 3 m / s
² Below at 1800 r. p. m], the off-track amount of the light spot is made to follow within a certain range (trace mode), or the light spot is moved to a near track (for example, within 13 tracks) (jump mode), or at least 13 tracks apart. The optical head (not shown) is moved to another track (seek mode), and the optical head is retracted to the home position position (home position mode).

That is, the radial servo system of the present invention uses the AGC circuit 3 for making the amplitude of the track error signal constant.
1. A gain block 32 for correcting the loop gain to be constant, a phase lead compensation filter 33, a high pass filter 34, a constant current drive circuit 35, a galvanometer actuator 36 for driving a galvanometer mirror (not shown), and the above. A low-pass filter 37 to which the output of the phase lead compensation filter 33 is supplied, a gain block 38 for correcting the output of the AGC circuit 31, a comparator 39 to which the output of the gain block 38 is supplied, and a track cross signal (TCS). , A seek control circuit 41, a D / A converter 42, a gain block 43 for correcting the output of the D / A converter 42,
It comprises a constant current drive circuit 44 to which the output of the gain block 43 or the output of the low pass filter 37 is selectively inputted, a linear motor 45 for moving the optical head, a subtractor 46 and the like.

In this case, the above gain blocks 32, 3
8, 43, phase lead compensation filter 33, high pass filter 34, low pass filter 37, seek control circuit 41,
And the D / A converter 42 is implemented as an LSI.

In the trace mode, when the track error signal is supplied, the level is first shifted by the AGC circuit 31. Then, the output is finely adjusted by a gain block 32 fixed to a certain gain, and then supplied to a constant current drive circuit 35 via a phase lead compensation filter 33 and a high pass filter 34. By driving the galvanometer actuator 36 with the output of the drive circuit 35, the galvanometer mirror is moved in the direction orthogonal to the optical axis.

The output of the phase lead compensation filter 33 is input to the low pass filter 37 and further supplied to the constant current drive circuit 44. By driving the linear motor 45 with the output of the drive circuit 44, the optical head is moved in the direction orthogonal to the optical axis.

Here, the drive amounts of the actuator 36 and the linear motor 45 described above are fed back to the subtractor 46 to obtain the difference from the track error signal, so that the difference is converged, that is, the light is tracked on the track of the optical disk. It works so that the output is constant (fixed) so that the spot follows.

On the other hand, in the seek mode, when the track error signal is supplied, the level is first shifted by the AGC circuit 31. Then, the output is supplied to the seek control circuit 41 after the amplitude is normalized by the gain block 38 fixed to a certain gain and further binarized by the comparator 39.

The track cross signal is binarized by the comparator 40, and the binarized signal is sought control circuit 4.
The speed control signal is generated by being supplied to 1. This speed control signal is supplied to the linear motor 45 via the D / A converter 42, the gain block 43, and the constant current drive circuit 44. As a result, the optical head is moved to the target track in the radial direction of the optical disk, that is, across the track. The description of the home position mode is omitted because it has no direct relation to the present invention.

The gain block used for each servo system described above is basically for normalizing the amplitude of the input signal. Although the gain values to be obtained are different, the gain width is the same, The required gain width is predetermined at the time of manufacture according to the characteristics of the applied optical disk drive. With such a circuit configuration, it is possible to realize an optical disc drive capable of highly accurate and high-speed servo operation and seek operation. Of course, various modifications can be made without departing from the spirit of the invention.

[0033]

As described above in detail, according to the present invention, it is possible to provide a variable amplification factor analog amplifying device which can realize high precision and high bandwidth, and in particular, can reduce the cost of LSI.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a basic configuration of a gain block according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a case where the present invention is applied to a focus servo system of an optical disk drive as an example.

FIG. 3 is a block diagram showing a case where the invention is applied to a radial servo system of an optical disk drive as an example.

FIG. 4 is a view for explaining the conventional technique and its problems,
3 is a circuit diagram of a gain block including resistors and switches. FIG.

FIG. 5 is a circuit diagram of a gain block including an operational amplifier and a DAC.

[Explanation of symbols]

11 ... Analog input terminal, 12 ... Analog output terminal, 1
3 ... Feedback capacitance setting unit, OP1 ... Operational amplifier, R1 to R1
7 ... Resistors for gain setting, SW1 to SW16 ... Analog switches for resistance selection, DEC1, DEC2 ... Decoder, C
1 to C8 ... Feedback capacitors, SW21 to SW27 ... Analog switches for selecting feedback capacitors.

Claims (3)

[Claims] 1. A plurality of input resistances connected in series, a plurality of analog switches provided to select each of the input resistances, and controlling the analog switch to select one of the input resistances. An amplification factor variable analog amplification device comprising: a selection unit; and an operational amplifier whose amplification factor is variable according to the input resistance selected by the selection unit. 2. A plurality of input resistors connected in series, a plurality of analog switches provided for selecting each of the input resistors, and controlling the analog switch to select one of the input resistors. The selection means includes: an operational amplifier whose amplification factor is variable according to the input resistance selected by the selection means; and determination means for determining a feedback capacitance with respect to the amplification factor of the input resistance selected by the selection means. An amplification factor variable analog amplification device characterized in that 3. A plurality of input resistors connected in series, a plurality of analog switches provided for selecting each of the input resistors, and controlling the analog switch to select one of the input resistors. It has a selection means, an operational amplifier whose amplification factor is variable according to the input resistance selected by the selection means, and a plurality of feedback capacitances, and the feedback capacitance is linked with the selection of the input resistance by the selection means. An amplification factor variable analog amplification device comprising a switching means for switching.