JPH05344720A - Resonant dc-dc converter - Google Patents

Resonant dc-dc converter

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Publication number
JPH05344720A
JPH05344720A JP17734092A JP17734092A JPH05344720A JP H05344720 A JPH05344720 A JP H05344720A JP 17734092 A JP17734092 A JP 17734092A JP 17734092 A JP17734092 A JP 17734092A JP H05344720 A JPH05344720 A JP H05344720A
Authority
JP
Japan
Prior art keywords
field effect
effect transistor
resonance
resonance capacitor
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP17734092A
Other languages
Japanese (ja)
Inventor
Takayuki Taguchi
隆行 田口
Teruhi Satou
輝被 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Origin Electric Co Ltd
Original Assignee
Origin Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Origin Electric Co Ltd filed Critical Origin Electric Co Ltd
Priority to JP17734092A priority Critical patent/JPH05344720A/en
Publication of JPH05344720A publication Critical patent/JPH05344720A/en
Withdrawn legal-status Critical Current

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  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To enlarge the control range of a prallel drive system resonant DC-DC converter to maintain stable activity against rising of input voltage or light load. CONSTITUTION:A series circuit consisting of a primary winding of a transformer 2, resonant inductance 3 and field effect transistor 5 is connected between terminals of a DC power supply 1. A resonance capacitor 7 is connected between of the field effect transistor 5. A series circuit consisting of a second resonant inductance 4 and a field effect transistor 6 is connected to the end of the primary of the transformer 2. A second resonance capacitor 8 is connected between main terminals of a field effect transistor 6. A third resonance capacitor 14 is connected to each drain of the field effect transistors 5 and 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【産業上の利用分野】本発明は,共振形DC−DCコン
バータ,特に並列駆動方式の共振形DC−DCコンバー
タに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resonance type DC-DC converter, and more particularly to a parallel drive type resonance DC-DC converter.

【従来の技術】共振形DC−DCコンバータはスイッチ
ング損失が小さく,低ノイズであることから高周波化に
適しており,電源の小型・軽量化に有効な回路方式とし
て注目されている。この共振形コンバータの電圧調整に
はスイッチング周波数を制御する方法が一般的に用いら
れているが,この方式ではスイッチング周波数の変化範
囲の最低周波数に対して出力フィルタを設計する必要が
あり,小型・軽量化に制限を与えるという欠点が残る。
そのため,固定周波数で出力電圧の調整が可能な回路方
式が共振形DC−DCコンバータの一つの課題となって
いる。この一つの方式として例えば,1989年9月8日に
電子情報通信学会技術研究報告〔電子通信用電源技術〕
PE89−26において発表された並列駆動方式電圧共振形D
C−DCコンバータがある。この並列駆動方式電圧共振
形DC−DCコンバータについて説明すると,図3にお
いて,1は直流電源でありその端子間には,変圧器2の
1次巻線21と,共振インダクタンス3と,第1のスイッ
チング素子である電界効果トランジスタ5とが直列接続
される。また変圧器2の1次巻線21の端部には,第2の
共振インダクタンス4と第2のスイッチング素子である
電界効果トランジスタ6との直列回路が並列接続されて
いる。第1のスイッチング素子である電界効果トランジ
スタ5のドレイン・ソース間には共振コンデンサ7が並
列接続され,同様に第2のスイッチング素子である電界
効果トランジスタ6のドレイン・ソース間に第2の共振
コンデンサ8が並列接続されている。変圧器2の2次側
巻線22には,整流ダイオード9と平滑用のコンデンサ10
が直列接続されている。平滑用のコンデンサ10の両端は
出力端子31,32 に接続される。この出力端子31,32 の電
圧は基準電圧と比較して誤差信号を増幅する比較・誤差
増幅回路11に接続される。この比較・誤差増幅回路11の
出力信号は発振回路13の信号を遅延させ電界効果トラン
ジスタ5と電界効果トランジスタ6との位相差を制御
し,電界効果トランジスタ6を駆動する位相制御回路12
に接続されている。電界効果トランジスタ5と電界効果
トランジスタ6は,発振回路13により固定周波数,固定
パルス幅で動作しており,出力電圧と基準電圧との誤差
信号を増幅する比較・誤差増幅回路11が電界効果トラン
ジスタ5と電界効果トランジスタ6の位相差を決定し出
力電圧を安定化する。第1のスイッチング素子である電
界効果トランジスタ5と,第2のスイッチング素子であ
る電界効果トランジスタ6との位相が一致したとき最大
出力となり,反対に位相をずらすほど出力は減少する。
2. Description of the Related Art A resonance type DC-DC converter is suitable for high frequency because of its small switching loss and low noise, and it has been attracting attention as a circuit system effective for reducing the size and weight of a power supply. A method of controlling the switching frequency is generally used for voltage adjustment of this resonant converter, but in this method, it is necessary to design an output filter for the lowest frequency in the change range of the switching frequency. The drawback remains that it limits weight reduction.
Therefore, a circuit method capable of adjusting the output voltage at a fixed frequency is one of the problems of the resonance type DC-DC converter. As one method of this, for example, on September 8, 1989, the Institute of Electronics, Information and Communication Engineers Technical Research Report [Power Technology for Electronic Communications]
Parallel drive type voltage resonance type D announced at PE89-26
There is a C-DC converter. This parallel drive type voltage resonance type DC-DC converter will be explained. In FIG. 3, reference numeral 1 is a DC power source, and between its terminals, the primary winding 21 of the transformer 2, the resonance inductance 3 and the first winding 21. The field effect transistor 5, which is a switching element, is connected in series. At the end of the primary winding 21 of the transformer 2, a series circuit of a second resonance inductance 4 and a field effect transistor 6 which is a second switching element is connected in parallel. A resonance capacitor 7 is connected in parallel between the drain and the source of the field effect transistor 5 which is the first switching element, and a second resonance capacitor is similarly connected between the drain and the source of the field effect transistor 6 which is the second switching element. 8 are connected in parallel. The secondary winding 22 of the transformer 2 includes a rectifying diode 9 and a smoothing capacitor 10
Are connected in series. Both ends of the smoothing capacitor 10 are connected to the output terminals 31 and 32. The voltages at the output terminals 31 and 32 are connected to a comparison / error amplification circuit 11 that amplifies the error signal by comparing it with a reference voltage. The output signal of the comparison / error amplification circuit 11 delays the signal of the oscillation circuit 13 to control the phase difference between the field effect transistor 5 and the field effect transistor 6, and drives the field effect transistor 6.
It is connected to the. The field effect transistor 5 and the field effect transistor 6 operate at a fixed frequency and a fixed pulse width by the oscillation circuit 13, and the comparison / error amplification circuit 11 that amplifies the error signal between the output voltage and the reference voltage has the field effect transistor 5. And the phase difference between the field effect transistor 6 and the output voltage is stabilized. When the phase of the field effect transistor 5 which is the first switching element and the field effect transistor 6 which is the second switching element match, the maximum output is obtained, and on the contrary, the output is reduced as the phases are shifted.

【発明が解決しようする課題】しかしながら,このよう
な従来の固定周波数で動作する並列駆動方式電圧共振形
DC−DCコンバータの制御方法は,2つのスイッチン
グ素子の位相差を制御しており,この制御範囲は2つの
スイッチング素子のうちどちらかがオフしているとき変
圧器の2次側に電力を供給するので2つのスイッチング
素子のオフが重なり合う範囲が動作範囲となる。この制
御範囲を逸脱すると伝達電力はほぼ一定になり制御不能
となる。したがって入力電圧の上昇や負荷が軽くなると
制御範囲を逸脱し出力電圧が上昇してしまうという問題
があった。本発明は,並列駆動方式電圧共振形DC−D
Cコンバータの制御範囲を拡げて,入力電圧の上昇や軽
負荷に対しても安定動作を保つことを課題とする。
However, such a conventional control method for a parallel drive type voltage resonance type DC-DC converter operating at a fixed frequency controls the phase difference between two switching elements. Since the power is supplied to the secondary side of the transformer when one of the two switching elements is off, the operating range is the range where the two switching elements are off. If it deviates from this control range, the transmitted power becomes almost constant and control becomes impossible. Therefore, there is a problem that when the input voltage rises or the load becomes lighter, the output voltage rises outside the control range. The present invention is a parallel drive type voltage resonance type DC-D.
An object is to expand the control range of the C converter and maintain stable operation even when the input voltage rises and the load is light.

【課題を解決するための手段】この課題を解決するた
め,本発明では,並列駆動方式電圧共振形DC−DCコ
ンバータの2つの共振コンデンサ間に第3の共振コンデ
ンサを付加することにより2つのスイッチング素子の位
相差に応じて共振容量を等価的に変化させることで2つ
スイッチング素子の位相を大きくずらすことなく出力電
圧を安定に制御可能とするものである。
In order to solve this problem, according to the present invention, by adding a third resonance capacitor between two resonance capacitors of a parallel drive type voltage resonance type DC-DC converter, two switching circuits are provided. By equivalently changing the resonance capacitance according to the phase difference between the elements, the output voltage can be stably controlled without significantly shifting the phases of the two switching elements.

【実施例】図1は,本発明の一実施例を示すものであ
り,以下同図にもとづいて説明する。図において1は直
流電源でありその端子間には,変圧器2の1次巻線21,
共振インダクタンス3,第1のスイッチング素子たる電
界効果トランジスタ5が直列接続され,さらに共振イン
ダクタンス4と第2のスイッチング素子たる電界効果ト
ランジスタ6の直列回路が,変圧器2の1次巻線21の端
部に並列接続されている。電界効果トランジスタ5のド
レイン・ソース間に共振コンデンサ7が並列接続され,
同様に電界効果トランジスタ6のドレイン・ソース間に
第2の共振コンデンサ8が並列接続されている。さら
に,電界効果トランジスタ5のドレインと電界効果トラ
ンジスタ6のドレイン間に第3の共振コンデンサ14が接
続されている。変圧器2の2次側巻線22には,整流ダイ
オード9と平滑コンデンサ10が直列接続されている。平
滑コンデンサ10の電圧と基準電圧との誤差信号を増幅す
る誤差増幅回路11と,誤差増幅回路11の信号で発振器13
の信号を遅延させ,電界効果トランジスタ5と電界効果
トランジスタ6との位相差を制御し電界効果トランジス
タ6を駆動する位相制御回路12が発振器13と電界効果ト
ランジスタ6のゲートの間に接続されている。電界効果
トランジスタ5と電界効果トランジスタ6は,発振器13
により固定周波数,固定パルス幅で動作する。出力電圧
と基準電圧との誤差信号を増幅する誤差増幅回路11が電
界効果トランジスタ5と電界効果トランジスタ6の位相
差を決定し出力電圧を安定化する。電界効果トランジス
タ5と電界効果トランジスタ6との位相が一致したとき
最大出力となり,反対に位相をずらすほど出力が減少す
る。動作をさらに詳細に説明する。図2は本発明の共振
形DC−DCコンバータの2つスイッチング素子たる電
界効果トランジスタ5,6の位相差が零でないときの動
作モード別の1次側等価回路を示す。なお,2つの電界
効果トランジスタ5,6の位相差が零の時の動作は,単
一のスイッチング素子を有する通常の共振形コンバータ
となるので,説明は割愛する。モード1は,電界効果ト
ランジスタ5,6が共にオンしているときの1次側等価
回路である。モード2は,電界効果トランジスタ5がオ
フ,電界効果トランジスタ6がオンのときの1次側等価
回路である。ここで,第3の共振コンデンサ14は,第1
の共振コンデンサ7と並列接続となり,第1の共振イン
ダクタンス3と第1の共振コンデンサ7との共振周波数
は,低くなる。モード3は,電界効果トランジスタ5,
6が共にオフしたときの1次側等価回路である。このと
き,第3の共振コンデンサ14は,第1の共振コンデンサ
7との接点の方が電圧が高くなっている。モード4は,
電界効果トランジスタ5,6が共にオフしたときの1次
側等価回路で第3の共振コンデンサ14の電圧がモード3
と逆極性のときである。モード4,5においては,第1
の共振コンデンサと第2の共振コンデンサの電圧差が変
化することによって,第3の共振コンデンサ14が共振現
象に関わってくる。モード5は,電界効果トランジスタ
5がオン,電界効果トランジスタ6がオフしているとき
の1次側等価回路である。このとき第3の共振コンデン
サ14は,第2の共振コンデンサ8と並列接続となり,第
2の共振インダクタンス4と第2の共振コンデンサ8と
の共振回路の共振周波数は低くなる。このあとモード1
に戻り,モード1からモード5までの動作が繰り返され
る。これらの全モードのうち,モード4,5において
は,第1の共振コンデンサ7と第2の共振コンデンサ8
の電圧差が変化することによって,第3の共振コンデン
サ14が共振現象に関わってくる。モード2からモード5
においては,2つの電界効果トランジスタ5,6の位相
差により第1の共振コンデンサ7と第2の共振コンデン
サ8とに電位差が生じ,第3の共振コンデンサ14に電荷
が蓄えられる。位相差が大きくなるほど第3の共振コン
デンサ14に電荷が蓄えられる時間が多くなる。つまり,
位相差が大きくなると第3の共振コンデンサ14が共振現
象に関与する時間が多くなり,共振回路を総合的にみる
と位相差が大きくなるほど共振容量が等価的に大きくな
っていると考えられる。共振容量が大きくなると共振周
波数が低くなり2つの電界効果トランジスタ5,6のオ
フ時間が長くなる。従って,固定周波数で動作している
場合変圧器2の1次巻線21に蓄えられるエネルギー量が
減り,出力電力も減る。位相差が大きいときの状況とし
ては,負荷が軽いときや入力電圧が高いときが考えられ
る。このようなときに第3の共振コンデンサ14によっ
て,共振容量を等価的に大きくして出力電力を減らし2
つの電界効果トランジスタ5,6の位相差を大きくしな
くても出力電圧の制御が可能となる。このことにより,
出力電圧の制御可能範囲を広くしたり,2つのスイッチ
ング素子の位相差によって起こる問題,例えば2つのス
イッチング素子間に流れる循環電流による電力損失の発
生や共振電圧の過大等を防止できる。
FIG. 1 shows an embodiment of the present invention, which will be described below with reference to FIG. In the figure, 1 is a DC power supply, and between its terminals, the primary winding 21 of the transformer 2,
The resonance inductance 3 and the field effect transistor 5 as the first switching element are connected in series, and the series circuit of the resonance inductance 4 and the field effect transistor 6 as the second switching element is connected to the end of the primary winding 21 of the transformer 2. Are connected in parallel. A resonance capacitor 7 is connected in parallel between the drain and source of the field effect transistor 5,
Similarly, the second resonance capacitor 8 is connected in parallel between the drain and source of the field effect transistor 6. Further, a third resonance capacitor 14 is connected between the drain of the field effect transistor 5 and the drain of the field effect transistor 6. A rectifier diode 9 and a smoothing capacitor 10 are connected in series to the secondary winding 22 of the transformer 2. An error amplification circuit 11 that amplifies an error signal between the voltage of the smoothing capacitor 10 and the reference voltage, and an oscillator 13 based on the signal of the error amplification circuit 11.
A phase control circuit 12 for delaying the signal of FIG. 1 and controlling the phase difference between the field effect transistor 5 and the field effect transistor 6 to drive the field effect transistor 6 is connected between the oscillator 13 and the gate of the field effect transistor 6. .. The field effect transistor 5 and the field effect transistor 6 are the oscillator 13
Operates with a fixed frequency and a fixed pulse width. An error amplification circuit 11 that amplifies an error signal between the output voltage and the reference voltage determines the phase difference between the field effect transistor 5 and the field effect transistor 6 and stabilizes the output voltage. The maximum output is obtained when the phases of the field effect transistor 5 and the field effect transistor 6 match, and conversely, the output decreases as the phases are shifted. The operation will be described in more detail. FIG. 2 shows a primary side equivalent circuit for each operation mode when the phase difference between the field effect transistors 5 and 6 which are two switching elements of the resonance type DC-DC converter of the present invention is not zero. The operation when the phase difference between the two field effect transistors 5 and 6 is zero is a normal resonance type converter having a single switching element, and therefore the description thereof is omitted. Mode 1 is a primary side equivalent circuit when the field effect transistors 5 and 6 are both turned on. Mode 2 is a primary side equivalent circuit when the field effect transistor 5 is off and the field effect transistor 6 is on. Here, the third resonant capacitor 14 is
And the resonance frequency of the first resonance inductance 3 and the first resonance capacitor 7 becomes low. Mode 3 is a field effect transistor 5,
6 is an equivalent circuit of the primary side when both 6 are turned off. At this time, the third resonance capacitor 14 has a higher voltage at the contact point with the first resonance capacitor 7. Mode 4 is
In the equivalent circuit of the primary side when the field effect transistors 5 and 6 are both turned off, the voltage of the third resonance capacitor 14 is in mode 3
And the opposite polarity. In modes 4 and 5, the first
By changing the voltage difference between the second resonance capacitor and the second resonance capacitor, the third resonance capacitor 14 is involved in the resonance phenomenon. Mode 5 is a primary side equivalent circuit when the field effect transistor 5 is on and the field effect transistor 6 is off. At this time, the third resonance capacitor 14 is connected in parallel with the second resonance capacitor 8, and the resonance frequency of the resonance circuit of the second resonance inductance 4 and the second resonance capacitor 8 becomes low. After this mode 1
Then, the operation from mode 1 to mode 5 is repeated. In all of these modes, in modes 4 and 5, the first resonant capacitor 7 and the second resonant capacitor 8
The third resonance capacitor 14 is involved in the resonance phenomenon due to the change in the voltage difference between the third resonance capacitor 14 and the third resonance capacitor 14. Mode 2 to Mode 5
In, the potential difference is generated between the first resonance capacitor 7 and the second resonance capacitor 8 due to the phase difference between the two field effect transistors 5 and 6, and the electric charge is stored in the third resonance capacitor 14. The larger the phase difference, the more time the charge is stored in the third resonance capacitor 14. That is,
As the phase difference increases, the time taken for the third resonance capacitor 14 to participate in the resonance phenomenon increases, and it is considered that the resonance capacitance is equivalently increased as the phase difference increases when the resonance circuit is viewed comprehensively. When the resonance capacitance is large, the resonance frequency is low and the off-time of the two field effect transistors 5 and 6 is long. Therefore, when operating at a fixed frequency, the amount of energy stored in the primary winding 21 of the transformer 2 decreases and the output power also decreases. The situation when the phase difference is large may be when the load is light or when the input voltage is high. In such a case, the resonance capacitance is equivalently increased by the third resonance capacitor 14 to reduce the output power.
The output voltage can be controlled without increasing the phase difference between the two field effect transistors 5 and 6. By this,
It is possible to widen the controllable range of the output voltage and prevent problems caused by the phase difference between the two switching elements, for example, generation of power loss due to circulating current flowing between the two switching elements and excessive resonance voltage.

【発明の効果】以上説明してきたように,本発明によれ
ば,2つのスイッチング素子の位相差を制御することに
より出力電圧を安定化する固定周波数の並列駆動方式の
共振形DC−DCコンバータにおいて,第3の共振コン
デンサを付加することにより出力電圧の制御可能範囲を
広くしたり,スイッチング素子の位相差によって起こる
問題を改善できる。
As described above, according to the present invention, in a fixed frequency parallel drive type resonance DC-DC converter for stabilizing the output voltage by controlling the phase difference between two switching elements. By adding the third resonance capacitor, the controllable range of the output voltage can be widened and the problems caused by the phase difference of the switching elements can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る共振形DC−DCコンバータの一
実施例の回路図である。
FIG. 1 is a circuit diagram of an embodiment of a resonance type DC-DC converter according to the present invention.

【図2】図1に示す回路の動作モード別1次側等価回路
である。
FIG. 2 is a primary-side equivalent circuit for each operation mode of the circuit shown in FIG.

【図3】従来の並列駆動方式の共振形DC−DCコンバ
ータの回路図である。
FIG. 3 is a circuit diagram of a conventional parallel drive type resonant DC-DC converter.

【符号の説明】[Explanation of symbols]

1…直流電源 2…変圧器 3,4…共振イン
ダクタンス 5,6…電界効果トランジスタ 7,8…共振コン
デンサ 9…整流ダイオード 10…コンデンサ 11…比較・誤差増幅回路 12…位相制
御回路 13…発振回路 14…共振コンデンサ 31,32 …出力
端子
1 ... DC power supply 2 ... Transformer 3, 4 ... Resonance inductance 5, 6 ... Field effect transistor 7, 8 ... Resonance capacitor 9 ... Rectifier diode 10 ... Capacitor 11 ... Comparison / error amplification circuit 12 ... Phase control circuit 13 ... Oscillation circuit 14 ... Resonant capacitor 31, 32 ... Output terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 インダクタンスとコンデンサとスイッチ
ング素子とからなる共振スイッチを一対並列接続し,前
記一対のスイッチング素子を同一の周波数で駆動し,相
互の位相差により出力電力制御をする共振形DC−DC
コンバータにおいて,前記一対のコンデンサの端部に接
続された第3の共振コンデンサを備えてなることを特徴
とする共振形DC−DCコンバータ。
1. A resonance type DC-DC in which a pair of resonance switches composed of an inductance, a capacitor and a switching element are connected in parallel, the pair of switching elements are driven at the same frequency, and output power is controlled by the phase difference between them.
A resonant DC-DC converter comprising a third resonant capacitor connected to the ends of the pair of capacitors.
JP17734092A 1992-06-11 1992-06-11 Resonant dc-dc converter Withdrawn JPH05344720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17734092A JPH05344720A (en) 1992-06-11 1992-06-11 Resonant dc-dc converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17734092A JPH05344720A (en) 1992-06-11 1992-06-11 Resonant dc-dc converter

Publications (1)

Publication Number Publication Date
JPH05344720A true JPH05344720A (en) 1993-12-24

Family

ID=16029258

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17734092A Withdrawn JPH05344720A (en) 1992-06-11 1992-06-11 Resonant dc-dc converter

Country Status (1)

Country Link
JP (1) JPH05344720A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102594103A (en) * 2012-03-20 2012-07-18 思源清能电气电子有限公司 High-voltage input fly-back topology-based series-wound field effect tube driving circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102594103A (en) * 2012-03-20 2012-07-18 思源清能电气电子有限公司 High-voltage input fly-back topology-based series-wound field effect tube driving circuit

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A300 Withdrawal of application because of no request for examination

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Effective date: 19990831