JPH05343981A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

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Publication number
JPH05343981A
JPH05343981A JP15191292A JP15191292A JPH05343981A JP H05343981 A JPH05343981 A JP H05343981A JP 15191292 A JP15191292 A JP 15191292A JP 15191292 A JP15191292 A JP 15191292A JP H05343981 A JPH05343981 A JP H05343981A
Authority
JP
Japan
Prior art keywords
circuit
semiconductor integrated
integrated circuit
control
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15191292A
Other languages
Japanese (ja)
Inventor
Isao Shimotsuhama
功 下津浜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15191292A priority Critical patent/JPH05343981A/en
Publication of JPH05343981A publication Critical patent/JPH05343981A/en
Withdrawn legal-status Critical Current

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Abstract

PURPOSE:To obtain a semiconductor integrated circuit in which the influence of a switching characteristic of a logic circuit (delay time) on a temperature change through comparatively simple circuit configuration concerning to the semiconductor integrated circuit of an ECL circuit. CONSTITUTION:This semiconductor integrated circuit is provided with a logic level control circuit C in which when a potential at a control terminal (a) gets higher, a logic amplitude is smaller, and when the potential at the control terminal (a) gets lower, the logic amplitude is larger and with a control element D1 connecting in series with the control terminal (a) of the logic amplitude control circuit C, whose impedance is smaller as temperature gets higher, whose impedance is larger as temperature gets lower. Then the fluctuation in the output logic amplitude of the circuit due to a temperature change is cancelled by the control of the logic amplitude control circuit C due to an impedance change in the control element D1 to eliminate the temperature dependence of the switching characteristic of the circuit.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はECL(Emitter-Couple
d Logic )回路の半導体集積回路に係り、特に、論理回
路のスイッチング特性(遅延時間)の温度変化による影
響を無くした半導体集積回路に関する。
The present invention relates to an ECL (Emitter-Couple
d Logic) circuit semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that eliminates the influence of the temperature change of the switching characteristics (delay time) of the logic circuit.

【0002】半導体集積回路を構成する論理回路は、通
常、温度の変動に伴ってスイッチング特性も変動してし
まうという特性を持っている。この特性は、非常に特殊
な場合を除いて、半導体集積回路を使用する場合は問題
にならない場合が多い。しかしながら、半導体集積回路
の用途によっては、この特性が問題となる場合がある。
このような場合には、温度の変動によるスイッチング特
性(遅延時間)の変動をキャンセルする必要が生じてく
る。
A logic circuit that constitutes a semiconductor integrated circuit usually has a characteristic that switching characteristics also fluctuate with temperature fluctuations. This characteristic is often not a problem when using a semiconductor integrated circuit, except for very special cases. However, this characteristic may be a problem depending on the application of the semiconductor integrated circuit.
In such a case, it becomes necessary to cancel fluctuations in switching characteristics (delay time) due to temperature fluctuations.

【0003】[0003]

【従来の技術】従来より、電子機器において半導体集積
回路を使用する場合には、信号の論理処理がその半導体
集積回路の主たる機能であり、スイッチング特性(遅延
時間)が多少変動しても問題とならないような装置設計
がなされてきた。
2. Description of the Related Art Conventionally, when a semiconductor integrated circuit is used in electronic equipment, signal logic processing is the main function of the semiconductor integrated circuit, and even if the switching characteristics (delay time) fluctuates to some extent, there is a problem. The device design has been made so that it will not happen.

【0004】ところが、半導体集積回路の用途が広がっ
ていくにつれて、半導体集積回路のスイッチング特性
(遅延時間)そのものを利用するような装置設計がなさ
れる場合もでてきた。例えば、一定の決まった遅延時間
を補償する、或いは遅延時間をコントロールするような
半導体集積回路がこれである。このような半導体集積回
路では、遅延時間の絶対値の精度が要求されることにな
る。
However, as the applications of semiconductor integrated circuits have expanded, there have been cases where device design is made to utilize the switching characteristics (delay time) itself of the semiconductor integrated circuit. For example, this is a semiconductor integrated circuit that compensates for a certain fixed delay time or controls the delay time. In such a semiconductor integrated circuit, accuracy of the absolute value of the delay time is required.

【0005】高速な信号を処理する回路として代表的な
ECL回路では、温度の上昇と共に出力振幅が大きくな
り、スイッチング特性(遅延時間)が劣化する。出力振
幅が大きくなる原因は、内部バイアス回路の温度特性に
起因しており、内部バイアス回路を調整すれば温度に対
してスイッチング特性(遅延時間)が劣化しないような
特性にすることも可能である。
In an ECL circuit, which is a typical circuit for processing high-speed signals, the output amplitude increases as the temperature rises, and the switching characteristics (delay time) deteriorate. The cause of the large output amplitude is due to the temperature characteristic of the internal bias circuit, and if the internal bias circuit is adjusted, it is possible to make the characteristic such that the switching characteristic (delay time) does not deteriorate with temperature. ..

【0006】しかしながら、この内部バイアス回路の特
性は、入出力インタフェースレベルを決める重要なパラ
メータとなっており、これを調整するためには、入出力
回路と内部回路とを分けてバイアス回路を構成すること
が必要となり、回路構成も複雑になることが予想される
ため、通常、このような方法によって温度変動に対する
スイッチング特性の問題を解決することは行なわない。
However, the characteristic of the internal bias circuit is an important parameter for determining the input / output interface level, and in order to adjust this, the input / output circuit and the internal circuit are separated to form the bias circuit. Since it is expected that the circuit configuration will be complicated and the circuit configuration will be complicated, the problem of the switching characteristic with respect to temperature fluctuation is not usually solved by such a method.

【0007】[0007]

【発明が解決しようとする課題】以上のように、従来の
半導体集積回路では、温度変動に対するスイッチング特
性(遅延時間)の変動をキャンセルするための適切な方
法がなく、例えばECL回路においても、内部バイアス
回路の特性を調整する方法が考えられるが、入出力イン
タフェースレベルへの影響から回路構成が複雑になると
いう問題があった。
As described above, in the conventional semiconductor integrated circuit, there is no suitable method for canceling the fluctuation of the switching characteristic (delay time) with respect to the temperature fluctuation. For example, even in the ECL circuit, the internal Although a method of adjusting the characteristics of the bias circuit can be considered, there is a problem that the circuit configuration becomes complicated due to the influence on the input / output interface level.

【0008】本発明は、上記問題点を解決するもので、
比較的簡単な回路構成で、論理回路のスイッチング特性
(遅延時間)の温度変化による影響を無くした半導体集
積回路を提供することを目的とする。
The present invention solves the above problems,
An object of the present invention is to provide a semiconductor integrated circuit which has a relatively simple circuit configuration and is free from the influence of the temperature change of the switching characteristics (delay time) of the logic circuit.

【0009】[0009]

【課題を解決するための手段】上記課題を解決するため
に、本発明の第1の特徴の半導体集積回路は、図1また
は図3に示す如く、回路出力の論理振幅を制御する論理
振幅制御回路Cを備えるECL回路の半導体集積回路で
あって、前記論理振幅制御回路Cの制御端子aに直列に
接続され、温度が高くなると該インピーダンスが小さく
なり、温度が低くなると該インピーダンスが大きくなる
制御素子D1またはR1を有して構成する。
In order to solve the above-mentioned problems, the semiconductor integrated circuit of the first feature of the present invention is, as shown in FIG. 1 or 3, a logic amplitude control for controlling the logic amplitude of the circuit output. A semiconductor integrated circuit of an ECL circuit including a circuit C, which is connected in series to a control terminal a of the logic amplitude control circuit C, the impedance decreases when the temperature rises, and the impedance increases when the temperature falls. It is configured to include the element D1 or R1.

【0010】本発明の第2の特徴の半導体集積回路は、
請求項1に記載の半導体集積回路において、前記論理振
幅制御回路Cは、制御端子aの電位が高くなると論理振
幅が小さくなり、制御端子aの電位が低くなると論理振
幅が大きくなる。
The semiconductor integrated circuit of the second feature of the present invention is
In the semiconductor integrated circuit according to claim 1, in the logic amplitude control circuit C, the logic amplitude decreases when the potential of the control terminal a increases, and the logic amplitude increases when the potential of the control terminal a decreases.

【0011】また、本発明の第3の特徴の半導体集積回
路は、請求項1または2に記載の半導体集積回路におい
て、図1に示す如く、前記制御素子は、ダイオードD1
である。
The semiconductor integrated circuit according to the third aspect of the present invention is the semiconductor integrated circuit according to claim 1 or 2, wherein the control element is a diode D1 as shown in FIG.
Is.

【0012】更に、本発明の第4の特徴の半導体集積回
路は、請求項1または2に記載の半導体集積回路におい
て、図3に示す如く、前記制御素子は、負の温度係数を
持つ抵抗R1である。
Furthermore, the semiconductor integrated circuit according to the fourth aspect of the present invention is the semiconductor integrated circuit according to claim 1 or 2, wherein the control element has a resistor R1 having a negative temperature coefficient as shown in FIG. Is.

【0013】[0013]

【作用】本発明の第1、第2、第3、及び第4の特徴の
半導体集積回路では、図1または図3に示す如く、出力
振幅可変用コントロール端子CTLを備えて、制御端子
aの電位が高くなると出力の論理振幅が小さくなり、制
御端子aの電位が低くなると出力の論理振幅が大きくな
る論理振幅制御回路Cを、差動ペアQ1及びQ2の負荷
側に構成し、温度が高くなると該インピーダンスが小さ
くなり、温度が低くなると該インピーダンスが大きくな
る制御素子として、ダイオードD1(図1)または負の
温度係数を持つ抵抗R1(図3)を、論理振幅制御回路
Cの制御端子aに直列に接続している。
In the semiconductor integrated circuit of the first, second, third and fourth features of the present invention, as shown in FIG. 1 or 3, the output amplitude varying control terminal CTL is provided and the control terminal a of the control terminal a is changed. The logic amplitude control circuit C, in which the logic amplitude of the output decreases when the potential increases and the logic amplitude of the output increases when the potential of the control terminal a decreases, is configured on the load side of the differential pair Q1 and Q2 to increase the temperature. As a control element in which the impedance decreases when the temperature decreases and the impedance increases when the temperature decreases, the diode D1 (FIG. 1) or the resistor R1 having a negative temperature coefficient (FIG. 3) is connected to the control terminal a of the logic amplitude control circuit C. Are connected in series.

【0014】温度が上昇すると、半導体集積回路の出力
の論理振幅は大きくなる傾向を持つが、一方で、制御素
子D1またはR1のインピーダンスが小さくなり、制御
端子aの電位を上げるため、論理振幅制御回路Cは出力
の論理振幅を小さくする方向に働く。従って、これら両
者の傾向により出力の論理振幅の変動が相殺され、スイ
ッチング特性(遅延時間)の変動も無くなり、スイッチ
ング特性(遅延時間)の温度依存性を無くすことが可能
となる。
When the temperature rises, the logic amplitude of the output of the semiconductor integrated circuit tends to increase. On the other hand, the impedance of the control element D1 or R1 decreases and the potential of the control terminal a increases, so that the logic amplitude control is performed. The circuit C works to reduce the logical amplitude of the output. Therefore, the fluctuations of the logical amplitude of the output are canceled by the tendency of both of them, the fluctuations of the switching characteristics (delay time) are also eliminated, and the temperature dependence of the switching characteristics (delay time) can be eliminated.

【0015】[0015]

【実施例】次に、本発明に係る実施例を図面に基づいて
説明する。 第1実施例 図1に本発明の第1実施例に係る半導体集積回路の回路
図を示す。
Embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 shows a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

【0016】同図において、本実施例の半導体集積回路
は、通常の差動ペアQ1及びQ2を有するECL回路に
対して、論理振幅制御回路C、ダイオードD1を具備し
た構成となっている。
In the figure, the semiconductor integrated circuit of this embodiment has a structure in which a logic amplitude control circuit C and a diode D1 are provided to an ECL circuit having a normal differential pair Q1 and Q2.

【0017】論理振幅制御回路Cは、トランジスタQ
8、Q9、及びQ10、並びに抵抗R2、R3、R4、
及びR5(R2<R3、R2=R4、R3=R5)から
構成され、出力振幅可変用コントロール端子CTLへの
入力電圧により、制御端子aの電位が高くなると出力の
論理振幅が小さくなり、制御端子aの電位が低くなると
出力の論理振幅が大きくなる。
The logic amplitude control circuit C includes a transistor Q
8, Q9, and Q10 and resistors R2, R3, R4,
And R5 (R2 <R3, R2 = R4, R3 = R5), the logical amplitude of the output decreases when the potential of the control terminal a increases due to the input voltage to the output amplitude varying control terminal CTL. The lower the potential of a, the larger the logical amplitude of the output.

【0018】また、ダイオードD1は、論理振幅制御回
路Cの制御端子aと出力振幅可変用コントロール端子C
TL間に接続され、温度が高くなるとインピーダンスが
小さくなり、温度が低くなるとインピーダンスが大きく
なる特性を持つ。
The diode D1 has a control terminal a of the logic amplitude control circuit C and a control terminal C for varying the output amplitude.
It is connected between TLs and has a characteristic that the impedance decreases as the temperature rises and the impedance increases as the temperature lowers.

【0019】先ず、出力振幅可変用コントロール端子C
TLの電位を固定し、ダイオードD1の両端の電圧が一
定である(或いは、ダイオードD1がない)とした場合
について考える。この場合、温度が上昇すると、図2
(1)の破線に示すように、半導体集積回路の出力の論
理振幅は大きくなる傾向を持つ。また、出力の論理振幅
が大きくなることによって、スイッチング特性(遅延時
間)も、図2(2)の破線に示すように変動(遅くな
る)する。
First, the output amplitude varying control terminal C
Consider a case where the potential of TL is fixed and the voltage across the diode D1 is constant (or there is no diode D1). In this case, if the temperature rises,
As indicated by the broken line in (1), the logic amplitude of the output of the semiconductor integrated circuit tends to increase. Further, the switching characteristic (delay time) also fluctuates (becomes slower) as shown by the broken line in FIG. 2 (2) due to the increase in the logical amplitude of the output.

【0020】次に、温度変化により、ダイオードD1の
インピーダンスが変動する(ダイオードD1が存在す
る)場合には、温度上昇に伴い、制御素子D1のインピ
ーダンスが小さくなり(両端の電圧が小さくなり)、制
御端子aの電位を上げるため、論理振幅制御回路Cは出
力の論理振幅を小さくする方向に働く。
Next, when the impedance of the diode D1 changes (the diode D1 exists) due to the temperature change, the impedance of the control element D1 becomes smaller (the voltage at both ends becomes smaller) as the temperature rises. In order to raise the potential of the control terminal a, the logic amplitude control circuit C works to reduce the logic amplitude of the output.

【0021】従って、出力の論理振幅の大きくなる傾向
(前者)は、論理振幅制御回路Cの制御によりキャンセ
ルされ(図2(1)の実線参照)、スイッチング特性
(遅延時間)の変動も無くなり(図2(2)の実線参
照)、スイッチング特性(遅延時間)の温度依存が無く
なる。 第2実施例 図3に本発明の第2実施例に係る半導体集積回路の回路
図を示す。
Therefore, the tendency that the logical amplitude of the output becomes large (the former) is canceled by the control of the logical amplitude control circuit C (see the solid line in FIG. 2A), and the fluctuation of the switching characteristic (delay time) also disappears ( 2 (see the solid line in FIG. 2), the temperature dependence of the switching characteristic (delay time) disappears. Second Embodiment FIG. 3 shows a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

【0022】本実施例の半導体集積回路は、第1実施例
において、制御素子として負の温度係数を持つ抵抗R1
を使用し、トランジスタQ8及びQ9、並びに抵抗R
2、R3、R4、及びR5(R2<R3、R2=R4、
R3=R5)から構成された論理振幅制御回路C’を使
用したものである。その特性作用は、第1実施例とほぼ
同等である。
In the semiconductor integrated circuit of this embodiment, the resistor R1 having a negative temperature coefficient is used as the control element in the first embodiment.
Using transistors Q8 and Q9 and a resistor R
2, R3, R4, and R5 (R2 <R3, R2 = R4,
The logic amplitude control circuit C ′ composed of R3 = R5) is used. The characteristic action is almost the same as that of the first embodiment.

【0023】[0023]

【発明の効果】以上説明したように、本発明によれば、
制御端子の電位が高くなると出力の論理振幅が小さくな
り、制御端子の電位が低くなると出力の論理振幅が大き
くなる論理振幅制御回路を、差動ペアの負荷側に構成
し、温度が高くなると該インピーダンスが小さく、温度
が低くなると該インピーダンスが大きくなる制御素子と
して、ダイオードまたは負の温度係数を持つ抵抗を論理
振幅制御回路Cの制御端子aに直列に接続した構成とし
たので、温度が上昇すると、半導体集積回路の出力の論
理振幅は大きくなる傾向を持つが、一方で、制御素子の
インピーダンスが小さくなり、制御端子の電位を上げる
ため、論理振幅制御回路は出力の論理振幅を小さくする
方向に働き、これら両者の傾向により出力の論理振幅の
変動が相殺され、スイッチング特性(遅延時間)の変動
も無くなり、スイッチング特性(遅延時間)の温度依存
性を無くすことが可能な半導体集積回路を提供すること
ができる。
As described above, according to the present invention,
When the potential of the control terminal becomes high, the logical amplitude of the output becomes small, and when the potential of the control terminal becomes low, the logical amplitude of the output becomes large. Since a diode or a resistor having a negative temperature coefficient is connected in series to the control terminal a of the logic amplitude control circuit C as a control element whose impedance is small and whose impedance increases when the temperature becomes low, when the temperature rises , The output of the semiconductor integrated circuit tends to have a large logical amplitude, but on the other hand, the impedance of the control element decreases and the potential of the control terminal rises, so the logical amplitude control circuit tends to reduce the logical amplitude of the output. The fluctuations in the output logical amplitude are canceled by these two tendencies, and the fluctuations in the switching characteristics (delay time) also disappear. It is possible to provide a semiconductor integrated circuit capable of eliminating the temperature dependency of the ring characteristics (delay time).

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例に係る半導体集積回路の回
路図である。
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

【図2】第1実施例の半導体集積回路の特性曲線であ
り、図2(1)は出力の論理振幅の温度特性、図2
(2)は出力の論理振幅変化に対する遅延時間の特性で
ある。
2 is a characteristic curve of the semiconductor integrated circuit of the first embodiment, FIG. 2 (1) shows a temperature characteristic of an output logical amplitude, and FIG.
(2) is the characteristic of the delay time with respect to the change in the logical amplitude of the output.

【図3】本発明の第2実施例に係る半導体集積回路の回
路図である。
FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

C,C’…論理振幅制御回路 D1…ダイオード(制御素子) R1…(負の温度係数を持つ)抵抗(制御素子) Q1〜Q10…トランジスタ R2〜R8…抵抗 Vcc,Vee…電源 A1,XA1…入力端子 X,Y…出力端子 CTL…出力振幅可変用コントロール端子 a…制御端子 C, C '... Logic amplitude control circuit D1 ... Diode (control element) R1 ... (having negative temperature coefficient) Resistance (control element) Q1-Q10 ... Transistors R2-R8 ... Resistors Vcc, Vee ... Power supplies A1, XA1 ... Input terminal X, Y ... Output terminal CTL ... Output amplitude variable control terminal a ... Control terminal

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 回路出力の論理振幅を制御する論理振幅
制御回路(C)を備えるECL回路の半導体集積回路で
あって、 前記論理振幅制御回路(C)の制御端子(a)に直列に
接続され、温度が高くなると該インピーダンスが小さく
なり、温度が低くなると該インピーダンスが大きくなる
制御素子(D1またはR1)を有することを特徴とする
半導体集積回路。
1. A semiconductor integrated circuit of an ECL circuit, comprising a logic amplitude control circuit (C) for controlling a logic amplitude of a circuit output, which is connected in series to a control terminal (a) of the logic amplitude control circuit (C). The semiconductor integrated circuit has a control element (D1 or R1) whose impedance decreases as the temperature rises and which increases as the temperature lowers.
【請求項2】 前記論理振幅制御回路(C)は、制御端
子(a)の電位が高くなると論理振幅が小さくなり、制
御端子(a)の電位が低くなると論理振幅が大きくなる
ことを特徴とする請求項1に記載の半導体集積回路。
2. The logic amplitude control circuit (C) is characterized in that the logic amplitude decreases when the potential of the control terminal (a) increases and the logic amplitude increases when the potential of the control terminal (a) decreases. The semiconductor integrated circuit according to claim 1.
【請求項3】 前記制御素子は、ダイオード(D1)で
あることを特徴とする請求項1または2に記載の半導体
集積回路。
3. The semiconductor integrated circuit according to claim 1, wherein the control element is a diode (D1).
【請求項4】 前記制御素子は、負の温度係数を持つ抵
抗(R1)であることを特徴とする請求項1または2に
記載の半導体集積回路。
4. The semiconductor integrated circuit according to claim 1, wherein the control element is a resistor (R1) having a negative temperature coefficient.
JP15191292A 1992-06-11 1992-06-11 Semiconductor integrated circuit Withdrawn JPH05343981A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15191292A JPH05343981A (en) 1992-06-11 1992-06-11 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15191292A JPH05343981A (en) 1992-06-11 1992-06-11 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH05343981A true JPH05343981A (en) 1993-12-24

Family

ID=15528916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15191292A Withdrawn JPH05343981A (en) 1992-06-11 1992-06-11 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH05343981A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411129B1 (en) * 2000-10-03 2002-06-25 Semiconductor Components Industries Llc Logic circuit with output high voltage boost and method of using

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411129B1 (en) * 2000-10-03 2002-06-25 Semiconductor Components Industries Llc Logic circuit with output high voltage boost and method of using

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